[ARC] Add finer details for LLOCK and SCOND

This patch changes the "class" of LLOCK/SCOND from "MEMORY" to
"LLOCK/SCOND" respectively. Moreover, it corrects the "data_size_mode".

These changes are necessary for GDB's atmoic sequence handler.

Signed-off-by: Shahab Vahedi <shahab@synopsys.com>

1 files changed, 21 insertions, 21 deletions

diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
index 17fa97a..10625f1 100644
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -9214,40 +9214,40 @@
 { "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { UIMM7_11_S }, { 0 }},
 
 /* llock<.di> b,c 00100bbb00101111DBBBCCCCCC010000.  */
-{ "llock", 0x202F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+{ "llock", 0x202F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LLOCK, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
 
 /* llock<.di> 0,c 0010011000101111D111CCCCCC010000.  */
-{ "llock", 0x262F7010, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+{ "llock", 0x262F7010, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LLOCK, NONE, { ZA, BRAKET, RC, BRAKETdup }, { C_DI16 }},
 
 /* llock<.di> b,u6 00100bbb01101111DBBBuuuuuu010000.  */
-{ "llock", 0x206F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+{ "llock", 0x206F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LLOCK, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
 
 /* llock<.di> 0,u6 0010011001101111D111uuuuuu010000.  */
-{ "llock", 0x266F7010, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+{ "llock", 0x266F7010, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LLOCK, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
 
 /* llock<.di> b,limm 00100bbb00101111DBBB111110010000.  */
-{ "llock", 0x202F0F90, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+{ "llock", 0x202F0F90, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LLOCK, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
 
 /* llock<.di> 0,limm 0010011000101111D111111110010000.  */
-{ "llock", 0x262F7F90, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+{ "llock", 0x262F7F90, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LLOCK, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
 
 /* llockd<.di> b,c 00100bbb00101111DBBBCCCCCC010010.  */
-{ "llockd", 0x202F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+{ "llockd", 0x202F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, LLOCK, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* llockd<.di> 0,c 0010011000101111D111CCCCCC010010.  */
-{ "llockd", 0x262F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+{ "llockd", 0x262F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, LLOCK, NONE, { ZA, BRAKET, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* llockd<.di> b,u6 00100bbb01101111DBBBuuuuuu010010.  */
-{ "llockd", 0x206F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+{ "llockd", 0x206F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, LLOCK, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* llockd<.di> 0,u6 0010011001101111D111uuuuuu010010.  */
-{ "llockd", 0x266F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+{ "llockd", 0x266F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, LLOCK, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* llockd<.di> b,limm 00100bbb00101111DBBB111110010010.  */
-{ "llockd", 0x202F0F92, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+{ "llockd", 0x202F0F92, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, LLOCK, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* llockd<.di> 0,limm 0010011000101111D111111110010010.  */
-{ "llockd", 0x262F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+{ "llockd", 0x262F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, LLOCK, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* lp s13 00100RRR101010000RRRssssssSSSSSS.  */
 { "lp", 0x20A80000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOOP, NONE, { SIMM13_A16_20 }, { 0 }},
@@ -15640,31 +15640,31 @@
 { "sbcs", 0x2EE77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
 
 /* scond<.di> b,c 00100bbb00101111DBBBCCCCCC010001.  */
-{ "scond", 0x202F0011, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+{ "scond", 0x202F0011, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SCOND, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
 
 /* scond<.di> b,u6 00100bbb01101111DBBBuuuuuu010001.  */
-{ "scond", 0x206F0011, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+{ "scond", 0x206F0011, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SCOND, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
 
 /* scond<.di> b,limm 00100bbb00101111DBBB111110010001.  */
-{ "scond", 0x202F0F91, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+{ "scond", 0x202F0F91, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SCOND, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
 
 /* scond<.di> limm,c 0010011000101111D111CCCCCC010001.  */
-{ "scond", 0x262F7011, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+{ "scond", 0x262F7011, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, SCOND, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_DI16 }},
 
 /* scond<.di> limm,u6 0010011001101111D111uuuuuu010001.  */
-{ "scond", 0x266F7011, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+{ "scond", 0x266F7011, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, SCOND, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
 
 /* scond<.di> limm,limm 0010011000101111D111111110010001.  */
-{ "scond", 0x262F7F91, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_DI16 }},
+{ "scond", 0x262F7F91, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, SCOND, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_DI16 }},
 
 /* scondd<.di> b,c 00100bbb00101111DBBBCCCCCC010011.  */
-{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, SCOND, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* scondd<.di> b,u6 00100bbb01101111DBBBuuuuuu010011.  */
-{ "scondd", 0x206F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+{ "scondd", 0x206F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, SCOND, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* scondd<.di> b,limm 00100bbb00101111DBBB111110010011.  */
-{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, SCOND, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* setacc a,b,c 00101bbb000011011BBBCCCCCCAAAAAA.  */
 { "setacc", 0x280D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},