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authorClaudiu Zissulescu <claziss@gmail.com>2019-07-24 16:52:23 +0300
committerClaudiu Zissulescu <claziss@gmail.com>2019-07-24 16:52:23 +0300
commit0f3f71676a8971e0376d7d99b383660f06ff4d95 (patch)
tree4b8d9e9bb46f32326a21903e3ac469cb91ce389d /opcodes/arc-dis.c
parent7e126ba31ab6536b1dd779e483b72f47d3a76742 (diff)
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[ARC] Update disassembler opcode selection
New instruction are added, and some of them are overlapping. Update disassembler to correctly recognize them. Introduce nps400 option. opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes, and MPY class instructions. (parse_option): Add nps400 option. (print_arc_disassembler_options): Add nps400 info. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/nps400-6.d: Update test.
Diffstat (limited to 'opcodes/arc-dis.c')
-rw-r--r--opcodes/arc-dis.c24
1 files changed, 23 insertions, 1 deletions
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index ee59891..8207c05 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -181,7 +181,9 @@ skip_this_opcode (const struct arc_opcode *opcode)
/* Check opcode for major 0x06, return if it is not in. */
if (arc_opcode_len (opcode) == 4
- && OPCODE_32BIT_INSN (opcode->opcode) != 0x06)
+ && (OPCODE_32BIT_INSN (opcode->opcode) != 0x06
+ /* Can be an APEX extensions. */
+ && OPCODE_32BIT_INSN (opcode->opcode) != 0x07))
return FALSE;
/* or not a known truble class. */
@@ -190,6 +192,7 @@ skip_this_opcode (const struct arc_opcode *opcode)
case FLOAT:
case DSP:
case ARITH:
+ case MPY:
break;
default:
return FALSE;
@@ -764,6 +767,23 @@ parse_option (const char *option)
else if (disassembler_options_cmp (option, "fpuda") == 0)
add_to_decodelist (FLOAT, DPA);
+ else if (disassembler_options_cmp (option, "nps400") == 0)
+ {
+ add_to_decodelist (ACL, NPS400);
+ add_to_decodelist (ARITH, NPS400);
+ add_to_decodelist (BITOP, NPS400);
+ add_to_decodelist (BMU, NPS400);
+ add_to_decodelist (CONTROL, NPS400);
+ add_to_decodelist (DMA, NPS400);
+ add_to_decodelist (DPI, NPS400);
+ add_to_decodelist (MEMORY, NPS400);
+ add_to_decodelist (MISC, NPS400);
+ add_to_decodelist (NET, NPS400);
+ add_to_decodelist (PMU, NPS400);
+ add_to_decodelist (PROTOCOL_DECODE, NPS400);
+ add_to_decodelist (ULTRAIP, NPS400);
+ }
+
else if (disassembler_options_cmp (option, "fpus") == 0)
{
add_to_decodelist (FLOAT, SP);
@@ -1411,6 +1431,8 @@ with -M switch (multiple options should be separated by commas):\n"));
fprintf (stream, _("\
fpud Recognize double precision FPU instructions.\n"));
fprintf (stream, _("\
+ nps400 Recognize NPS400 instructions.\n"));
+ fprintf (stream, _("\
hex Use only hexadecimal number to print immediates.\n"));
}