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authorClaudiu Zissulescu <claziss@synopsys.com>2016-10-13 15:01:19 +0200
committerClaudiu Zissulescu <claziss@synopsys.com>2016-10-14 13:52:15 +0200
commite5b06ef06b062f0626462abb182ee5470cf798bc (patch)
treec0df3f5db56418cfaf7e1cd62bcc070d9d1cf53e /opcodes/arc-dis.c
parentafb1110bfa4fe150cb2f2c58329551bd82cb3627 (diff)
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[ARC] Disassembler: fix LIMM detection for short instructions.
The ARC (short) instructions are using a special register number to indicate is the instruction uses a long immediate (LIMM). In the case of short instruction, this LIMM indicator depends on the ISA version used. Thus, for ARCv1 processors, the LIMM indicator is 0x3E, the same value used in "long" instructions. However, for the ARCv2 processors, this LIMM indicator is 0x1E. This patch fixes the LIMM detection for ARCv1 ISA and adds two tests. gas/ 2016-10-13 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/shortlimm_a7.d: New file. * testsuite/gas/arc/shortlimm_a7.s: Likewise. * testsuite/gas/arc/shortlimm_hs.d: Likewise. * testsuite/gas/arc/shortlimm_hs.s: Likewise. include/ 2016-10-13 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (ARC_OPCODE_ARCV2): New define. opcodes/ 2016-10-13 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (find_format_from_table): Discriminate LIMM indicator usage on ISA basis.
Diffstat (limited to 'opcodes/arc-dis.c')
-rw-r--r--opcodes/arc-dis.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index c4e118e..898512c 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -296,7 +296,7 @@ find_format_from_table (struct disassemble_info *info,
/* Possible candidate, check the operands. */
for (opidx = opcode->operands; *opidx; opidx++)
{
- int value;
+ int value, limmind;
const struct arc_operand *operand = &arc_operands[*opidx];
if (operand->flags & ARC_OPERAND_FAKE)
@@ -309,11 +309,12 @@ find_format_from_table (struct disassemble_info *info,
/* Check for LIMM indicator. If it is there, then make sure
we pick the right format. */
+ limmind = (isa_mask & ARC_OPCODE_ARCV2) ? 0x1E : 0x3E;
if (operand->flags & ARC_OPERAND_IR
&& !(operand->flags & ARC_OPERAND_LIMM))
{
if ((value == 0x3E && insn_len == 4)
- || (value == 0x1E && insn_len == 2))
+ || (value == limmind && insn_len == 2))
{
invalid = TRUE;
break;