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authorSudakshina Das <sudi.das@arm.com>2018-11-12 13:19:12 +0000
committerSudakshina Das <sudi.das@arm.com>2018-11-12 13:20:58 +0000
commit503ba600259856b41a88b56922e094ea826df270 (patch)
tree3db3d7f334fc3cf0de24c808169bc126d9913a36 /opcodes/aarch64-dis.c
parente6025b546c21b280ef05201b065f07335ee10e2e (diff)
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[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Bulk Allocation Tag instructions from MTE. These are the following instructions added in this patch: - LDGV <Xt>, [<Xn|SP>]! - STGV <Xt>, [<Xn|SP>]! This needed a new kind of operand for the new addressing [<Xn|SP>]! since this has no offset and only takes a pre-indexed version. Hence AARCH64_OPND_ADDR_SIMPLE_2 and ldtdgv_indexed are introduced. (AARCH64_OPND_ADDR_SIMPLE fulfilled the no offset criteria but does not allow writeback). We also needed new encoding and decoding functions to be able to do the same. where <Xt> : Is the 64-bit destination GPR. <Xn|SP> : Is the 64-bit first source GPR or Stack pointer. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2. (aarch64_insn_class): Add ldstgv_indexed. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-asm.c (aarch64_ins_addr_simple_2): New. * aarch64-asm.h (ins_addr_simple_2): Declare the above. * aarch64-dis.c (aarch64_ext_addr_simple_2): New. * aarch64-dis.h (ext_addr_simple_2): Declare the above. * aarch64-opc.c (operand_general_constraint_met_p): Add case for AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed. (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv. (AARCH64_OPERANDS): Define ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it. (warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
Diffstat (limited to 'opcodes/aarch64-dis.c')
-rw-r--r--opcodes/aarch64-dis.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index defb53d..fd542ac 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -985,6 +985,23 @@ aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
return TRUE;
}
+
+
+/* Decode the address operand for e.g. STGV <Xt>, [<Xn|SP>]!. */
+bfd_boolean
+aarch64_ext_addr_simple_2 (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ /* Rn */
+ info->addr.base_regno = extract_field (FLD_Rn, code, 0);
+ info->addr.writeback = 1;
+ info->addr.preind = 1;
+ return TRUE;
+}
+
/* Decode the address operand for e.g.
stlur <Xt>, [<Xn|SP>{, <amount>}]. */
bfd_boolean