Adds the new Fields and Operand types for the new instructions in Armv8.4-a.

gas/
	* config/tc-aarch64.c (process_omitted_operand):
	Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2
	and AARCH64_OPND_IMM_2.
	(parse_operands): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
	AARCH64_OPND_IMM_2, AARCH64_OPND_MASK
	and AARCH64_OPND_ADDR_OFFSET.

include/
	* opcode/aarch64.h:
	(aarch64_opnd): Add AARCH64_OPND_Va, AARCH64_OPND_MASK,
	AARCH64_OPND_IMM_2, AARCH64_OPND_ADDR_OFFSET
	and AARCH64_OPND_SM3_IMM2.
	(aarch64_insn_class): Add cryptosm3 and cryptosm4.
	(arch64_feature_set): Make uint64_t.

opcodes/
	* aarch64-asm.h (ins_addr_offset): New.
	* aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
	(aarch64_ins_addr_offset): New.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_addr_offset): New.
	* aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
	(aarch64_ext_addr_offset): New.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
	FLD_imm4_2 and FLD_SM3_imm2.
	* aarch64-opc.c (fields): Add FLD_imm6_2,
	FLD_imm4_2 and FLD_SM3_imm2.
	(operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
	(aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
	AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
	* aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
	* aarch64-tbl.h
	(aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.

1 files changed, 30 insertions, 0 deletions

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 345d599..9294910 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -135,6 +135,13 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
 	  assert (0);
 	}
     }
+  else if (inst->opcode->iclass == cryptosm3)
+    {
+      /* index for e.g. SM3TT2A <Vd>.4S, <Vn>.4S, <Vm>S[<imm2>].  */
+      unsigned reglane_index = info->reglane.index;
+      assert (reglane_index < 4);
+      insert_field (FLD_SM3_imm2, code, reglane_index, 0);
+    }
   else
     {
       /* index for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
@@ -620,6 +627,29 @@ aarch64_ins_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
   return NULL;
 }
 
+/* Encode the address operand for e.g.
+     stlur <Xt>, [<Xn|SP>{, <amount>}].  */
+const char *
+aarch64_ins_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
+			 const aarch64_opnd_info *info, aarch64_insn *code,
+			 const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+  /* Rn */
+  insert_field (self->fields[0], code, info->addr.base_regno, 0);
+
+  /* simm9 */
+  int imm = info->addr.offset.imm;
+  insert_field (self->fields[1], code, imm, 0);
+
+  /* writeback */
+  if (info->addr.writeback)
+    {
+      assert (info->addr.preind == 1 && info->addr.postind == 0);
+      insert_field (self->fields[2], code, 1, 0);
+    }
+  return NULL;
+}
+
 /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>, #<simm>]!.  */
 const char *
 aarch64_ins_addr_simm (const aarch64_operand *self,