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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:13 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:13 +0100 |
| commit | ed429b33c1ee8d6d8f8e640e58f04ec800bc7b2a (patch) | |
| tree | 9dec9ddf10c70e8d8c16f5f0820eb23eefe4a733 /opcodes/aarch64-asm.c | |
| parent | 80752eb0989b85e88af7f1f4627dbed8a42dfe6d (diff) | |
| download | gdb-ed429b33c1ee8d6d8f8e640e58f04ec800bc7b2a.zip gdb-ed429b33c1ee8d6d8f8e640e58f04ec800bc7b2a.tar.gz gdb-ed429b33c1ee8d6d8f8e640e58f04ec800bc7b2a.tar.bz2 | |
aarch64: Add the SME2 MLAL and MLSL instructions
The {BF,F,S,U}MLAL and {BF,F,S,U}MLSL instructions share the same
encoding. They are the first instance of a ZA (as opposed to ZA tile)
operand having a range of offsets. As with ZA tiles, the expected
range size is encoded in the operand-specific data field.
Diffstat (limited to 'opcodes/aarch64-asm.c')
| -rw-r--r-- | opcodes/aarch64-asm.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index f2b7d7d..b1d2d58 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1487,8 +1487,10 @@ aarch64_ins_sme_za_array (const aarch64_operand *self, { int regno = info->indexed_za.index.regno & 3; int imm = info->indexed_za.index.imm; + int countm1 = info->indexed_za.index.countm1; + assert (imm % (countm1 + 1) == 0); insert_field (self->fields[0], code, regno, 0); - insert_field (self->fields[1], code, imm, 0); + insert_field (self->fields[1], code, imm / (countm1 + 1), 0); return true; } |