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author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 19:31:25 +0000 |
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committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 19:32:17 +0000 |
commit | 7bb5f07c8aa5168009f1e7b6857a30f0ee5ad16a (patch) | |
tree | e8a7449925ac32ef3a5ebf0db7276c348ca5bb8c /opcodes/aarch64-asm.c | |
parent | 971eda734150ea9cdea47be259486c3a8d087037 (diff) | |
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aarch64: [SME] Add MOV and MOVA instructions
This patch is adding new MOV (alias) and MOVA SME instruction.
gas/ChangeLog:
* config/tc-aarch64.c (enum sme_hv_slice): new enum.
(struct reloc_entry): Added ZAH and ZAV registers.
(parse_sme_immediate): Immediate parser.
(parse_sme_za_hv_tiles_operand): ZA tile parser.
(parse_sme_za_hv_tiles_operand_index): Index parser.
(parse_operands): Added ZA tile parser calls.
(REGNUMS): New macro. Regs with suffix.
(REGSET16S): New macro. 16 regs with suffix.
* testsuite/gas/aarch64/sme-2-illegal.d: New test.
* testsuite/gas/aarch64/sme-2-illegal.l: New test.
* testsuite/gas/aarch64/sme-2-illegal.s: New test.
* testsuite/gas/aarch64/sme-2.d: New test.
* testsuite/gas/aarch64/sme-2.s: New test.
* testsuite/gas/aarch64/sme-2a.d: New test.
* testsuite/gas/aarch64/sme-2a.s: New test.
* testsuite/gas/aarch64/sme-3-illegal.d: New test.
* testsuite/gas/aarch64/sme-3-illegal.l: New test.
* testsuite/gas/aarch64/sme-3-illegal.s: New test.
* testsuite/gas/aarch64/sme-3.d: New test.
* testsuite/gas/aarch64/sme-3.s: New test.
* testsuite/gas/aarch64/sme-3a.d: New test.
* testsuite/gas/aarch64/sme-3a.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New enums
AARCH64_OPND_SME_ZA_HV_idx_src and
AARCH64_OPND_SME_ZA_HV_idx_dest.
(struct aarch64_opnd_info): New ZA tile vector struct.
opcodes/ChangeLog:
* aarch64-asm.c (aarch64_ins_sme_za_hv_tiles):
New inserter.
* aarch64-asm.h (AARCH64_DECL_OPD_INSERTER):
New inserter ins_sme_za_hv_tiles.
* aarch64-dis.c (aarch64_ext_sme_za_hv_tiles):
New extractor.
* aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR):
New extractor ext_sme_za_hv_tiles.
* aarch64-opc.c (aarch64_print_operand):
Handle SME_ZA_HV_idx_src and SME_ZA_HV_idx_dest.
* aarch64-opc.h (enum aarch64_field_kind): New enums
FLD_SME_size_10, FLD_SME_Q, FLD_SME_V and FLD_SME_Rv.
(struct aarch64_operand): Increase fields size to 5.
* aarch64-tbl.h (OP_SME_BHSDQ_PM_BHSDQ): New qualifiers
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
Diffstat (limited to 'opcodes/aarch64-asm.c')
-rw-r--r-- | opcodes/aarch64-asm.c | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 7cc8146..9a77d0f 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1325,6 +1325,61 @@ aarch64_ins_sve_float_zero_one (const aarch64_operand *self, return true; } +/* Encode in SME instruction such as MOVA ZA tile vector register number, + vector indicator, vector selector and immediate. */ +bool +aarch64_ins_sme_za_hv_tiles (const aarch64_operand *self, + const aarch64_opnd_info *info, + aarch64_insn *code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + int fld_size; + int fld_q; + int fld_v = info->za_tile_vector.v; + int fld_rv = info->za_tile_vector.index.regno - 12; + int fld_zan_imm = info->za_tile_vector.index.imm; + int regno = info->za_tile_vector.regno; + + switch (info->qualifier) + { + case AARCH64_OPND_QLF_S_B: + fld_size = 0; + fld_q = 0; + break; + case AARCH64_OPND_QLF_S_H: + fld_size = 1; + fld_q = 0; + fld_zan_imm |= regno << 3; + break; + case AARCH64_OPND_QLF_S_S: + fld_size = 2; + fld_q = 0; + fld_zan_imm |= regno << 2; + break; + case AARCH64_OPND_QLF_S_D: + fld_size = 3; + fld_q = 0; + fld_zan_imm |= regno << 1; + break; + case AARCH64_OPND_QLF_S_Q: + fld_size = 3; + fld_q = 1; + fld_zan_imm = regno; + break; + default: + assert (0); + } + + insert_field (self->fields[0], code, fld_size, 0); + insert_field (self->fields[1], code, fld_q, 0); + insert_field (self->fields[2], code, fld_v, 0); + insert_field (self->fields[3], code, fld_rv, 0); + insert_field (self->fields[4], code, fld_zan_imm, 0); + + return true; +} + /* Miscellaneous encoding functions. */ /* Encode size[0], i.e. bit 22, for |