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author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:16 +0100 |
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committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:16 +0100 |
commit | 6efa660124f481a5ba415cedd195764ea6ac09fd (patch) | |
tree | 5ceb8e36ccb0439e3256688ff9cfb98abb06673d /opcodes/aarch64-asm.c | |
parent | ce623e7aa486d1330c9a4529c77a302d2fdcb801 (diff) | |
download | gdb-6efa660124f481a5ba415cedd195764ea6ac09fd.zip gdb-6efa660124f481a5ba415cedd195764ea6ac09fd.tar.gz gdb-6efa660124f481a5ba415cedd195764ea6ac09fd.tar.bz2 |
aarch64: Add the SME2 shift instructions
There are two instruction formats here:
- SQRSHR, SQRSHRU and UQRSHR, which operate on lists of two
or four registers.
- SQRSHRN, SQRSHRUN and UQRSHRN, which operate on lists of
four registers.
These are the first SME2 instructions to have immediate operands.
The patch makes sure that, when parsing SME2 instructions with
immediate operands, the new predicate-as-counter registers are
parsed as registers rather than as #-less immediates.
Diffstat (limited to 'opcodes/aarch64-asm.c')
-rw-r--r-- | opcodes/aarch64-asm.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 5f2e510..0025cb6 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1624,6 +1624,19 @@ aarch64_ins_simple_index (const aarch64_operand *self, return true; } +/* Insert a plain shift-right immediate, when there is only a single + element size. */ +bool +aarch64_ins_plain_shrimm (const aarch64_operand *self, + const aarch64_opnd_info *info, aarch64_insn *code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + unsigned int base = 1 << get_operand_field_width (self, 0); + insert_field (self->fields[0], code, base - info->imm.value, 0); + return true; +} + /* Miscellaneous encoding functions. */ /* Encode size[0], i.e. bit 22, for @@ -1980,6 +1993,7 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) 0, 2, FLD_SVE_M_14, FLD_size); break; + case sme_shift: case sve_index: case sve_shift_pred: case sve_shift_unpred: |