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author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 20:02:06 +0000 |
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committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 20:02:24 +0000 |
commit | 01a4d0822025084609380fb989d43bda0667db72 (patch) | |
tree | 5c1888e350164f67afae5b11ab70b82fa4a353bf /opcodes/aarch64-asm.c | |
parent | 1cad938de57a1577e5fe4b4afcabe889a8b9b9d7 (diff) | |
download | gdb-01a4d0822025084609380fb989d43bda0667db72.zip gdb-01a4d0822025084609380fb989d43bda0667db72.tar.gz gdb-01a4d0822025084609380fb989d43bda0667db72.tar.bz2 |
aarch64: [SME] Add LD1x, ST1x, LDR and STR instructions
This patch is adding new loads and stores defined by SME instructions.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sme_address): New parser.
(parse_sme_za_hv_tiles_operand_with_braces): New parser.
(parse_sme_za_array): New parser.
(output_operand_error_record): Print error details if
present.
(parse_operands): Support new operands.
* testsuite/gas/aarch64/sme-5-illegal.d: New test.
* testsuite/gas/aarch64/sme-5-illegal.l: New test.
* testsuite/gas/aarch64/sme-5-illegal.s: New test.
* testsuite/gas/aarch64/sme-5.d: New test.
* testsuite/gas/aarch64/sme-5.s: New test.
* testsuite/gas/aarch64/sme-6-illegal.d: New test.
* testsuite/gas/aarch64/sme-6-illegal.l: New test.
* testsuite/gas/aarch64/sme-6-illegal.s: New test.
* testsuite/gas/aarch64/sme-6.d: New test.
* testsuite/gas/aarch64/sme-6.s: New test.
* testsuite/gas/aarch64/sme-7-illegal.d: New test.
* testsuite/gas/aarch64/sme-7-illegal.l: New test.
* testsuite/gas/aarch64/sme-7-illegal.s: New test.
* testsuite/gas/aarch64/sme-7.d: New test.
* testsuite/gas/aarch64/sme-7.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New operands.
(enum aarch64_insn_class): Added sme_ldr and sme_str.
(AARCH64_OPDE_UNTIED_IMMS): New operand error kind.
opcodes/ChangeLog:
* aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter.
(aarch64_ins_sme_za_list): New inserter.
(aarch64_ins_sme_za_array): New inserter.
(aarch64_ins_sme_addr_ri_u4xvl): New inserter.
* aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): Added
ins_sme_za_list, ins_sme_za_array and ins_sme_addr_ri_u4xvl.
* aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor.
(aarch64_ext_sme_za_list): New extractor.
(aarch64_ext_sme_za_array): New extractor.
(aarch64_ext_sme_addr_ri_u4xvl): New extractor.
* aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): Added
ext_sme_za_list, ext_sme_za_array and ext_sme_addr_ri_u4xvl.
* aarch64-opc.c (operand_general_constraint_met_p):
(aarch64_match_operands_constraint): Handle sme_ldr, sme_str
and sme_misc.
(aarch64_print_operand): New operands supported.
* aarch64-tbl.h (OP_SVE_QUU): New qualifier.
(OP_SVE_QZU): New qualifier.
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
Diffstat (limited to 'opcodes/aarch64-asm.c')
-rw-r--r-- | opcodes/aarch64-asm.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 9a77d0f..a2b0e86 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1380,6 +1380,53 @@ aarch64_ins_sme_za_hv_tiles (const aarch64_operand *self, return true; } +/* Encode in SME instruction ZERO list of up to eight 64-bit element tile names + separated by commas, encoded in the "imm8" field. + + For programmer convenience an assembler must also accept the names of + 32-bit, 16-bit and 8-bit element tiles which are converted into the + corresponding set of 64-bit element tiles. +*/ +bool +aarch64_ins_sme_za_list (const aarch64_operand *self, + const aarch64_opnd_info *info, + aarch64_insn *code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + int fld_mask = info->imm.value; + insert_field (self->fields[0], code, fld_mask, 0); + return true; +} + +bool +aarch64_ins_sme_za_array (const aarch64_operand *self, + const aarch64_opnd_info *info, + aarch64_insn *code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + int regno = info->za_tile_vector.index.regno - 12; + int imm = info->za_tile_vector.index.imm; + insert_field (self->fields[0], code, regno, 0); + insert_field (self->fields[1], code, imm, 0); + return true; +} + +bool +aarch64_ins_sme_addr_ri_u4xvl (const aarch64_operand *self, + const aarch64_opnd_info *info, + aarch64_insn *code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + int regno = info->addr.base_regno; + int imm = info->addr.offset.imm; + insert_field (self->fields[0], code, regno, 0); + insert_field (self->fields[1], code, imm, 0); + return true; +} + /* Miscellaneous encoding functions. */ /* Encode size[0], i.e. bit 22, for |