Fix AArch64 encodings for by element instructions.

Some instructions in Armv8-a place a limitation on FP16 registers that can be
used as the register from which to select an element from.

e.g. fmla restricts Rm to 4 bits when using an FP16 register.  This restriction
does not apply for all instructions, e.g. fcmla does not have this restriction
as it gets an extra bit from the M field.

Unfortunately, this restriction to S_H was added for all _Em operands before,
meaning for a large number of instructions you couldn't use the full register
file.

This fixes the issue by introducing a new operand _Em16 which applies this
restriction only when paired with S_H and leaves the _Em and the other
qualifiers for _Em16 unbounded (i.e. using the full 5 bit range).

Also the patch updates all instructions that should be affected by this.

opcodes/

	PR binutils/23192
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
	* aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
	* aarch64-opc.c (operand_general_constraint_met_p,
	aarch64_print_operand): Likewise.
	* aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
	smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
	fmlal2, fmlsl2.
	(AARCH64_OPERANDS): Add Em2.

gas/

	PR binutils/23192
	* config/tc-aarch64.c (process_omitted_operand, parse_operands): Add
	AARCH64_OPND_Em16
	* testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper
	16 registers.
	* testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
	* testsuite/gas/aarch64/advsimd-compnum.s: Likewise.
	* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
	* testsuite/gas/aarch64/sve.d: Likewise.

include/

	PR binutils/23192
	*opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.

1 files changed, 69 insertions, 68 deletions

diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 45b0085..b0320db 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -614,7 +614,6 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 27:
     case 28:
     case 29:
-    case 152:
     case 153:
     case 154:
     case 155:
@@ -624,7 +623,7 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 159:
     case 160:
     case 161:
-    case 174:
+    case 162:
     case 175:
     case 176:
     case 177:
@@ -633,8 +632,9 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 180:
     case 181:
     case 182:
-    case 186:
-    case 189:
+    case 183:
+    case 187:
+    case 190:
       return aarch64_ins_regno (self, info, code, inst, errors);
     case 13:
       return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -645,21 +645,21 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 30:
     case 31:
     case 32:
-    case 191:
-      return aarch64_ins_reglane (self, info, code, inst, errors);
     case 33:
-      return aarch64_ins_reglist (self, info, code, inst, errors);
+    case 192:
+      return aarch64_ins_reglane (self, info, code, inst, errors);
     case 34:
-      return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
+      return aarch64_ins_reglist (self, info, code, inst, errors);
     case 35:
-      return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
+      return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
     case 36:
-      return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
+      return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
     case 37:
+      return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
     case 38:
     case 39:
     case 40:
-    case 50:
+    case 41:
     case 51:
     case 52:
     case 53:
@@ -673,13 +673,13 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 61:
     case 62:
     case 63:
-    case 75:
+    case 64:
     case 76:
     case 77:
     case 78:
-    case 149:
-    case 151:
-    case 166:
+    case 79:
+    case 150:
+    case 152:
     case 167:
     case 168:
     case 169:
@@ -687,86 +687,86 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 171:
     case 172:
     case 173:
+    case 174:
       return aarch64_ins_imm (self, info, code, inst, errors);
-    case 41:
     case 42:
-      return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
     case 43:
+      return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
     case 44:
     case 45:
+    case 46:
       return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
-    case 49:
-    case 140:
+    case 50:
+    case 141:
       return aarch64_ins_fpimm (self, info, code, inst, errors);
-    case 64:
-    case 147:
-      return aarch64_ins_limm (self, info, code, inst, errors);
     case 65:
-      return aarch64_ins_aimm (self, info, code, inst, errors);
+    case 148:
+      return aarch64_ins_limm (self, info, code, inst, errors);
     case 66:
-      return aarch64_ins_imm_half (self, info, code, inst, errors);
+      return aarch64_ins_aimm (self, info, code, inst, errors);
     case 67:
+      return aarch64_ins_imm_half (self, info, code, inst, errors);
+    case 68:
       return aarch64_ins_fbits (self, info, code, inst, errors);
-    case 69:
     case 70:
-    case 145:
-      return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
     case 71:
-    case 144:
-      return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
+    case 146:
+      return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
     case 72:
+    case 145:
+      return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
     case 73:
+    case 74:
       return aarch64_ins_cond (self, info, code, inst, errors);
-    case 79:
-    case 86:
-      return aarch64_ins_addr_simple (self, info, code, inst, errors);
     case 80:
-      return aarch64_ins_addr_regoff (self, info, code, inst, errors);
+    case 87:
+      return aarch64_ins_addr_simple (self, info, code, inst, errors);
     case 81:
+      return aarch64_ins_addr_regoff (self, info, code, inst, errors);
     case 82:
     case 83:
-      return aarch64_ins_addr_simm (self, info, code, inst, errors);
     case 84:
-      return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
+      return aarch64_ins_addr_simm (self, info, code, inst, errors);
     case 85:
+      return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
+    case 86:
       return aarch64_ins_addr_uimm12 (self, info, code, inst, errors);
-    case 87:
-      return aarch64_ins_addr_offset (self, info, code, inst, errors);
     case 88:
-      return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
+      return aarch64_ins_addr_offset (self, info, code, inst, errors);
     case 89:
-      return aarch64_ins_sysreg (self, info, code, inst, errors);
+      return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
     case 90:
-      return aarch64_ins_pstatefield (self, info, code, inst, errors);
+      return aarch64_ins_sysreg (self, info, code, inst, errors);
     case 91:
+      return aarch64_ins_pstatefield (self, info, code, inst, errors);
     case 92:
     case 93:
     case 94:
-      return aarch64_ins_sysins_op (self, info, code, inst, errors);
     case 95:
+      return aarch64_ins_sysins_op (self, info, code, inst, errors);
     case 96:
-      return aarch64_ins_barrier (self, info, code, inst, errors);
     case 97:
-      return aarch64_ins_prfop (self, info, code, inst, errors);
+      return aarch64_ins_barrier (self, info, code, inst, errors);
     case 98:
-      return aarch64_ins_hint (self, info, code, inst, errors);
+      return aarch64_ins_prfop (self, info, code, inst, errors);
     case 99:
-      return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
+      return aarch64_ins_hint (self, info, code, inst, errors);
     case 100:
+      return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
     case 101:
     case 102:
     case 103:
-      return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
     case 104:
-      return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
     case 105:
-      return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
     case 106:
+      return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
     case 107:
     case 108:
     case 109:
-      return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
     case 110:
+      return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
     case 111:
     case 112:
     case 113:
@@ -779,8 +779,8 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 120:
     case 121:
     case 122:
-      return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
     case 123:
+      return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
     case 124:
     case 125:
     case 126:
@@ -788,48 +788,49 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 128:
     case 129:
     case 130:
-      return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
     case 131:
+      return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
     case 132:
     case 133:
     case 134:
-      return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
     case 135:
-      return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
     case 136:
-      return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
     case 137:
-      return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
     case 138:
-      return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
     case 139:
+      return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+    case 140:
       return aarch64_ins_sve_asimm (self, info, code, inst, errors);
-    case 141:
-      return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
     case 142:
-      return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+      return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
     case 143:
+      return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+    case 144:
       return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
-    case 146:
+    case 147:
       return aarch64_ins_inv_limm (self, info, code, inst, errors);
-    case 148:
+    case 149:
       return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
-    case 150:
+    case 151:
       return aarch64_ins_sve_scale (self, info, code, inst, errors);
-    case 162:
     case 163:
-      return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
     case 164:
+      return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
     case 165:
+    case 166:
       return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
-    case 183:
     case 184:
     case 185:
+    case 186:
       return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
-    case 187:
-      return aarch64_ins_sve_index (self, info, code, inst, errors);
     case 188:
-    case 190:
+      return aarch64_ins_sve_index (self, info, code, inst, errors);
+    case 189:
+    case 191:
       return aarch64_ins_sve_reglist (self, info, code, inst, errors);
     default: assert (0); abort ();
     }