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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-06-24 11:51:56 +0900 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2022-06-28 09:08:42 +0800 |
| commit | 766077c17343e4e539f3588f1c7f63d920f2bfa2 (patch) | |
| tree | 7a37fe04ce098e5e08f1758f7c9b1a19bd6c036d /include | |
| parent | 713f370809b523277f8ecc69680ab591ce94da5e (diff) | |
| download | gdb-766077c17343e4e539f3588f1c7f63d920f2bfa2.zip gdb-766077c17343e4e539f3588f1c7f63d920f2bfa2.tar.gz gdb-766077c17343e4e539f3588f1c7f63d920f2bfa2.tar.bz2 | |
RISC-V: Add 'Sstc' extension and its CSRs
This commit adds "stimecmp / vstimecmp" Extension (Sstc) and its CSRs.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sstc'
extension to valid 'S' extension list.
gas/ChangeLog:
* config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for
'Sstc' extension. (riscv_csr_address): Add handling for new CSR
classes.
* testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr.s: Add new CSRs.
* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (CSR_STIMECMP, CSR_STIMECMPH,
CSR_VSTIMECMP, CSR_VSTIMECMPH): New CSR macros.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 8546a6e..88b8d7f 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2484,6 +2484,11 @@ #define CSR_MHPMEVENT29H 0x73d #define CSR_MHPMEVENT30H 0x73e #define CSR_MHPMEVENT31H 0x73f +/* Sstc extension */ +#define CSR_STIMECMP 0x14d +#define CSR_STIMECMPH 0x15d +#define CSR_VSTIMECMP 0x24d +#define CSR_VSTIMECMPH 0x25d /* Unprivileged Floating-Point CSR addresses. */ #define CSR_FFLAGS 0x1 #define CSR_FRM 0x2 @@ -3201,6 +3206,11 @@ DECLARE_CSR(mhpmevent28h, CSR_MHPMEVENT28H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLA DECLARE_CSR(mhpmevent29h, CSR_MHPMEVENT29H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mhpmevent30h, CSR_MHPMEVENT30H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mhpmevent31h, CSR_MHPMEVENT31H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +/* Sstc extension */ +DECLARE_CSR(stimecmp, CSR_STIMECMP, CSR_CLASS_SSTC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(stimecmph, CSR_STIMECMPH, CSR_CLASS_SSTC_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(vstimecmp, CSR_VSTIMECMP, CSR_CLASS_SSTC_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(vstimecmph, CSR_VSTIMECMPH, CSR_CLASS_SSTC_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) /* Dropped CSRs. */ DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) |