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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-06-28 17:43:57 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-09-22 18:06:09 +0200 |
| commit | 547c18d9bb95571261dbd17f4767194037eb82bd (patch) | |
| tree | ba5189db19567b97acc4c916c7d864f7c1c6356d /include | |
| parent | a9ba8bc2d396fb8ae2b892f3bc6be8cdfe4b555c (diff) | |
| download | gdb-547c18d9bb95571261dbd17f4767194037eb82bd.zip gdb-547c18d9bb95571261dbd17f4767194037eb82bd.tar.gz gdb-547c18d9bb95571261dbd17f4767194037eb82bd.tar.bz2 | |
RISC-V: Add T-Head SYNC vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadSync extension, a collection of
T-Head-specific multi-processor synchronization instructions.
The 'th' prefix and the "XTheadSync" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc.h | 17 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 1 |
2 files changed, 18 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 53b1c22..970cdf2 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2156,6 +2156,17 @@ #define MASK_TH_L2CACHE_CIALL 0xffffffff #define MATCH_TH_L2CACHE_IALL 0x0160000b #define MASK_TH_L2CACHE_IALL 0xffffffff +/* Vendor-specific (T-Head) XTheadSync instructions. */ +#define MATCH_TH_SFENCE_VMAS 0x0400000b +#define MASK_TH_SFENCE_VMAS 0xfe007fff +#define MATCH_TH_SYNC 0x0180000b +#define MASK_TH_SYNC 0xffffffff +#define MATCH_TH_SYNC_I 0x01a0000b +#define MASK_TH_SYNC_I 0xffffffff +#define MATCH_TH_SYNC_IS 0x01b0000b +#define MASK_TH_SYNC_IS 0xffffffff +#define MATCH_TH_SYNC_S 0x0190000b +#define MASK_TH_SYNC_S 0xffffffff /* Unprivileged Counter/Timers CSR addresses. */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 @@ -2917,6 +2928,12 @@ DECLARE_INSN(th_icache_iva, MATCH_TH_ICACHE_IVA, MASK_TH_ICACHE_IVA) DECLARE_INSN(th_l2cache_call, MATCH_TH_L2CACHE_CALL, MASK_TH_L2CACHE_CALL) DECLARE_INSN(th_l2cache_ciall, MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL) DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL) +/* Vendor-specific (T-Head) XTheadSync instructions. */ +DECLARE_INSN(th_sfence_vmas, MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS) +DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC) +DECLARE_INSN(th_sync_i, MATCH_TH_SYNC_I, MASK_TH_SYNC_I) +DECLARE_INSN(th_sync_is, MATCH_TH_SYNC_IS, MASK_TH_SYNC_IS) +DECLARE_INSN(th_sync_s, MATCH_TH_SYNC_S, MASK_TH_SYNC_S) #endif /* DECLARE_INSN */ #ifdef DECLARE_CSR /* Unprivileged Counter/Timers CSRs. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index d369831..6fdc9c9 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -399,6 +399,7 @@ enum riscv_insn_class INSN_CLASS_ZICBOZ, INSN_CLASS_H, INSN_CLASS_XTHEADCMO, + INSN_CLASS_XTHEADSYNC, }; /* This structure holds information for a particular instruction. */ |