Revert "2.41 Release sources"

This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d.

See https://sourceware.org/pipermail/binutils/2023-August/128761.html.

6 files changed, 92 insertions, 3 deletions

diff --git a/include/ChangeLog b/include/ChangeLog
index f0c8fe8..4d40740 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,35 @@
+2023-07-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+	* elf/bpf.h (EF_BPF_CPUVER): Define.
+	* opcode/bpf.h (BPF_XBPF): Change from 0xf to 0xff so it fits in
+	EF_BPF_CPUVER.
+
+2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+	* opcode/bpf.h (BPF_IMM32_BSWAP16): Define.
+	(BPF_IMM32_BSWAP32): Likewise.
+	(BPF_IMM32_BSWAP64): Likewise.
+	(enum bpf_insn_id): New entries BPF_INSN_BSWAP{16,32,64}.
+
+2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+	* opcode/bpf.h (enum bpf_insn_id): Add entry BPF_INSN_JAL.
+	(enum bpf_insn_id): Remove spurious entry BPF_INSN_CALLI.
+
+2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+	* opcode/bpf.h (enum bpf_insn_id): Add entries for signed load
+	instructions.
+	(BPF_MODE_SMEM): Define.
+
+2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+	* opcode/bpf.h (BPF_OFFSET16_MOVS8): Define.
+	(BPF_OFFSET16_MOVS16): Likewise.
+	(BPF_OFFSET16_MOVS32): Likewise.
+	(enum bpf_insn_id): Add entries for MOVS{8,16,32}R and
+	MOVS32{8,16,32}R.
+
 2023-07-03  Nick Clifton  <nickc@redhat.com>
 
 	2.41 Branch Point.
diff --git a/include/coff/internal.h b/include/coff/internal.h
index 92a0abf..7a566ca 100644
--- a/include/coff/internal.h
+++ b/include/coff/internal.h
@@ -352,7 +352,7 @@ struct internal_aouthdr
 
 #define C_NULL_VALUE	0x00de1e00    /* Value for a C_NULL deleted entry.  */
 
-#if defined _AIX52 || defined AIX_WEAK_SUPPORT
+#ifdef AIX_WEAK_SUPPORT
 #undef C_WEAKEXT
 #define C_WEAKEXT       C_AIX_WEAKEXT
 #endif
diff --git a/include/dis-asm.h b/include/dis-asm.h
index d356429..c76185f 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -388,6 +388,7 @@ extern void print_arc_disassembler_options (FILE *);
 extern void print_s390_disassembler_options (FILE *);
 extern void print_wasm32_disassembler_options (FILE *);
 extern void print_loongarch_disassembler_options (FILE *);
+extern void print_bpf_disassembler_options (FILE *);
 extern bool aarch64_symbol_is_valid (asymbol *, struct disassemble_info *);
 extern bool arm_symbol_is_valid (asymbol *, struct disassemble_info *);
 extern bool csky_symbol_is_valid (asymbol *, struct disassemble_info *);
diff --git a/include/elf/bpf.h b/include/elf/bpf.h
index fb19360..e4d4162 100644
--- a/include/elf/bpf.h
+++ b/include/elf/bpf.h
@@ -34,6 +34,12 @@ START_RELOC_NUMBERS (elf_bpf_reloc_type)
  * It is kept in this file to remind that the value is already taken. */
   RELOC_NUMBER (R_BPF_64_NODYLD32, 		4)
   RELOC_NUMBER (R_BPF_64_32,      		10)
+  RELOC_NUMBER (R_BPF_GNU_64_16,                256)
 END_RELOC_NUMBERS (R_BPF_max)
 
+/* Processor specific flags for the ELF header e_flags field.  */
+
+/* Version of the BPF ISA used in the file.  */
+#define EF_BPF_CPUVER 0x0000000f
+
 #endif /* _ELF_BPF_H  */
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 90f4415..53f5f20 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2210,6 +2210,31 @@
 #define MASK_VSM3C_VI 0xfe00707f
 #define MATCH_VSM3ME_VV 0x82002077
 #define MASK_VSM3ME_VV 0xfe00707f
+/* Zcb instructions.  */
+#define MATCH_C_LBU 0x8000
+#define MASK_C_LBU 0xfc03
+#define MATCH_C_LHU 0x8400
+#define MASK_C_LHU 0xfc43
+#define MATCH_C_LH 0x8440
+#define MASK_C_LH 0xfc43
+#define MATCH_C_SB 0x8800
+#define MASK_C_SB 0xfc03
+#define MATCH_C_SH 0x8c00
+#define MASK_C_SH 0xfc43
+#define MATCH_C_ZEXT_B 0x9c61
+#define MASK_C_ZEXT_B 0xfc7f
+#define MATCH_C_SEXT_B 0x9c65
+#define MASK_C_SEXT_B 0xfc7f
+#define MATCH_C_ZEXT_H 0x9c69
+#define MASK_C_ZEXT_H 0xfc7f
+#define MATCH_C_SEXT_H 0x9c6d
+#define MASK_C_SEXT_H 0xfc7f
+#define MATCH_C_ZEXT_W 0x9c71
+#define MASK_C_ZEXT_W 0xfc7f
+#define MATCH_C_NOT 0x9c75
+#define MASK_C_NOT 0xfc7f
+#define MATCH_C_MUL 0x9c41
+#define MASK_C_MUL 0xfc63
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3367,6 +3392,19 @@ DECLARE_INSN(vsm4r_vv, MATCH_VSM4R_VV, MASK_VSM4R_VV)
 /* Zvksh instructions.  */
 DECLARE_INSN(vsm3c_vi, MATCH_VSM3C_VI, MASK_VSM3C_VI)
 DECLARE_INSN(vsm3me_vv, MATCH_VSM3ME_VV, MASK_VSM3ME_VV)
+/* Zcb instructions.  */
+DECLARE_INSN(c_sext_b, MATCH_C_SEXT_B, MASK_C_SEXT_B)
+DECLARE_INSN(c_sext_h, MATCH_C_SEXT_H, MASK_C_SEXT_H)
+DECLARE_INSN(c_zext_b, MATCH_C_ZEXT_B, MASK_C_ZEXT_B)
+DECLARE_INSN(c_zext_h, MATCH_C_ZEXT_H, MASK_C_ZEXT_H)
+DECLARE_INSN(c_zext_w, MATCH_C_ZEXT_W, MASK_C_ZEXT_W)
+DECLARE_INSN(c_mul, MATCH_C_MUL, MASK_C_MUL)
+DECLARE_INSN(c_not, MATCH_C_NOT, MASK_C_NOT)
+DECLARE_INSN(c_lbu, MATCH_C_LBU, MASK_C_LBU)
+DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU)
+DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH)
+DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB)
+DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index d859f44..808f365 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -108,6 +108,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 20, 10))
 #define EXTRACT_RVV_VC_IMM(x) \
   (RV_X(x, 20, 11))
+#define EXTRACT_ZCB_BYTE_UIMM(x) \
+  (RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1))
+#define EXTRACT_ZCB_HALFWORD_UIMM(x) \
+  (RV_X(x, 5, 1) << 1)
 
 #define ENCODE_ITYPE_IMM(x) \
   (RV_X(x, 0, 12) << 20)
@@ -155,6 +159,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 0, 11) << 20)
 #define ENCODE_RVV_VI_UIMM6(x) \
   (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26)
+#define ENCODE_ZCB_BYTE_UIMM(x) \
+  ((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5))
+#define ENCODE_ZCB_HALFWORD_UIMM(x) \
+  (RV_X(x, 1, 1) << 5)
 
 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -180,6 +188,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 #define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x))
 #define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x))
 #define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))
+#define VALID_ZCB_BYTE_UIMM(x) (EXTRACT_ZCB_BYTE_UIMM(ENCODE_ZCB_BYTE_UIMM(x)) == (x))
+#define VALID_ZCB_HALFWORD_UIMM(x) (EXTRACT_ZCB_HALFWORD_UIMM(ENCODE_ZCB_HALFWORD_UIMM(x)) == (x))
 
 #define RISCV_RTYPE(insn, rd, rs1, rs2) \
   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
@@ -418,11 +428,13 @@ enum riscv_insn_class
   INSN_CLASS_ZVBC,
   INSN_CLASS_ZVKG,
   INSN_CLASS_ZVKNED,
-  INSN_CLASS_ZVKNHA,
-  INSN_CLASS_ZVKNHB,
   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
   INSN_CLASS_ZVKSED,
   INSN_CLASS_ZVKSH,
+  INSN_CLASS_ZCB,
+  INSN_CLASS_ZCB_AND_ZBA,
+  INSN_CLASS_ZCB_AND_ZBB,
+  INSN_CLASS_ZCB_AND_ZMMUL,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,