diff options
| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-05-20 20:51:49 +0900 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2022-05-20 22:21:30 +0800 |
| commit | aa8c9d60a6fc8865a5c4131aab243bf97b961e2c (patch) | |
| tree | 3b19354c999a0b2be87240673c027e9cfcb5925f /include | |
| parent | f270fd72f6694daa74cbd4d42a1ed3aaeddb8e38 (diff) | |
| download | gdb-aa8c9d60a6fc8865a5c4131aab243bf97b961e2c.zip gdb-aa8c9d60a6fc8865a5c4131aab243bf97b961e2c.tar.gz gdb-aa8c9d60a6fc8865a5c4131aab243bf97b961e2c.tar.bz2 | |
RISC-V: Remove RV128-only fmv instructions
As fmv.x.q and fmv.q.x instructions are RV128-only (not RV64-only),
it should be removed until RV128 support for GNU Binutils is required
again.
gas/ChangeLog:
* testsuite/gas/riscv/fmv.x.q-rv64-fail.d: New failure test.
* testsuite/gas/riscv/fmv.x.q-rv64-fail.l: Likewise.
* testsuite/gas/riscv/fmv.x.q-rv64-fail.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_FMV_X_Q, MASK_FMV_X_Q,
MATCH_FMV_Q_X, MASK_FMV_Q_X): Remove RV128-only instructions.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Remove RV128-only instructions.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index ecbb8b8..2e86796 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -389,8 +389,6 @@ #define MASK_FCVT_L_Q 0xfff0007f #define MATCH_FCVT_LU_Q 0xc6300053 #define MASK_FCVT_LU_Q 0xfff0007f -#define MATCH_FMV_X_Q 0xe6000053 -#define MASK_FMV_X_Q 0xfff0707f #define MATCH_FCLASS_Q 0xe6001053 #define MASK_FCLASS_Q 0xfff0707f #define MATCH_FCVT_S_W 0xd0000053 @@ -421,8 +419,6 @@ #define MASK_FCVT_Q_L 0xfff0007f #define MATCH_FCVT_Q_LU 0xd6300053 #define MASK_FCVT_Q_LU 0xfff0007f -#define MATCH_FMV_Q_X 0xf6000053 -#define MASK_FMV_Q_X 0xfff0707f #define MATCH_CLZ 0x60001013 #define MASK_CLZ 0xfff0707f #define MATCH_CTZ 0x60101013 @@ -2650,7 +2646,6 @@ DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) -DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) @@ -2666,7 +2661,6 @@ DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) -DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ) DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ) DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP) |