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| author | Renlin Li <renlin.li@arm.com> | 2016-12-13 12:37:18 +0000 |
|---|---|---|
| committer | Renlin Li <renlin.li@arm.com> | 2016-12-13 17:20:08 +0000 |
| commit | a6a51754740513db76fdee3aa153cdd51e87a24a (patch) | |
| tree | cd031cfc7ea3a40ab6b947955cba72f6984e83b7 /include | |
| parent | aa785360cfa271505394080c8e367017782ca57a (diff) | |
| download | gdb-a6a51754740513db76fdee3aa153cdd51e87a24a.zip gdb-a6a51754740513db76fdee3aa153cdd51e87a24a.tar.gz gdb-a6a51754740513db76fdee3aa153cdd51e87a24a.tar.bz2 | |
[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm field
The internal CN register representation for coprocessor fields used in aarch64
sys, sysl instructions are removed in this patch.
After the change, those fields are represented as immediate. Related checks are
added as well.
opcodes/
* aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
qualifier.
(operand_general_constraint_met_p): Remove case for CP_REG.
(aarch64_print_operand): Print CRn, CRm operand using imm field.
* aarch64-tbl.h (QL_SYS): Use CR qualifier.
(QL_SYSL): Likewise.
(aarch64_opcode_table): Change CRn, CRm operand class and type.
* aarch64-opc-2.c : Regenerate.
* aarch64-asm-2.c : Likewise.
* aarch64-dis-2.c : Likewise.
include/
* opcode/aarch64.h (aarch64_operand_class): Remove
AARCH64_OPND_CLASS_CP_REG.
(enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn,
AARCH64_OPND_Cm to AARCH64_OPND_CRm.
(aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier.
gas/
* config/tc-aarch64.c (AARCH64_REG_TYPES): Remove CN register.
(get_reg_expected_msg): Remove CN register case.
(parse_operands): rewrite parser for CRn, CRm operand.
(reg_names): Remove CN register.
* testsuite/gas/aarch64/diagnostic.s: Add a new test case.
* testsuite/gas/aarch64/diagnostic.l: Adjust error message.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 8 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 6 |
2 files changed, 11 insertions, 3 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index b8c9628..f65fabb 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,11 @@ +2016-12-13 Renlin Li <renlin.li@arm.com> + + * opcode/aarch64.h (aarch64_operand_class): Remove + AARCH64_OPND_CLASS_CP_REG. + (enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn, + AARCH64_OPND_Cm to AARCH64_OPND_CRm. + (aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier. + 2016-12-09 Maciej W. Rozycki <macro@imgtec.com> * opcode/mips.h: Remove references to `>' operand code. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 69645d0..f129a6d 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -113,7 +113,6 @@ enum aarch64_operand_class AARCH64_OPND_CLASS_SIMD_ELEMENT, AARCH64_OPND_CLASS_SISD_REG, AARCH64_OPND_CLASS_SIMD_REGLIST, - AARCH64_OPND_CLASS_CP_REG, AARCH64_OPND_CLASS_SVE_REG, AARCH64_OPND_CLASS_PRED_REG, AARCH64_OPND_CLASS_ADDRESS, @@ -170,8 +169,8 @@ enum aarch64_opnd structure to all lanes. */ AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ - AARCH64_OPND_Cn, /* Co-processor register in CRn field. */ - AARCH64_OPND_Cm, /* Co-processor register in CRm field. */ + AARCH64_OPND_CRn, /* Co-processor register in CRn field. */ + AARCH64_OPND_CRm, /* Co-processor register in CRm field. */ AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ @@ -394,6 +393,7 @@ enum aarch64_opnd_qualifier AARCH64_OPND_QLF_P_M, /* Constraint on value. */ + AARCH64_OPND_QLF_CR, /* CRn, CRm. */ AARCH64_OPND_QLF_imm_0_7, AARCH64_OPND_QLF_imm_0_15, AARCH64_OPND_QLF_imm_0_31, |