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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-06-30 22:43:55 +0200 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-07-01 07:28:40 -0600 |
| commit | 62edb233ef5fff5356c46570b3ba19dcbe6ceb35 (patch) | |
| tree | 96fdd45a48f4d3e2f6d94e5b7833760b82afe60a /include | |
| parent | fce8fef965904dc16ffba2388ba44003e61cd908 (diff) | |
| download | gdb-62edb233ef5fff5356c46570b3ba19dcbe6ceb35.zip gdb-62edb233ef5fff5356c46570b3ba19dcbe6ceb35.tar.gz gdb-62edb233ef5fff5356c46570b3ba19dcbe6ceb35.tar.bz2 | |
RISC-V: Add support for the Zvknh[a,b] ISA extensions
Zvknh[a,b] are parts of the vector crypto extensions.
This extension adds the following instructions:
- vsha2ms.vv
- vsha2c[hl].vv
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvknh[a,b].
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvknha.d: New test.
* testsuite/gas/riscv/zvknha_zvknhb.s: New test.
* testsuite/gas/riscv/zvknhb.d: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VSHA2CH_VV): New.
(MASK_VSHA2CH_VV): New.
(MATCH_VSHA2CL_VV): New.
(MASK_VSHA2CL_VV): New.
(MATCH_VSHA2MS_VV): New.
(MASK_VSHA2MS_VV): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvknh[a,b].
opcodes/ChangeLog:
* riscv-opc.c: Add Zvknh[a,b] instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc.h | 11 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 3 |
2 files changed, 14 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index b8c3834..95c4188 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2191,6 +2191,13 @@ #define MASK_VAESKF2_VI 0xfe00707f #define MATCH_VAESZ_VS 0xa603a077 #define MASK_VAESZ_VS 0xfe0ff07f +/* Zvknh[a,b] instructions. */ +#define MATCH_VSHA2CH_VV 0xba002077 +#define MASK_VSHA2CH_VV 0xfe00707f +#define MATCH_VSHA2CL_VV 0xbe002077 +#define MASK_VSHA2CL_VV 0xfe00707f +#define MATCH_VSHA2MS_VV 0xb6002077 +#define MASK_VSHA2MS_VV 0xfe00707f /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3337,6 +3344,10 @@ DECLARE_INSN(vaesem_vv, MATCH_VAESEM_VV, MASK_VAESEM_VV) DECLARE_INSN(vaeskf1_vi, MATCH_VAESKF1_VI, MASK_VAESKF1_VI) DECLARE_INSN(vaeskf2_vi, MATCH_VAESKF2_VI, MASK_VAESKF2_VI) DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS) +/* Zvknh[a,b] instructions. */ +DECLARE_INSN(vsha2ch_vv, MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV) +DECLARE_INSN(vsha2cl_vv, MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV) +DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 5d55dbc..77207ea 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -418,6 +418,9 @@ enum riscv_insn_class INSN_CLASS_ZVBC, INSN_CLASS_ZVKG, INSN_CLASS_ZVKNED, + INSN_CLASS_ZVKNHA, + INSN_CLASS_ZVKNHB, + INSN_CLASS_ZVKNHA_OR_ZVKNHB, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, |