[AArch64][SVE 21/32] Add Zn and Pn registers

This patch adds the Zn and Pn registers, and associated fields and
operands.

include/
	* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
	aarch64_operand_class.
	(AARCH64_OPND_CLASS_PRED_REG): Likewise.
	(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
	(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
	(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
	(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
	(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
	(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
	(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
	* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
	(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
	(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
	(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
	* aarch64-opc.c (fields): Add corresponding entries here.
	(operand_general_constraint_met_p): Check that SVE register lists
	have the correct length.  Check the ranges of SVE index registers.
	Check for cases where p8-p15 are used in 3-bit predicate fields.
	(aarch64_print_operand): Handle the new SVE operands.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
	* aarch64-asm.c (aarch64_ins_sve_index): New function.
	(aarch64_ins_sve_reglist): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
	* aarch64-dis.c (aarch64_ext_sve_index): New function.
	(aarch64_ext_sve_reglist): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
	(AARCH64_REG_TYPES): Add ZN and PN.
	(get_reg_expected_msg): Handle them.
	(parse_vector_type_for_operand): Add a reg_type parameter.
	Skip the width for Zn and Pn registers.
	(parse_typed_reg): Extend vector handling to Zn and Pn.  Update the
	call to parse_vector_type_for_operand.  Set HASVARTYPE for Zn and Pn,
	expecting the width to be 0.
	(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
	REG_TYPE_VN.
	(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
	(parse_operands): Handle the new Zn and Pn operands.
	(REGSET16): New macro, split out from...
	(REGSET31): ...here.
	(reg_names): Add Zn and Pn entries.

2 files changed, 34 insertions, 0 deletions

diff --git a/include/ChangeLog b/include/ChangeLog
index e6c3dbd..53d0ba0 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,18 @@
 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 
+	* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
+	aarch64_operand_class.
+	(AARCH64_OPND_CLASS_PRED_REG): Likewise.
+	(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
+	(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
+	(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
+	(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
+	(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
+	(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
+	(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
+
+2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
+
 	* opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
 	(AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
 
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index d39f10d..b0eb617 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -120,6 +120,8 @@ enum aarch64_operand_class
   AARCH64_OPND_CLASS_SISD_REG,
   AARCH64_OPND_CLASS_SIMD_REGLIST,
   AARCH64_OPND_CLASS_CP_REG,
+  AARCH64_OPND_CLASS_SVE_REG,
+  AARCH64_OPND_CLASS_PRED_REG,
   AARCH64_OPND_CLASS_ADDRESS,
   AARCH64_OPND_CLASS_IMMEDIATE,
   AARCH64_OPND_CLASS_SYSTEM,
@@ -241,6 +243,25 @@ enum aarch64_opnd
   AARCH64_OPND_BARRIER_ISB,	/* Barrier operand for ISB.  */
   AARCH64_OPND_PRFOP,		/* Prefetch operation.  */
   AARCH64_OPND_BARRIER_PSB,	/* Barrier operand for PSB.  */
+
+  AARCH64_OPND_SVE_Pd,		/* SVE p0-p15 in Pd.  */
+  AARCH64_OPND_SVE_Pg3,		/* SVE p0-p7 in Pg.  */
+  AARCH64_OPND_SVE_Pg4_5,	/* SVE p0-p15 in Pg, bits [8,5].  */
+  AARCH64_OPND_SVE_Pg4_10,	/* SVE p0-p15 in Pg, bits [13,10].  */
+  AARCH64_OPND_SVE_Pg4_16,	/* SVE p0-p15 in Pg, bits [19,16].  */
+  AARCH64_OPND_SVE_Pm,		/* SVE p0-p15 in Pm.  */
+  AARCH64_OPND_SVE_Pn,		/* SVE p0-p15 in Pn.  */
+  AARCH64_OPND_SVE_Pt,		/* SVE p0-p15 in Pt.  */
+  AARCH64_OPND_SVE_Za_5,	/* SVE vector register in Za, bits [9,5].  */
+  AARCH64_OPND_SVE_Za_16,	/* SVE vector register in Za, bits [20,16].  */
+  AARCH64_OPND_SVE_Zd,		/* SVE vector register in Zd.  */
+  AARCH64_OPND_SVE_Zm_5,	/* SVE vector register in Zm, bits [9,5].  */
+  AARCH64_OPND_SVE_Zm_16,	/* SVE vector register in Zm, bits [20,16].  */
+  AARCH64_OPND_SVE_Zn,		/* SVE vector register in Zn.  */
+  AARCH64_OPND_SVE_Zn_INDEX,	/* Indexed SVE vector register, for DUP.  */
+  AARCH64_OPND_SVE_ZnxN,	/* SVE vector register list in Zn.  */
+  AARCH64_OPND_SVE_Zt,		/* SVE vector register in Zt.  */
+  AARCH64_OPND_SVE_ZtxN,	/* SVE vector register list in Zt.  */
 };
 
 /* Qualifier constrains an operand.  It either specifies a variant of an