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authorPrzemyslaw Wirkus <przemyslaw.wirkus@arm.com>2021-11-17 20:26:53 +0000
committerPrzemyslaw Wirkus <przemyslaw.wirkus@arm.com>2021-11-17 20:27:42 +0000
commitd3de0860104b8bb8d496527fbb042c3b4c5c82dc (patch)
treed639da6b0a9e7bc01d3331c170d7e15099299203 /include
parent8f1bfdb44894423680a6d56a0994dafb4b82efca (diff)
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aarch64: [SME] SVE2 instructions added to support SME
This patch is adding new SVE2 instructions added to support SME extension. The following SVE2 instructions are added by the SME architecture: * PSEL, * REVD, SCLAMP and UCLAMP. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_pred_reg_with_index): New parser. (parse_operands): New parser. * testsuite/gas/aarch64/sme-9-illegal.d: New test. * testsuite/gas/aarch64/sme-9-illegal.l: New test. * testsuite/gas/aarch64/sme-9-illegal.s: New test. * testsuite/gas/aarch64/sme-9.d: New test. * testsuite/gas/aarch64/sme-9.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_PnT_Wm_imm. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_pred_reg_with_index): New inserter. * aarch64-dis.c (aarch64_ext_sme_pred_reg_with_index): New extractor. * aarch64-opc.c (aarch64_print_operand): Printout of OPND_SME_PnT_Wm_imm. * aarch64-opc.h (enum aarch64_field_kind): New bitfields FLD_SME_Rm, FLD_SME_i1, FLD_SME_tszh, FLD_SME_tszl. * aarch64-tbl.h (OP_SVE_NN_BHSD): New qualifier. (OP_SVE_QMQ): New qualifier. (struct aarch64_opcode): New instructions PSEL, REVD, SCLAMP and UCLAMP. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
Diffstat (limited to 'include')
-rw-r--r--include/opcode/aarch64.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index d111bb9..9448d35 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -455,6 +455,7 @@ enum aarch64_opnd
AARCH64_OPND_SME_ZA_array, /* SME ZA[<Wv>{, #<imm>}]. */
AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
+ AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
};