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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-11-09 11:09:12 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-11-09 11:19:44 +0000 |
| commit | 8edca81ece5df534c1cdd1f8362e7b5b9b090cfa (patch) | |
| tree | 7e07cdc4b08f84ca60406cc67afd31eaa71c8bf3 /include | |
| parent | a76bf0e55d84e8529a337cad278814ba2e30d3af (diff) | |
| download | gdb-8edca81ece5df534c1cdd1f8362e7b5b9b090cfa.zip gdb-8edca81ece5df534c1cdd1f8362e7b5b9b090cfa.tar.gz gdb-8edca81ece5df534c1cdd1f8362e7b5b9b090cfa.tar.bz2 | |
aarch64: Limit Rt register number for LS64 load/store instructions
Atomic 64-byte load/store instructions limit Rt register number to
values matching below condition (register <Xt> number must be even
and <= 22):
if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED;
This patch adds check if Rt fulfills above requirement.
For more details regarding atomic 64-byte load/store instruction for
Armv8.7 please refer to Arm A64 Instruction set documentation for
Armv8-A architecture profile, see document page 157 for load
instruction, and pages 414-418 for store instructions of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 846b3d1..5a4f453 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2020-11-09 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * opcode/aarch64.h (enum aarch64_opnd): Add new operand AARCH64_OPND_Rt_LS64. + 2020-11-06 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_PAC): Add new feature. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index ffde1ba..304c6cb 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -201,6 +201,7 @@ enum aarch64_opnd AARCH64_OPND_Rm, /* Integer register as source. */ AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ + AARCH64_OPND_Rt_LS64, /* Integer register used in LS64 instructions. */ AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */ AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ |