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authorAndrew Burgess <andrew.burgess@embecosm.com>2016-04-01 19:51:50 +0100
committerAndrew Burgess <andrew.burgess@embecosm.com>2016-04-19 22:51:27 +0100
commit537aefaf18444430df8126b474cf11ff7201b4c6 (patch)
treedb19856dded7bea0f5ff6e68ad2577bd49e4df0b /include
parentc8f785f220bab3c17fc93445ac509495d00d5afe (diff)
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opcodes/arc: Add yet more nps instructions
Add some more arc/nps400 instructions and the associated operands. There's also a test added into the assembler. gas/ChangeLog: * testsuite/gas/arc/nps400-6.d: New file. * testsuite/gas/arc/nps400-6.s: New file. include/ChangeLog: * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8. opcodes/ChangeLog: * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb, fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, and qcmp instructions. * arc-opc.c (insert_nps_bitop_size): Delete. (extract_nps_bitop_size): Delete. (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use. (extract_nps_qcmp_m3): Define. (extract_nps_qcmp_m2): Define. (extract_nps_qcmp_m1): Define. (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL. (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE, NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST, NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and NPS_QCMP_M3.
Diffstat (limited to 'include')
-rw-r--r--include/ChangeLog4
-rw-r--r--include/opcode/arc.h2
2 files changed, 5 insertions, 1 deletions
diff --git a/include/ChangeLog b/include/ChangeLog
index 9bd4a72..ec9adeb 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,9 @@
2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
+ * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.
+
+2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
+
* opcode/arc.h (insn_class_t): Add NET and ACL class.
2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 31daeb7..1d4a844 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -25,7 +25,7 @@
#define OPCODE_ARC_H
#ifndef MAX_INSN_ARGS
-#define MAX_INSN_ARGS 6
+#define MAX_INSN_ARGS 8
#endif
#ifndef MAX_INSN_FLGS