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| author | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2016-11-18 09:49:06 +0000 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2016-11-18 09:49:06 +0000 |
| commit | 3f06e55061d0d8f72dfd11f6c432c23f45d9b597 (patch) | |
| tree | 6f63bbc6a1be5e476b4333ef45e16516cc272869 /include | |
| parent | 6ec49e7c0aeb6d98e379319b565aee2c89388615 (diff) | |
| download | gdb-3f06e55061d0d8f72dfd11f6c432c23f45d9b597.zip gdb-3f06e55061d0d8f72dfd11f6c432c23f45d9b597.tar.gz gdb-3f06e55061d0d8f72dfd11f6c432c23f45d9b597.tar.bz2 | |
[AArch64] Add ARMv8.3 combined pointer authentication load instructions
Add support for ARMv8.3 LDRAA and LDRAB combined pointer authentication and
load instructions.
These instructions authenticate the base register and load 8 byte from it plus
a scaled 10-bit offset with optional writeback to update the base register.
A new instruction class (ldst_imm10) and operand type (AARCH64_OPND_ADDR_SIMM10)
were introduced to handle the special addressing form.
include/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
(enum aarch64_insn_class): Add ldst_imm10.
opcodes/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (QL_X1NIL): New.
(arch64_opcode_table): Add ldraa, ldrab.
(AARCH64_OPERANDS): Add "ADDR_SIMM10".
* aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
* aarch64-asm.c (aarch64_ins_addr_simm10): Define.
* aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
* aarch64-dis.c (aarch64_ext_addr_simm10): Define.
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
* aarch64-opc.c (fields): Add data for FLD_S_simm10.
(operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
(aarch64_print_operand): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_ADDR_SIMM10.
(fix_insn): Likewise.
(warn_unpredictable_ldst): Handle ldst_imm10.
* testsuite/gas/aarch64/pac.s: Add ldraa and ldrab tests.
* testsuite/gas/aarch64/pac.d: Likewise.
* testsuite/gas/aarch64/illegal-ldraa.s: New.
* testsuite/gas/aarch64/illegal-ldraa.l: New.
* testsuite/gas/aarch64/illegal-ldraa.d: New.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 2 |
2 files changed, 7 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index d9b7bca..9375bc8 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> + + * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10. + (enum aarch64_insn_class): Add ldst_imm10. + 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index a25b211..a35a813 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -225,6 +225,7 @@ enum aarch64_opnd friendly feature of using LDR/STR as the the mnemonic name for LDUR/STUR instructions wherever there is no ambiguity. */ + AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */ AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ @@ -465,6 +466,7 @@ enum aarch64_insn_class ldst_immpost, ldst_immpre, ldst_imm9, /* immpost or immpre */ + ldst_imm10, /* LDRAA/LDRAB */ ldst_pos, ldst_regoff, ldst_unpriv, |