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authorNelson Chu <nelson.chu@sifive.com>2021-01-28 10:45:56 +0800
committerNelson Chu <nelson.chu@sifive.com>2021-02-18 15:09:16 +0800
commit3d73d29e4eff8701ae6251347d03dd6057911178 (patch)
treece9f9774e088fdf2760261983841664b13dc1e4a /include
parent6a780b6766378e3dc9610cba7e12d7eaba196f52 (diff)
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RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.
Make the opcode/riscv-opc.c and include/opcode/riscv.h tidy, move the spec versions stuff to bfd/cpu-riscv.h. Also move the csr stuff and ext_version_table to gas/config/tc-riscv.c for internal use. To avoid too many repeated code, define general RISCV_GET_SPEC_NAME/SPEC_CLASS macros. Therefore, assembler/dis-assembler/linker/gdb can get all spec versions related stuff from cpu-riscv.h and cpu-riscv.c, since the stuff are defined there uniformly. bfd/ * Makefile.am: Added cpu-riscv.h. * Makefile.in: Regenerated. * po/SRC-POTFILES.in: Regenerated. * cpu-riscv.h: Added to support spec versions controlling. Also added extern arrays and functions for cpu-riscv.c. (enum riscv_spec_class): Define all spec classes here uniformly. (struct riscv_spec): Added for all specs. (RISCV_GET_SPEC_CLASS): Added to reduce repeated code. (RISCV_GET_SPEC_NAME): Likewise. (RISCV_GET_ISA_SPEC_CLASS): Added to get ISA spec class. (RISCV_GET_PRIV_SPEC_CLASS): Added to get privileged spec class. (RISCV_GET_PRIV_SPEC_NAME): Added to get privileged spec name. * cpu-riscv.c (struct priv_spec_t): Replaced with struct riscv_spec. (riscv_get_priv_spec_class): Replaced with RISCV_GET_PRIV_SPEC_CLASS. (riscv_get_priv_spec_name): Replaced with RISCV_GET_PRIV_SPEC_NAME. (riscv_priv_specs): Moved below. (riscv_get_priv_spec_class_from_numbers): Likewise, updated. (riscv_isa_specs): Moved from include/opcode/riscv.h. * elfnn-riscv.c: Included cpu-riscv.h. (riscv_merge_attributes): Initialize in_priv_spec and out_priv_spec. * elfxx-riscv.c: Included cpu-riscv.h and opcode/riscv.h. (RISCV_UNKNOWN_VERSION): Moved from include/opcode/riscv.h. * elfxx-riscv.h: Removed extern functions to cpu-riscv.h. gas/ * config/tc-riscv.c: Included cpu-riscv.h. (enum riscv_csr_clas): Moved from include/opcode/riscv.h. (struct riscv_csr_extra): Likewise. (struct riscv_ext_version): Likewise. (ext_version_table): Moved from opcodes/riscv-opc.c. (default_isa_spec): Updated type to riscv_spec_class. (default_priv_spec): Likewise. (riscv_set_default_isa_spec): Updated. (init_ext_version_hash): Likewise. (riscv_init_csr_hash): Likewise, also fixed indent. include/ * opcode/riscv.h: Moved stuff and make the file tidy. opcodes/ * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h. (default_priv_spec): Updated type to riscv_spec_class. (parse_riscv_dis_option): Updated. * riscv-opc.c: Moved stuff and make the file tidy.
Diffstat (limited to 'include')
-rw-r--r--include/ChangeLog4
-rw-r--r--include/opcode/riscv.h69
2 files changed, 4 insertions, 69 deletions
diff --git a/include/ChangeLog b/include/ChangeLog
index 6c3a835..0f4936e 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2021-02-18 Nelson Chu <nelson.chu@sifive.com>
+
+ * opcode/riscv.h: Moved stuff and make the file tidy.
+
2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
* opcode/s390.h (enum s390_opcode_cpu_val): Add
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 5432e6c..9372852 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -349,71 +349,6 @@ struct riscv_opcode
unsigned long pinfo;
};
-/* The current supported ISA spec versions. */
-enum riscv_isa_spec_class
-{
- ISA_SPEC_CLASS_NONE,
-
- ISA_SPEC_CLASS_2P2,
- ISA_SPEC_CLASS_20190608,
- ISA_SPEC_CLASS_20191213,
- ISA_SPEC_CLASS_DRAFT
-};
-
-#define RISCV_UNKNOWN_VERSION -1
-
-/* This structure holds version information for specific ISA. */
-struct riscv_ext_version
-{
- const char *name;
- enum riscv_isa_spec_class isa_spec_class;
- int major_version;
- int minor_version;
-};
-
-/* All RISC-V CSR belong to one of these classes. */
-enum riscv_csr_class
-{
- CSR_CLASS_NONE,
-
- CSR_CLASS_I,
- CSR_CLASS_I_32, /* RV32 only. */
- CSR_CLASS_F, /* F extension only. */
- CSR_CLASS_DEBUG /* Debug CSR. */
-};
-
-/* The current supported privilege spec versions. */
-enum riscv_priv_spec_class
-{
- PRIV_SPEC_CLASS_NONE,
-
- PRIV_SPEC_CLASS_1P9P1,
- PRIV_SPEC_CLASS_1P10,
- PRIV_SPEC_CLASS_1P11,
- PRIV_SPEC_CLASS_DRAFT
-};
-
-/* This structure holds all restricted conditions for a CSR. */
-struct riscv_csr_extra
-{
- /* Class to which this CSR belongs. Used to decide whether or
- not this CSR is legal in the current -march context. */
- enum riscv_csr_class csr_class;
-
- /* CSR may have differnet numbers in the previous priv spec. */
- unsigned address;
-
- /* Record the CSR is defined/valid in which versions. */
- enum riscv_priv_spec_class define_version;
-
- /* Record the CSR is aborted/invalid from which versions. If it isn't
- aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
- enum riscv_priv_spec_class abort_version;
-
- /* The CSR may have more than one setting. */
- struct riscv_csr_extra *next;
-};
-
/* Instruction is a simple alias (e.g. "mv" for "addi"). */
#define INSN_ALIAS 0x00000001
@@ -488,9 +423,5 @@ extern const char * const riscv_fpr_names_abi[NFPR];
extern const struct riscv_opcode riscv_opcodes[];
extern const struct riscv_opcode riscv_insn_types[];
-extern const struct riscv_ext_version riscv_ext_version_table[];
-
-extern int
-riscv_get_isa_spec_class (const char *, enum riscv_isa_spec_class *);
#endif /* _RISCV_H_ */