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authorChao-ying Fu <fu@mips.com>2013-10-14 18:41:17 +0000
committerChao-ying Fu <fu@mips.com>2013-10-14 18:41:17 +0000
commit387a82f12438b971c6e72fb1070495155b1532eb (patch)
treee813930a86b32b265a00593f217ee458309120d4 /include
parent63b8b2af80dcbd02419c2f41e6e0f63c52f0ebf9 (diff)
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2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX. (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL. For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. For MIPS, update extension character sequences after +. (ASE_MSA): New define. (ASE_MSA64): New define. For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. For microMIPS, update extension character sequences after +.
Diffstat (limited to 'include')
-rw-r--r--include/opcode/ChangeLog13
-rw-r--r--include/opcode/mips.h83
2 files changed, 89 insertions, 7 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index caf7aee..f645a7e 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,16 @@
+2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
+
+ * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
+ (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
+ For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
+ +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
+ For MIPS, update extension character sequences after +.
+ (ASE_MSA): New define.
+ (ASE_MSA64): New define.
+ For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
+ +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
+ For microMIPS, update extension character sequences after +.
+
2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
PR binutils/15834
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index f21697e..cb16d2a 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -413,7 +413,13 @@ enum mips_operand_type {
/* Like OP_VU0_SUFFIX, but used when the operand's value has already
been set. Any suffix used here must match the previous value. */
- OP_VU0_MATCH_SUFFIX
+ OP_VU0_MATCH_SUFFIX,
+
+ /* An index selected by an integer, e.g. [1]. */
+ OP_IMM_INDEX,
+
+ /* An index selected by a register, e.g. [$2]. */
+ OP_REG_INDEX
};
/* Enumerates the types of MIPS register. */
@@ -454,7 +460,13 @@ enum mips_reg_operand_type {
OP_REG_R5900_I,
OP_REG_R5900_Q,
OP_REG_R5900_R,
- OP_REG_R5900_ACC
+ OP_REG_R5900_ACC,
+
+ /* MSA registers $w0-$w31. */
+ OP_REG_MSA,
+
+ /* MSA control registers $0-$31. */
+ OP_REG_MSA_CTRL
};
/* Base class for all operands. */
@@ -891,6 +903,32 @@ struct mips_opcode
Enhanced VA Scheme:
"+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
+ MSA Extension:
+ "+d" 5-bit MSA register (FD)
+ "+e" 5-bit MSA register (FS)
+ "+h" 5-bit MSA register (FT)
+ "+k" 5-bit GPR at bit 6
+ "+l" 5-bit MSA control register at bit 6
+ "+n" 5-bit MSA control register at bit 11
+ "+o" 5-bit vector element index at bit 16
+ "+u" 4-bit vector element index at bit 16
+ "+v" 3-bit vector element index at bit 16
+ "+w" 2-bit vector element index at bit 16
+ "+T" (-512 .. 511) << 0 at bit 16
+ "+U" (-512 .. 511) << 1 at bit 16
+ "+V" (-512 .. 511) << 2 at bit 16
+ "+W" (-512 .. 511) << 3 at bit 16
+ "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
+ "+!" 3 bit unsigned bit position at bit 16
+ "+@" 4 bit unsigned bit position at bit 16
+ "+#" 6 bit unsigned bit position at bit 16
+ "+$" 5 bit unsigned immediate at bit 16
+ "+%" 5 bit signed immediate at bit 16
+ "+^" 10 bit signed immediate at bit 11
+ "+&" 0 vector element index
+ "+*" 5-bit register vector element index at bit 16
+ "+|" 8-bit mask at bit 16
+
Other:
"()" parens surrounding optional value
"," separates operands
@@ -905,8 +943,9 @@ struct mips_opcode
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
"1234567890"
- "ABCEFGHJKLMNPQSXZ"
- "abcfgijmpqrstxyz"
+ "~!@#$%^&*|"
+ "ABCEFGHJKLMNPQSTUVWXZ"
+ "abcdefghijklmnopqrstuvwxyz"
*/
/* These are the bits which may be set in the pinfo field of an
@@ -1115,6 +1154,9 @@ static const unsigned int mips_isa_table[] =
/* Virtualization ASE */
#define ASE_VIRT 0x00000200
#define ASE_VIRT64 0x00000400
+/* MSA Extension */
+#define ASE_MSA 0x00000800
+#define ASE_MSA64 0x00001000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -2044,6 +2086,33 @@ extern const int bfd_mips16_num_opcodes;
microMIPS Enhanced VA Scheme:
"+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
+ MSA Extension:
+ "+d" 5-bit MSA register (FD)
+ "+e" 5-bit MSA register (FS)
+ "+h" 5-bit MSA register (FT)
+ "+k" 5-bit GPR at bit 6
+ "+l" 5-bit MSA control register at bit 6
+ "+n" 5-bit MSA control register at bit 11
+ "+o" 5-bit vector element index at bit 16
+ "+u" 4-bit vector element index at bit 16
+ "+v" 3-bit vector element index at bit 16
+ "+w" 2-bit vector element index at bit 16
+ "+x" 5-bit shift amount at bit 16
+ "+T" (-512 .. 511) << 0 at bit 16
+ "+U" (-512 .. 511) << 1 at bit 16
+ "+V" (-512 .. 511) << 2 at bit 16
+ "+W" (-512 .. 511) << 3 at bit 16
+ "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
+ "+!" 3 bit unsigned bit position at bit 16
+ "+@" 4 bit unsigned bit position at bit 16
+ "+#" 6 bit unsigned bit position at bit 16
+ "+$" 5 bit unsigned immediate at bit 16
+ "+%" 5 bit signed immediate at bit 16
+ "+^" 10 bit signed immediate at bit 11
+ "+&" 0 vector element index
+ "+*" 5-bit register vector element index at bit 16
+ "+|" 8-bit mask at bit 16
+
Other:
"()" parens surrounding optional value
"," separates operands
@@ -2059,9 +2128,9 @@ extern const int bfd_mips16_num_opcodes;
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
""
- ""
- "ABCEFGH"
- "ij"
+ "~!@#$%^&*|"
+ "ABCEFGHTUVW"
+ "dehijklnouvwx"
Extension character sequences used so far ("m" followed by the
following), for quick reference when adding more: