RISC-V: Comments tidy and improvement.

The GNU coding standards said the comments should be complete sentences
and end with a period and two spaces.  But sometimes it should be more
cleaner when the comments only include a word or codes.  Therefore, I made
the following changes after referring to other target/generic codes,

* Try to write sentences in comments, must end with a period and two spaces.
* End with two spaces without a period for codes/instructions only.
* End with one space without a period for a single word/variable only.

Besids, also rewrite/remove some comments which are obsolete or too long,
and fix indents for comments.

bfd/
    * elfnn-riscv.c: Comments tidy and improvement.
    * elfxx-riscv.c: Likewise.
    * elfxx-riscv.h: Likewise.
gas/
    * config/tc-riscv.c: Comments tidy and improvement.  Also update
    comment "fallthru" to "Fall through" that end with a period and
    two spaces.
include/
    * elf/riscv.h: Comments tidy and improvement.
    * opcode/riscv-opc.h: Likewise.
    * opcode/riscv.h: Likewise.
opcodes/
    * riscv-dis.c: Comments tidy and improvement.
    * riscv-opc.c: Likewise.

2 files changed, 17 insertions, 31 deletions

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 38ce41d..c16f3f4 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -669,7 +669,7 @@
 #define MASK_CUSTOM3_RD_RS1  0x707f
 #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
 #define MASK_CUSTOM3_RD_RS1_RS2  0x707f
-/* Privileged CSR addresses (v1.11).  */
+/* Privileged CSR addresses.  */
 #define CSR_USTATUS 0x0
 #define CSR_UIE 0x4
 #define CSR_UTVEC 0x5
@@ -916,7 +916,7 @@
 #define CSR_TCONTROL 0x7a5
 #define CSR_MCONTEXT 0x7a8
 #define CSR_SCONTEXT 0x7aa
-#endif /* RISCV_ENCODING_H.  */
+#endif /* RISCV_ENCODING_H */
 #ifdef DECLARE_INSN
 DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
 DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
@@ -1238,9 +1238,9 @@ DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
 DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
 DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
-#endif /* DECLARE_INSN.  */
+#endif /* DECLARE_INSN */
 #ifdef DECLARE_CSR
-/* Privileged.  */
+/* Privileged CSRs.  */
 DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
 DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
 DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
@@ -1453,7 +1453,7 @@ DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR
 DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
 DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
 DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-/* Dropped.  */
+/* Dropped CSRs.  */
 DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
 DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
 DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
@@ -1472,7 +1472,7 @@ DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CL
 DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
 DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
 DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
-/* Unprivileged.  */
+/* Unprivileged CSRs.  */
 DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
@@ -1488,7 +1488,7 @@ DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_C
 DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
-#endif /* DECLARE_CSR.  */
+#endif /* DECLARE_CSR */
 #ifdef DECLARE_CSR_ALIAS
 DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
 DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
@@ -1502,4 +1502,4 @@ DECLARE_CSR_ALIAS(itrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, P
 DECLARE_CSR_ALIAS(etrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR_ALIAS(textra32, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR_ALIAS(textra64, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
-#endif /* DECLARE_CSR_ALIAS.  */
+#endif /* DECLARE_CSR_ALIAS */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 33ef290..e7dc2c7 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -29,13 +29,13 @@ typedef uint64_t insn_t;
 
 static inline unsigned int riscv_insn_length (insn_t insn)
 {
-  if ((insn & 0x3) != 0x3) /* RVC.  */
+  if ((insn & 0x3) != 0x3) /* RVC instructions.  */
     return 2;
-  if ((insn & 0x1f) != 0x1f) /* Base ISA and extensions in 32-bit space.  */
+  if ((insn & 0x1f) != 0x1f) /* 32-bit instructions.  */
     return 4;
-  if ((insn & 0x3f) == 0x1f) /* 48-bit extensions.  */
+  if ((insn & 0x3f) == 0x1f) /* 48-bit instructions.  */
     return 6;
-  if ((insn & 0x7f) == 0x3f) /* 64-bit extensions.  */
+  if ((insn & 0x7f) == 0x3f) /* 64-bit instructions.  */
     return 8;
   /* Longer instructions not supported at the moment.  */
   return 2;
@@ -291,11 +291,10 @@ static const char * const riscv_pred_succ[16] =
 #define EXTRACT_OPERAND(FIELD, INSN) \
   EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
 
-/* The maximal number of subset can be required. */
+/* The maximal number of subset can be required.  */
 #define MAX_SUBSET_NUM 4
 
 /* All RISC-V instructions belong to at least one of these classes.  */
-
 enum riscv_insn_class
   {
    INSN_CLASS_NONE,
@@ -319,7 +318,6 @@ enum riscv_insn_class
   };
 
 /* This structure holds information for a particular instruction.  */
-
 struct riscv_opcode
 {
   /* The name of the instruction.  */
@@ -351,7 +349,6 @@ struct riscv_opcode
 };
 
 /* The current supported ISA spec versions.  */
-
 enum riscv_isa_spec_class
 {
   ISA_SPEC_CLASS_NONE,
@@ -365,7 +362,6 @@ enum riscv_isa_spec_class
 #define RISCV_UNKNOWN_VERSION -1
 
 /* This structure holds version information for specific ISA.  */
-
 struct riscv_ext_version
 {
   const char *name;
@@ -375,19 +371,17 @@ struct riscv_ext_version
 };
 
 /* All RISC-V CSR belong to one of these classes.  */
-
 enum riscv_csr_class
 {
   CSR_CLASS_NONE,
 
   CSR_CLASS_I,
-  CSR_CLASS_I_32,      /* rv32 only */
-  CSR_CLASS_F,         /* f-ext only */
-  CSR_CLASS_DEBUG      /* debug CSR */
+  CSR_CLASS_I_32, /* RV32 only.  */
+  CSR_CLASS_F, /* F extension only.  */
+  CSR_CLASS_DEBUG /* Debug CSR.  */
 };
 
 /* The current supported privilege spec versions.  */
-
 enum riscv_priv_spec_class
 {
   PRIV_SPEC_CLASS_NONE,
@@ -399,7 +393,6 @@ enum riscv_priv_spec_class
 };
 
 /* This structure holds all restricted conditions for a CSR.  */
-
 struct riscv_csr_extra
 {
   /* Class to which this CSR belongs.  Used to decide whether or
@@ -452,14 +445,7 @@ struct riscv_csr_extra
    disassembler, and requires special treatment by the assembler.  */
 #define INSN_MACRO		0xffffffff
 
-/* This is a list of macro expanded instructions.
-
-   _I appended means immediate
-   _A appended means address
-   _AB appended means address with base register
-   _D appended means 64 bit floating point constant
-   _S appended means 32 bit floating point constant.  */
-
+/* This is a list of macro expanded instructions.  */
 enum
 {
   M_LA,