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| author | Alan Modra <amodra@gmail.com> | 2022-03-16 09:59:07 +1030 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2022-03-16 09:59:07 +1030 |
| commit | 42952a9605b00e4b1d6514de9b30e56d4dcb8bbe (patch) | |
| tree | 75c8dfbfc16defe8b00e99366c272fff18b62ed0 /include/opcode | |
| parent | 8f50b4b574b9f34c4f23ce6d6508f72e9c2f5a59 (diff) | |
| download | gdb-42952a9605b00e4b1d6514de9b30e56d4dcb8bbe.zip gdb-42952a9605b00e4b1d6514de9b30e56d4dcb8bbe.tar.gz gdb-42952a9605b00e4b1d6514de9b30e56d4dcb8bbe.tar.bz2 | |
PowerPC64 extended instructions in powerpc_macros
The extended instructions implemented in powerpc_macros aren't used by
the disassembler. That means instructions like "sldi r3,r3,2" appear
in disassembly as "rldicr r3,r3,2,61", which is annoying since many
other extended instructions are shown.
Note that some of the instructions moved out of the macro table to the
opcode table won't appear in disassembly, because they are aliases
rather than a subset of the underlying raw instruction. If enabled,
rotrdi, extrdi, extldi, clrlsldi, and insrdi would replace all
occurrences of rotldi, rldicl, rldicr, rldic and rldimi. (Or many
occurrences in the case of clrlsldi if n <= b was added to the extract
functions.)
The patch also fixes a small bug in opcode sanity checking.
include/
* opcode/ppc.h (PPC_OPSHIFT_SH6): Define.
opcodes/
* ppc-opc.c (insert_erdn, extract_erdn, insert_eldn, extract_eldn),
(insert_crdn, extract_crdn, insert_rrdn, extract_rrdn),
(insert_sldn, extract_sldn, insert_srdn, extract_srdn),
(insert_erdb, extract_erdb, insert_csldn, extract_csldb),
(insert_irdb, extract_irdn): New functions.
(ELDn, ERDn, ERDn, RRDn, SRDn, ERDb, CSLDn, CSLDb, IRDn, IRDb):
Define and add associated powerpc_operands entries.
(powerpc_opcodes): Add "rotrdi", "srdi", "extrdi", "clrrdi",
"sldi", "extldi", "clrlsldi", "insrdi" and corresponding record
(ie. dot suffix) forms.
(powerpc_macros): Delete same from here.
gas/
* config/tc-ppc.c (insn_validate): Don't modify value passed
to operand->insert for PPC_OPERAND_PLUS1 when calculating mask.
Handle PPC_OPSHIFT_SH6.
* testsuite/gas/ppc/prefix-reloc.d: Update.
* testsuite/gas/ppc/simpshft.d: Update.
ld/
* testsuite/ld-powerpc/elfv2so.d: Update.
* testsuite/ld-powerpc/notoc.d: Update.
* testsuite/ld-powerpc/notoc3.d: Update.
* testsuite/ld-powerpc/tlsdesc2.d: Update.
* testsuite/ld-powerpc/tlsget.d: Update.
* testsuite/ld-powerpc/tlsget2.d: Update.
* testsuite/ld-powerpc/tlsopt5.d: Update.
* testsuite/ld-powerpc/tlsopt6.d: Update.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ppc.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index a236b6b..463965d 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -336,9 +336,11 @@ extern const struct powerpc_operand powerpc_operands[]; extern const unsigned int num_powerpc_operands; /* Use with the shift field of a struct powerpc_operand to indicate - that BITM and SHIFT cannot be used to determine where the operand - goes in the insn. */ -#define PPC_OPSHIFT_INV (-1U << 31) + that BITM and SHIFT cannot be used to determine where the operand + goes in the insn. */ +#define PPC_OPSHIFT_INV (1U << 30) +/* A special case, 6-bit SH field. */ +#define PPC_OPSHIFT_SH6 (2U << 30) /* Values defined for the flags field of a struct powerpc_operand. Keep the register bits low: They need to fit in an unsigned short. */ |