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authorAndre Vieira <andre.simoesdiasvieira@arm.com>2022-11-14 16:47:22 +0000
committerAndre Vieira <andre.simoesdiasvieira@arm.com>2022-11-14 16:47:22 +0000
commit1f7b42d52a8cb690c259eaa4975a608e82d7267a (patch)
tree8e0d1faeeb5f8cfb1cf2caf218936c625ac46e98 /include/opcode
parent255571cdbf05213cc96feefb779c4158df453398 (diff)
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aarch64: Add support for Common Short Sequence Compression extension
This patch adds support for the CSSC extension and its corresponding instructions: ABS, CNT, CTZ, SMAX, UMAX, SMIN, UMIN. gas/ChangeLog: * config/tc-aarch64.c (parse_operands): Handle new operand types. * doc/c-aarch64.texi: Document new extension. * testsuite/gas/aarch64/cssc.d: New test. * testsuite/gas/aarch64/cssc.s: New test. include/ChangeLog: * opcode/aarch64.h (AARCH64_FEATURE_CSSC): New feature Macro. (enum aarch64_opnd): New operand types. (enum aarch64_insn_class): New instruction class. opcodes/ChangeLog: * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (operand_general_constraint_met_p): Update for new operand types. (aarch64_print_operand): Likewise. * aarch64-opc.h (enum aarch64_field_kind): Declare FLD_CSSC_imm8 field. * aarch64-tbl.h (aarch64_feature_cssc): Define new feature set. (CSSC): Define new feature set Macro. (CSSC_INSN): Define new instruction type. (aarch64_opcode_table): Add new instructions.
Diffstat (limited to 'include/opcode')
-rw-r--r--include/opcode/aarch64.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 9477ac9..838d423 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -99,6 +99,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_SME_F64 (1ULL << 57) /* SME F64. */
#define AARCH64_FEATURE_SME_I64 (1ULL << 58) /* SME I64. */
#define AARCH64_FEATURE_V8_8 (1ULL << 59) /* Armv8.8 processors. */
+#define AARCH64_FEATURE_CSSC (1ULL << 60) /* Common Short Sequence Compression instructions. */
/* Crypto instructions are the combination of AES and SHA2. */
#define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
@@ -492,7 +493,9 @@ enum aarch64_opnd
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */
AARCH64_OPND_MOPS_ADDR_Rs, /* [Rs]!, in bits [16, 20]. */
- AARCH64_OPND_MOPS_WB_Rn /* Rn!, in bits [5, 9]. */
+ AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */
+ AARCH64_OPND_CSSC_SIMM8, /* CSSC signed 8-bit immediate. */
+ AARCH64_OPND_CSSC_UIMM8, /* CSSC unsigned 8-bit immediate. */
};
/* Qualifier constrains an operand. It either specifies a variant of an
@@ -684,6 +687,7 @@ enum aarch64_insn_class
cryptosm4,
dotproduct,
bfloat16,
+ cssc,
};
/* Opcode enumerators. */