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| author | Yao Qi <yao.qi@linaro.org> | 2016-03-04 16:02:15 +0000 |
|---|---|---|
| committer | Yao Qi <yao.qi@linaro.org> | 2016-03-04 16:02:15 +0000 |
| commit | f1771dcebf80c75a13ca456491ddfb9b43fcaddf (patch) | |
| tree | 3ed38e990bf78b22eff4c28f2c5686d678e52130 /gold/ChangeLog | |
| parent | ca92db2d5885c03d3e0ed23c96b5c6ab336d908d (diff) | |
| download | gdb-f1771dcebf80c75a13ca456491ddfb9b43fcaddf.zip gdb-f1771dcebf80c75a13ca456491ddfb9b43fcaddf.tar.gz gdb-f1771dcebf80c75a13ca456491ddfb9b43fcaddf.tar.bz2 | |
ARM process record: VMOV
ARM process record gets the wrong register number for VMOV (from core
register to single-precision register). That is, we should record
the D register rather than the S pseudo register. The patch also
removes the condition "bit (arm_insn_r->arm_insn, 20)" check, which
has been checked above.
It fixes the following internal error,
(gdb) PASS: gdb.reverse/finish-precsave.exp: BP at end of main
continue^M
Continuing.^M
../../binutils-gdb/gdb/regcache.c:649: internal-error: regcache_raw_read: Assertion `regnum >= 0 && regnum < regcache->descr->nr_raw_registers' failed.^M
A problem internal to GDB has been detected,FAIL: gdb.reverse/finish-precsave.exp: run to end of main (GDB internal error)
gdb:
2016-03-04 Yao Qi <yao.qi@linaro.org>
* arm-tdep.c (arm_record_vdata_transfer_insn): Simplify the
condition check. Record the right D register number.
Diffstat (limited to 'gold/ChangeLog')
0 files changed, 0 insertions, 0 deletions