Extend rl78 prologue analyzer to recognize more complicated prologues

This patch extends the rl78 prologue analyzer so that it can recognize
this kind of prologue:

   0x119f <main>:       movw    ax, sp
   0x11a1 <main+2>:     subw    ax, #0x1fa6
   0x11a4 <main+5>:     movw    sp, ax

The test case for gdb.base/miscexprs.exp is now compiled to generate
that sequence instead of a much longer and more inefficient sequence.

gdb/ChangeLog:

	* rl78-tdep.c (RL78_SP_ADDR): Define.
	(opc_reg_to_gdb_regnum): New static function.
	(rl78_analyze_prologue): Recognize instructions forming slightly
	more interesting prologues.

2 files changed, 89 insertions, 0 deletions

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index d8aafa6..de21098 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,10 @@
+2015-04-21  Kevin Buettner  <kevinb@redhat.com>
+
+	* rl78-tdep.c (RL78_SP_ADDR): Define.
+	(opc_reg_to_gdb_regnum): New static function.
+	(rl78_analyze_prologue): Recognize instructions forming slightly
+	more interesting prologues.
+
 2015-04-20  Pierre-Marie de Rodat  <derodat@adacore.com>
 
 	Revert:
diff --git a/gdb/rl78-tdep.c b/gdb/rl78-tdep.c
index a63e7b8..bf96e88 100644
--- a/gdb/rl78-tdep.c
+++ b/gdb/rl78-tdep.c
@@ -205,6 +205,8 @@ enum
   RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS
 };
 
+#define RL78_SP_ADDR 0xffff8 
+
 /* Architecture specific data.  */
 
 struct gdbarch_tdep
@@ -786,6 +788,57 @@ struct rl78_get_opcode_byte_handle
   CORE_ADDR pc;
 };
 
+static int
+opc_reg_to_gdb_regnum (int opcreg)
+{
+  switch (opcreg)
+    {
+      case RL78_Reg_X:
+        return RL78_X_REGNUM;
+      case RL78_Reg_A:
+	return RL78_A_REGNUM;
+      case RL78_Reg_C:
+	return RL78_C_REGNUM;
+      case RL78_Reg_B:
+	return RL78_B_REGNUM;
+      case RL78_Reg_E:
+	return RL78_E_REGNUM;
+      case RL78_Reg_D:
+	return RL78_D_REGNUM;
+      case RL78_Reg_L:
+	return RL78_L_REGNUM;
+      case RL78_Reg_H:
+	return RL78_H_REGNUM;
+      case RL78_Reg_AX:
+	return RL78_AX_REGNUM;
+      case RL78_Reg_BC:
+	return RL78_BC_REGNUM;
+      case RL78_Reg_DE:
+	return RL78_DE_REGNUM;
+      case RL78_Reg_HL:
+	return RL78_HL_REGNUM;
+      case RL78_Reg_SP:
+	return RL78_SP_REGNUM;
+      case RL78_Reg_PSW:
+	return RL78_PSW_REGNUM;
+      case RL78_Reg_CS:
+	return RL78_CS_REGNUM;
+      case RL78_Reg_ES:
+	return RL78_ES_REGNUM;
+      case RL78_Reg_PMC:
+	return RL78_PMC_REGNUM;
+      case RL78_Reg_MEM:
+	return RL78_MEM_REGNUM;
+      default:
+	internal_error (__FILE__, __LINE__,
+			_("Undefined mapping for opc reg %d"),
+			opcreg);
+    }
+
+  /* Not reached.  */
+  return 0;
+}
+
 /* Fetch a byte on behalf of the opcode decoder.  HANDLE contains
    the memory address of the next byte to fetch.  If successful,
    the address in the handle is updated and the byte fetched is
@@ -900,6 +953,35 @@ rl78_analyze_prologue (CORE_ADDR start_pc,
 	                                         -addend);
 	  after_last_frame_setup_insn = next_pc;
 	}
+      else if (opc.id == RLO_mov
+               && opc.size == RL78_Word
+	       && opc.op[0].type == RL78_Operand_Register
+	       && opc.op[1].type == RL78_Operand_Indirect
+	       && opc.op[1].addend == RL78_SP_ADDR)
+	{
+	  reg[opc_reg_to_gdb_regnum (opc.op[0].reg)]
+	    = reg[RL78_SP_REGNUM];
+	}
+      else if (opc.id == RLO_sub
+               && opc.size == RL78_Word
+	       && opc.op[0].type == RL78_Operand_Register
+	       && opc.op[1].type == RL78_Operand_Immediate)
+	{
+	  int addend = opc.op[1].addend;
+	  int regnum = opc_reg_to_gdb_regnum (opc.op[0].reg);
+
+	  reg[regnum] = pv_add_constant (reg[regnum], -addend);
+	}
+      else if (opc.id == RLO_mov
+               && opc.size == RL78_Word
+	       && opc.op[0].type == RL78_Operand_Indirect
+	       && opc.op[0].addend == RL78_SP_ADDR
+	       && opc.op[1].type == RL78_Operand_Register)
+	{
+	  reg[RL78_SP_REGNUM]
+	    = reg[opc_reg_to_gdb_regnum (opc.op[1].reg)];
+	  after_last_frame_setup_insn = next_pc;
+	}
       else
 	{
 	  /* Terminate the prologue scan.  */