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authorAndrew Burgess <andrew.burgess@embecosm.com>2020-11-23 18:03:32 +0000
committerAndrew Burgess <andrew.burgess@embecosm.com>2020-12-02 18:30:42 +0000
commit25428040229b10f5a8a71be51dfc6ee2fc3f41b9 (patch)
tree46bdacdc7d2c7af58d4ea018a151b5c4cb5dd982 /gdb/features
parent533b2ae07d0437d0f9ae26f2067c1eab7999c5ba (diff)
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gdb/riscv: rewrite target description validation, add rv32e support
This commit started as adding rv32e support to gdb. The rv32e architecture is a cut-down rv32i, it only has 16 x-registers compared to the usual 32, and an rv32e target should not have any floating point registers. In order to add this I needed to adjust the target description validation checks that are performed from riscv_gdbarch_init, and I finally got fed up with the current scheme of doing these checks and rewrote this code. Unfortunately the rv32e changes are currently mixed in with the rewrite of the validation scheme. I could split these apart if anyone is really interested in seeing these two ideas as separate patches. The main idea behind this change is that where previously I tried to have a purely data driven approach, a set of tables one for each expected feature, and then a single generic function that would validate a feature given a table, I have created a new class for each feature. Each class has its own check member function which allows the logic for how to check each feature to be different. I think the new scheme is much easier to follow. There are some other changes that I made to the validation code as part of this commit. I've relaxed some of the checks related to the floating point CSRs. Previously the 3 CSRs fflags, frm, and fcsr all had to be present in either the fpu feature or the csr feature. This requirement is now relaxed, if the CSRs are not present then gdb will not reject the target description. My thinking here is that there's no gdb functionality that specifically requires these registers, and so, if a target offers a description without these registers nothing else in gdb should stop working. And as part of the rv32e support targets now only have to provide the first 16 x-registers and $pc. The second half of the x-registers (x16 -> x31) are now optional. gdb/ChangeLog: * arch/riscv.c: Include 'rv32e-xregs.c'. (riscv_create_target_description): Update to handle rv32e. * arch/riscv.h (struct riscv_gdbarch_features) <embedded>: New member variable. <operator==>: Update to account for new field. <hash>: Likewise. * features/Makefile (FEATURE_XMLFILES): Add riscv/rv32e-xregs.xml. * features/riscv/rv32e-xregs.c: Generated. * features/riscv/rv32e-xregs.xml: New file. * riscv-tdep.c (riscv_debug_breakpoints): Move from later in the file. (riscv_debug_infcall): Likewise. (riscv_debug_unwinder): Likewise. (riscv_debug_gdbarch): Likewise. (enum riscv_register_required_status): Delete. (struct riscv_register_feature): Add constructor, delete default constructor, copy, and assign constructors. (struct riscv_register_feature::register_info) <required>: Delete. <check>: Update comment and arguments. (struct riscv_register_feature) <name>: Change to member function. <prefer_first_name>: Delete. <tdesc_feature>: New member function. <registers>: Rename to... <m_registers>: ...this. <m_feature_name>: New member variable. (riscv_register_feature::register_info::check): Update arguments. (riscv_xreg_feature): Rewrite as class, create a single static instance of the class. (riscv_freg_feature): Likewise. (riscv_virtual_feature): Likewise. (riscv_csr_feature): Likewise. (riscv_create_csr_aliases): Has become a member function inside riscv_csr_feature class. (riscv_abi_embedded): New function definition. (riscv_register_name): Adjust to use new feature objects. (struct riscv_call_info) <riscv_call_info>: Check for rv32e abi, and adjust available argument registers. (riscv_features_from_gdbarch_info): Check for EF_RISCV_RVE flag. (riscv_check_tdesc_feature): Delete. (riscv_tdesc_unknown_reg): Adjust to use new feature objects. (riscv_gdbarch_init): Delete target description checking code, and instead call to the new feature objects to perform the checks. Reorder handling of no abi information case, allows small code simplification. (_initialize_riscv_tdep): Remove call, this is now done in the riscv_csr_feature constructor. * riscv-tdep.h (riscv_abi_embedded): Declare.
Diffstat (limited to 'gdb/features')
-rw-r--r--gdb/features/Makefile1
-rw-r--r--gdb/features/riscv/rv32e-xregs.c30
-rw-r--r--gdb/features/riscv/rv32e-xregs.xml31
3 files changed, 62 insertions, 0 deletions
diff --git a/gdb/features/Makefile b/gdb/features/Makefile
index d5b3236..61a4fe7 100644
--- a/gdb/features/Makefile
+++ b/gdb/features/Makefile
@@ -229,6 +229,7 @@ FEATURE_XMLFILES = aarch64-core.xml \
i386/64bit-pkeys.xml \
i386/64bit-sse.xml \
i386/x32-core.xml \
+ riscv/rv32e-xregs.xml \
riscv/32bit-cpu.xml \
riscv/32bit-fpu.xml \
riscv/64bit-cpu.xml \
diff --git a/gdb/features/riscv/rv32e-xregs.c b/gdb/features/riscv/rv32e-xregs.c
new file mode 100644
index 0000000..cda3319
--- /dev/null
+++ b/gdb/features/riscv/rv32e-xregs.c
@@ -0,0 +1,30 @@
+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
+ Original: rv32e-xregs.xml */
+
+#include "gdbsupport/tdesc.h"
+
+static int
+create_feature_riscv_rv32e_xregs (struct target_desc *result, long regnum)
+{
+ struct tdesc_feature *feature;
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.riscv.cpu");
+ tdesc_create_reg (feature, "zero", regnum++, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "ra", regnum++, 1, NULL, 32, "code_ptr");
+ tdesc_create_reg (feature, "sp", regnum++, 1, NULL, 32, "data_ptr");
+ tdesc_create_reg (feature, "gp", regnum++, 1, NULL, 32, "data_ptr");
+ tdesc_create_reg (feature, "tp", regnum++, 1, NULL, 32, "data_ptr");
+ tdesc_create_reg (feature, "t0", regnum++, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "t1", regnum++, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "t2", regnum++, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "fp", regnum++, 1, NULL, 32, "data_ptr");
+ tdesc_create_reg (feature, "s1", regnum++, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "a0", regnum++, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "a1", regnum++, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "a2", regnum++, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "a3", regnum++, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "a4", regnum++, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "a5", regnum++, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "pc", regnum++, 1, NULL, 32, "code_ptr");
+ return regnum;
+}
diff --git a/gdb/features/riscv/rv32e-xregs.xml b/gdb/features/riscv/rv32e-xregs.xml
new file mode 100644
index 0000000..8d313e8
--- /dev/null
+++ b/gdb/features/riscv/rv32e-xregs.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018-2020 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- Register numbers are hard-coded in order to maintain backward
+ compatibility with older versions of tools that didn't use xml
+ register descriptions. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="32" type="int" regnum="0"/>
+ <reg name="ra" bitsize="32" type="code_ptr"/>
+ <reg name="sp" bitsize="32" type="data_ptr"/>
+ <reg name="gp" bitsize="32" type="data_ptr"/>
+ <reg name="tp" bitsize="32" type="data_ptr"/>
+ <reg name="t0" bitsize="32" type="int"/>
+ <reg name="t1" bitsize="32" type="int"/>
+ <reg name="t2" bitsize="32" type="int"/>
+ <reg name="fp" bitsize="32" type="data_ptr"/>
+ <reg name="s1" bitsize="32" type="int"/>
+ <reg name="a0" bitsize="32" type="int"/>
+ <reg name="a1" bitsize="32" type="int"/>
+ <reg name="a2" bitsize="32" type="int"/>
+ <reg name="a3" bitsize="32" type="int"/>
+ <reg name="a4" bitsize="32" type="int"/>
+ <reg name="a5" bitsize="32" type="int"/>
+ <reg name="pc" bitsize="32" type="code_ptr"/>
+</feature>