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| author | Luis Machado <luis.machado@linaro.org> | 2021-11-17 10:02:44 -0300 |
|---|---|---|
| committer | Luis Machado <luis.machado@linaro.org> | 2021-11-17 10:55:44 -0300 |
| commit | 1aed145ad6475a3be195f0b3444c14ecd84068e4 (patch) | |
| tree | a7ed98bb2b432d2f16622eb79f7af648ac1a632a /gdb/features | |
| parent | c9dcc18f8ded97ed7cd1dd64da8c7b37b86f61bb (diff) | |
| download | gdb-1aed145ad6475a3be195f0b3444c14ecd84068e4.zip gdb-1aed145ad6475a3be195f0b3444c14ecd84068e4.tar.gz gdb-1aed145ad6475a3be195f0b3444c14ecd84068e4.tar.bz2 | |
Expose the BTI BTYPE more explicitly in the registers
Augment the register description XML to expose the BTI BTYPE field contained
in the CPSR register. It will be displayed like so:
cpsr 0x60001000 [ EL=0 BTYPE=0 SSBS C Z ]
Diffstat (limited to 'gdb/features')
| -rw-r--r-- | gdb/features/aarch64-core.c | 1 | ||||
| -rw-r--r-- | gdb/features/aarch64-core.xml | 3 |
2 files changed, 4 insertions, 0 deletions
diff --git a/gdb/features/aarch64-core.c b/gdb/features/aarch64-core.c index a080a64..bb70717 100644 --- a/gdb/features/aarch64-core.c +++ b/gdb/features/aarch64-core.c @@ -18,6 +18,7 @@ create_feature_aarch64_core (struct target_desc *result, long regnum) tdesc_add_flag (type_with_fields, 7, "I"); tdesc_add_flag (type_with_fields, 8, "A"); tdesc_add_flag (type_with_fields, 9, "D"); + tdesc_add_bitfield (type_with_fields, "BTYPE", 10, 11); tdesc_add_flag (type_with_fields, 12, "SSBS"); tdesc_add_flag (type_with_fields, 20, "IL"); tdesc_add_flag (type_with_fields, 21, "SS"); diff --git a/gdb/features/aarch64-core.xml b/gdb/features/aarch64-core.xml index d634569..a328ede 100644 --- a/gdb/features/aarch64-core.xml +++ b/gdb/features/aarch64-core.xml @@ -61,6 +61,9 @@ <!-- Debug exception mask. --> <field name="D" start="9" end="9"/> + <!-- ARMv8.5-A: Branch Target Identification BTYPE. --> + <field name="BTYPE" start="10" end="11"/> + <!-- ARMv8.0-A: Speculative Store Bypass. --> <field name="SSBS" start="12" end="12"/> |