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| author | Luis Machado <luis.machado@arm.com> | 2023-04-04 17:20:46 +0100 |
|---|---|---|
| committer | Luis Machado <luis.machado@arm.com> | 2023-10-04 16:23:40 +0100 |
| commit | 42019af621005a274d1a658f4c752a98fe5bab8e (patch) | |
| tree | e1ffbb608ef942726edb6a813fde7c2b5f4ac384 /gdb/arch | |
| parent | 6762e153a9e4e450b1a9904f9c96ec9f9b4cbc31 (diff) | |
| download | gdb-42019af621005a274d1a658f4c752a98fe5bab8e.zip gdb-42019af621005a274d1a658f4c752a98fe5bab8e.tar.gz gdb-42019af621005a274d1a658f4c752a98fe5bab8e.tar.bz2 | |
sme2: Enable SME2 for AArch64 gdb on Linux
SME2 defines a new 512-bit register named ZT0, and it is only available
if SME is also supported. The ZT0 state is valid only if the SVCR ZA bit
is enabled. Otherwise its contents are empty (0).
The target description is dynamic and gets generated at runtime based on the
availability of the feature.
Validated under Fast Models.
Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
Diffstat (limited to 'gdb/arch')
| -rw-r--r-- | gdb/arch/aarch64-scalable-linux.h | 6 | ||||
| -rw-r--r-- | gdb/arch/aarch64.c | 4 | ||||
| -rw-r--r-- | gdb/arch/aarch64.h | 12 |
3 files changed, 21 insertions, 1 deletions
diff --git a/gdb/arch/aarch64-scalable-linux.h b/gdb/arch/aarch64-scalable-linux.h index cb9d85a..0f59ddb 100644 --- a/gdb/arch/aarch64-scalable-linux.h +++ b/gdb/arch/aarch64-scalable-linux.h @@ -29,6 +29,12 @@ #define HWCAP2_SME (1 << 23) #endif +/* Feature check for Scalable Matrix Extension 2. */ +#ifndef HWCAP2_SME2 +#define HWCAP2_SME2 (1UL << 37) +#define HWCAP2_SME2P1 (1UL << 38) +#endif + /* Streaming mode enabled/disabled bit. */ #define SVCR_SM_BIT (1 << 0) /* ZA enabled/disabled bit. */ diff --git a/gdb/arch/aarch64.c b/gdb/arch/aarch64.c index e1f4948..c93d602 100644 --- a/gdb/arch/aarch64.c +++ b/gdb/arch/aarch64.c @@ -25,6 +25,7 @@ #include "../features/aarch64-pauth.c" #include "../features/aarch64-mte.c" #include "../features/aarch64-sme.c" +#include "../features/aarch64-sme2.c" #include "../features/aarch64-tls.c" /* See arch/aarch64.h. */ @@ -62,6 +63,9 @@ aarch64_create_target_description (const aarch64_features &features) regnum = create_feature_aarch64_sme (tdesc.get (), regnum, sve_vl_from_vq (features.svq)); + if (features.sme2) + regnum = create_feature_aarch64_sme2 (tdesc.get (), regnum); + return tdesc.release (); } diff --git a/gdb/arch/aarch64.h b/gdb/arch/aarch64.h index c1cd233..65c6205 100644 --- a/gdb/arch/aarch64.h +++ b/gdb/arch/aarch64.h @@ -48,6 +48,9 @@ struct aarch64_features These use at most 5 bits to represent. */ uint8_t svq = 0; + + /* Whether SME2 is supported. */ + bool sme2 = false; }; inline bool operator==(const aarch64_features &lhs, const aarch64_features &rhs) @@ -56,7 +59,8 @@ inline bool operator==(const aarch64_features &lhs, const aarch64_features &rhs) && lhs.pauth == rhs.pauth && lhs.mte == rhs.mte && lhs.tls == rhs.tls - && lhs.svq == rhs.svq; + && lhs.svq == rhs.svq + && lhs.sme2 == rhs.sme2; } namespace std @@ -79,6 +83,9 @@ namespace std gdb_assert (features.svq >= 0); gdb_assert (features.svq <= 16); h = h << 5 | (features.svq & 0x5); + + /* SME2 feature. */ + h = h << 1 | features.sme2; return h; } }; @@ -220,4 +227,7 @@ enum aarch64_regnum #define AARCH64_SME_MIN_SVL 128 #define AARCH64_SME_MAX_SVL 2048 +/* Size of the SME2 ZT0 register in bytes. */ +#define AARCH64_SME2_ZT0_SIZE 64 + #endif /* ARCH_AARCH64_H */ |