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| author | John Baldwin <jhb@FreeBSD.org> | 2022-05-03 16:05:10 -0700 |
|---|---|---|
| committer | John Baldwin <jhb@FreeBSD.org> | 2022-05-03 16:05:10 -0700 |
| commit | 414d5848bb2766ea7cef162c6ef5862ddb4dfe0f (patch) | |
| tree | 511591dee02b69591c22778866b65925acfb8b93 /gdb/arch | |
| parent | 684943d213b461a6a84ae67a9b8fcae5a28f007d (diff) | |
| download | gdb-414d5848bb2766ea7cef162c6ef5862ddb4dfe0f.zip gdb-414d5848bb2766ea7cef162c6ef5862ddb4dfe0f.tar.gz gdb-414d5848bb2766ea7cef162c6ef5862ddb4dfe0f.tar.bz2 | |
Add an aarch64-tls feature which includes the tpidr register.
Diffstat (limited to 'gdb/arch')
| -rw-r--r-- | gdb/arch/aarch64.c | 7 | ||||
| -rw-r--r-- | gdb/arch/aarch64.h | 8 |
2 files changed, 12 insertions, 3 deletions
diff --git a/gdb/arch/aarch64.c b/gdb/arch/aarch64.c index 485d667..733a3fd 100644 --- a/gdb/arch/aarch64.c +++ b/gdb/arch/aarch64.c @@ -24,11 +24,13 @@ #include "../features/aarch64-sve.c" #include "../features/aarch64-pauth.c" #include "../features/aarch64-mte.c" +#include "../features/aarch64-tls.c" /* See arch/aarch64.h. */ target_desc * -aarch64_create_target_description (uint64_t vq, bool pauth_p, bool mte_p) +aarch64_create_target_description (uint64_t vq, bool pauth_p, bool mte_p, + bool tls_p) { target_desc_up tdesc = allocate_target_description (); @@ -52,5 +54,8 @@ aarch64_create_target_description (uint64_t vq, bool pauth_p, bool mte_p) if (mte_p) regnum = create_feature_aarch64_mte (tdesc.get (), regnum); + if (tls_p) + regnum = create_feature_aarch64_tls (tdesc.get (), regnum); + return tdesc.release (); } diff --git a/gdb/arch/aarch64.h b/gdb/arch/aarch64.h index e416e34..8496a03 100644 --- a/gdb/arch/aarch64.h +++ b/gdb/arch/aarch64.h @@ -29,6 +29,7 @@ struct aarch64_features bool sve = false; bool pauth = false; bool mte = false; + bool tls = false; }; /* Create the aarch64 target description. A non zero VQ value indicates both @@ -36,10 +37,12 @@ struct aarch64_features an SVE Z register. HAS_PAUTH_P indicates the presence of the PAUTH feature. - MTE_P indicates the presence of the Memory Tagging Extension feature. */ + MTE_P indicates the presence of the Memory Tagging Extension feature. + + TLS_P indicates the presence of the Thread Local Storage feature. */ target_desc *aarch64_create_target_description (uint64_t vq, bool has_pauth_p, - bool mte_p); + bool mte_p, bool tls_p); /* Register numbers of various important registers. Note that on SVE, the Z registers reuse the V register numbers and the V @@ -91,6 +94,7 @@ enum aarch64_regnum #define AARCH64_NUM_REGS AARCH64_FPCR_REGNUM + 1 #define AARCH64_SVE_NUM_REGS AARCH64_SVE_VG_REGNUM + 1 +#define AARCH64_TLS_REGS_SIZE (8) /* There are a number of ways of expressing the current SVE vector size: |