Add support fpr MAXQ processor

54 files changed, 9825 insertions, 65 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index d5efcc7..99121ec 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
+	    Vineet Sharma      <vineets@noida.hcltech.com>
+
+	* configure.in: Add support for new target maxq-coff.
+	* configure: Regenerate.
+	* NEWS: Mention new support.
+	* config/tc-maxq.c: New file.
+	* config/tc-maxq.h: New file.
+	* config/obj-coff.h: Add support for maxq-coff.
+
 2004-11-08  Aaron W. LaFramboise <aaron98wiridge9@aaronwl.com>
 
 	* symbols.c (any_external_name): Define.
diff --git a/gas/NEWS b/gas/NEWS
index fb487c2..28db422 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Port to MAXQ processor contributed by HCL Tech.
+
 * Added support for generating unwind tables for ARM ELF targets.
 
 * Add a -g command line option to generate debug information in the target's
diff --git a/gas/config/obj-coff.h b/gas/config/obj-coff.h
index 90d7e99..e010a39 100644
--- a/gas/config/obj-coff.h
+++ b/gas/config/obj-coff.h
@@ -115,6 +115,11 @@
 #define TARGET_FORMAT "coff-h8500"
 #endif
 
+#ifdef TC_MAXQ20
+#include "coff/maxq.h"
+#define TARGET_FORMAT "coff-maxq"
+#endif
+
 #ifdef TC_SH
 
 #ifdef TE_PE
diff --git a/gas/config/tc-maxq.c b/gas/config/tc-maxq.c
new file mode 100644
index 0000000..e467e04
--- /dev/null
+++ b/gas/config/tc-maxq.c
@@ -0,0 +1,3185 @@
+/* tc-maxq.c -- assembler code for a MAXQ chip.
+
+   Copyright 2004 Free Software Foundation, Inc.
+
+   Contributed by HCL Technologies Pvt. Ltd.
+
+   Author: Vineet Sharma(vineets@noida.hcltech.com) Inderpreet
+   S.(inderpreetb@noida.hcltech.com)
+
+   This file is part of GAS.
+
+   GAS is free software; you can redistribute it and/or modify it under the
+   terms of the GNU General Public License as published by the Free Software
+   Foundation; either version 2, or (at your option) any later version.
+
+   GAS is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+   details.
+
+   You should have received a copy of the GNU General Public License along
+   with GAS; see the file COPYING.  If not, write to the Free Software
+   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "as.h"
+#include "safe-ctype.h"
+#include "subsegs.h"
+#include "dwarf2dbg.h"
+#include "tc-maxq.h"
+#include "opcode/maxq.h"
+#include "ctype.h"
+
+#ifndef MAXQ10S
+#define MAXQ10S 1
+#endif
+
+#ifndef _STRING_H
+#include "string.h"
+#endif
+
+#ifndef DEFAULT_ARCH
+#define DEFAULT_ARCH "MAXQ20"
+#endif
+
+#ifndef MAX_OPERANDS
+#define MAX_OPERANDS 2
+#endif
+
+#ifndef MAX_MNEM_SIZE
+#define MAX_MNEM_SIZE 8
+#endif
+
+#ifndef END_OF_INSN
+#define END_OF_INSN '\0'
+#endif
+
+#ifndef IMMEDIATE_PREFIX
+#define IMMEDIATE_PREFIX '#'
+#endif
+
+#ifndef MAX_REG_NAME_SIZE
+#define MAX_REG_NAME_SIZE 4
+#endif
+
+#ifndef MAX_MEM_NAME_SIZE
+#define MAX_MEM_NAME_SIZE 9
+#endif
+
+/* opcode for PFX[0].  */
+#define PFX0 0x0b
+
+/* Set default to MAXQ20.  */
+unsigned int max_version = 20;
+
+const char *default_arch = DEFAULT_ARCH;
+
+/* Type of the operand: Register,Immediate,Memory access,flag or bit.  */
+
+union _maxq20_op
+{
+  const reg_entry *  reg;
+  char               imms; /* This is to store the immediate value operand.  */
+  expressionS *      disps;
+  symbolS *          data;
+  const mem_access * mem;
+  int                flag;
+  const reg_bit *    r_bit;
+};
+
+typedef union _maxq20_op maxq20_opcode;
+
+/* For handling optional L/S in Maxq20.  */
+#ifdef BFD_ASSEMBLER
+
+/* Exposed For Linker - maps indirectly to the liker relocations.  */
+#define LONG_PREFIX  		MAXQ_LONGJUMP	/* BFD_RELOC_16 */
+#define SHORT_PREFIX 		MAXQ_SHORTJUMP	/* BFD_RELOC_16_PCREL_S2 */
+#define ABSOLUTE_ADDR_FOR_DATA 	MAXQ_INTERSEGMENT
+
+#define NO_PREFIX    		0
+#define EXPLICT_LONG_PREFIX     14
+
+#else
+
+#define EXPLICT_LONG_PREFIX 14
+#define LONG_PREFIX  5
+#define SHORT_PREFIX 1
+#define ABSOLUTE_ADDR_FOR_DATA 0
+#define NO_PREFIX    0
+
+#endif
+
+/* The main instruction structure containing fields to describe instrn */
+typedef struct _maxq20_insn
+{
+  /* The opcode information for the MAXQ20 */
+  MAXQ20_OPCODE_INFO op;
+
+  /* The number of operands */
+  unsigned int operands;
+
+  /* Number of different types of operands - Comments can be removed if reqd. 
+   */
+  unsigned int reg_operands, mem_operands, disp_operands, data_operands;
+  unsigned int imm_operands, imm_bit_operands, bit_operands, flag_operands;
+
+  /* Types of the individual operands */
+  UNKNOWN_OP types[MAX_OPERANDS];
+
+  /* Relocation type for operand : to be investigated into */
+  int reloc[MAX_OPERANDS];
+
+  /* Complete information of the Operands */
+  maxq20_opcode maxq20_op[MAX_OPERANDS];
+
+  /* Choice of prefix register whenever needed */
+  int prefix;
+
+  /* Optional Prefix for Instructions like LJUMP, SJUMP etc */
+  unsigned char Instr_Prefix;
+
+  /* 16 bit Instruction word */
+  unsigned char instr[2];
+}
+maxq20_insn;
+
+/* Definitions of all possible characters that can start an operand.  */
+const char *extra_symbol_chars = "@(#";
+
+/* Special Character that would start a comment.  */
+const char comment_chars[] = ";";
+
+/* Starts a comment when it appears at the start of a line.  */
+const char line_comment_chars[] = ";#";
+
+const char line_separator_chars[] = "";	/* originally may b by sudeep "\n".  */
+
+/*  The following are used for option processing.  */
+
+/* This is added to the mach independent string passed to getopt.  */
+const char *md_shortopts = "q";
+
+/* Characters for exponent and floating point.  */
+const char EXP_CHARS[] = "eE";
+const char FLT_CHARS[] = "";
+
+/* This is for the machine dependent option handling.  */
+#define OPTION_EB               (OPTION_MD_BASE + 0)
+#define OPTION_EL               (OPTION_MD_BASE + 1)
+#define MAXQ_10                 (OPTION_MD_BASE + 2)
+#define MAXQ_20			(OPTION_MD_BASE + 3)
+
+struct option md_longopts[] =
+{
+  {"MAXQ10", no_argument, NULL, MAXQ_10},
+  {"MAXQ20", no_argument, NULL, MAXQ_20},
+  {NULL, no_argument, NULL, 0}
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+/* md_undefined_symbol We have no need for this function.  */
+
+symbolS *
+md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
+{
+  return NULL;
+}
+
+int
+md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
+{
+  /* Any options support will be added onto this switch case.  */
+  switch (c)
+    {
+    case MAXQ_10:
+      max_version = 10;
+      break;
+    case MAXQ_20:
+      max_version = 20;
+      break;
+
+    default:
+      return 0;
+    }
+
+  return 1;
+}
+
+/* When a usage message is printed, this function is called and
+   it prints a description of the machine specific options.  */
+
+void
+md_show_usage (FILE * stream)
+{
+  /* Over here we will fill the description of the machine specific options.  */
+
+  fprintf (stream, _(" MAXQ-specific assembler options:\n"));
+
+  fprintf (stream, _("\
+	-MAXQ20		       generate obj for MAXQ20(default)\n\
+	-MAXQ10		       generate obj for MAXQ10\n\
+	"));
+}
+
+#ifdef BFD_ASSEMBLER
+unsigned long
+maxq20_mach (void)
+{
+  if (!(strcmp (default_arch, "MAXQ20")))
+    return 0;
+
+  as_fatal (_("Unknown architecture"));
+  return 1;
+}
+
+arelent *
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
+{
+  arelent *rel;
+  bfd_reloc_code_real_type code;
+
+  switch (fixp->fx_r_type)
+    {
+    case MAXQ_INTERSEGMENT:
+    case MAXQ_LONGJUMP:
+    case BFD_RELOC_16_PCREL_S2:
+      code = fixp->fx_r_type;
+      break;
+
+    case 0:
+    default:
+      switch (fixp->fx_size)
+	{
+	default:
+	  as_bad_where (fixp->fx_file, fixp->fx_line,
+			_("can not do %d byte relocation"), fixp->fx_size);
+	  code = BFD_RELOC_32;
+	  break;
+
+	case 1:
+	  code = BFD_RELOC_8;
+	  break;
+	case 2:
+	  code = BFD_RELOC_16;
+	  break;
+	case 4:
+	  code = BFD_RELOC_32;
+	  break;
+	}
+    }
+
+  rel = xmalloc (sizeof (arelent));
+  rel->sym_ptr_ptr  = xmalloc (sizeof (asymbol *));
+  *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+
+  rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
+  rel->addend  = fixp->fx_addnumber;
+  rel->howto   = bfd_reloc_type_lookup (stdoutput, code);
+
+  if (rel->howto == NULL)
+    {
+      as_bad_where (fixp->fx_file, fixp->fx_line,
+		    _("cannot represent relocation type %s"),
+		    bfd_get_reloc_code_name (code));
+
+      /* Set howto to a garbage value so that we can keep going.  */
+      rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
+      assert (rel->howto != NULL);
+    }
+
+  return rel;
+}
+
+#endif
+
+/* md_estimate_size_before_relax()
+
+   Called just before relax() for rs_machine_dependent frags.  The MAXQ
+   assembler uses these frags to handle 16 bit absolute jumps which require a 
+   prefix instruction to be inserted. Any symbol that is now undefined will
+   not become defined. Return the correct fr_subtype in the frag. Return the
+   initial "guess for variable size of frag"(This will be eiter 2 or 0) to
+   caller. The guess is actually the growth beyond the fixed part.  Whatever
+   we do to grow the fixed or variable part contributes to our returned
+   value.  */
+
+int
+md_estimate_size_before_relax (fragS *fragP, segT segment)
+{
+  /* Check whether the symbol has been resolved or not.
+     Otherwise we will have to generate a fixup.  */
+  if ((S_GET_SEGMENT (fragP->fr_symbol) != segment)
+      || fragP->fr_subtype == EXPLICT_LONG_PREFIX)
+    {
+      RELOC_ENUM reloc_type;
+      unsigned char *opcode;
+      int old_fr_fix;
+
+      /* Now this symbol has not been defined in this file.
+	 Hence we will have to create a fixup.  */
+      int size = 2;
+
+      /* This is for the prefix instruction.  */
+
+      if (fragP->fr_subtype == EXPLICT_LONG_PREFIX)
+	fragP->fr_subtype = LONG_PREFIX;
+
+      if (S_GET_SEGMENT (fragP->fr_symbol) != segment
+	  && ((!(fragP->fr_subtype) == EXPLICT_LONG_PREFIX)))
+	fragP->fr_subtype = ABSOLUTE_ADDR_FOR_DATA;
+
+      reloc_type =
+	(fragP->fr_subtype ? fragP->fr_subtype : ABSOLUTE_ADDR_FOR_DATA);
+
+      fragP->fr_subtype = reloc_type;
+
+      if (reloc_type == SHORT_PREFIX)
+	size = 0;
+      old_fr_fix = fragP->fr_fix;
+      opcode = (unsigned char *) fragP->fr_opcode;
+
+      fragP->fr_fix += (size);
+
+      fix_new (fragP, old_fr_fix - 2, size + 2,
+	       fragP->fr_symbol, fragP->fr_offset, 0, reloc_type);
+      frag_wane (fragP);
+      return fragP->fr_fix - old_fr_fix;
+    }
+
+  if (fragP->fr_subtype == SHORT_PREFIX)
+    {
+      fragP->fr_subtype = SHORT_PREFIX;
+      return 0;
+    }
+
+  if (fragP->fr_subtype == NO_PREFIX || fragP->fr_subtype == LONG_PREFIX)
+    {
+      unsigned long instr;
+      unsigned long call_addr;
+      long diff;
+      fragS *f;
+      diff = diff ^ diff;;
+      call_addr = call_addr ^ call_addr;
+      instr = 0;
+      f = NULL;
+
+      /* segment_info_type *seginfo = seg_info (segment);  */
+      instr = fragP->fr_address + fragP->fr_fix - 2;
+
+      /* This is the offset if it is a PC relative jump.  */
+      call_addr = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
+      diff = (call_addr - instr);
+
+      if (diff >= (-128 * 2) && diff <= (2 * 127))
+	{
+	  /* Now as offset is an 8 bit value, we will pass
+	     that to the jump instruction directly.  */
+	  fragP->fr_subtype = NO_PREFIX;
+	  return 0;
+	}
+
+      fragP->fr_subtype = LONG_PREFIX;
+      return 2;
+    }
+
+  as_fatal (_("Illegal Reloc type in md_estimate_size_before_relax for line : %d"),
+	    frag_now->fr_line);
+  return 0;
+}
+
+/* Equal to MAX_PRECISION in atof-ieee.c */
+#define MAX_LITTLENUMS 6
+
+/* Turn a string in input_line_pointer into a floating point constant of type 
+   TYPE, and store the appropriate bytes in *LITP.  The number of LITTLENUMS
+   emitted is stored in *SIZEP.  An error message is returned, or NULL on OK.  */
+
+char *
+md_atof (int type, char * litP, int * sizeP)
+{
+  int prec;
+  LITTLENUM_TYPE words[4];
+  char *t;
+  int i;
+
+  switch (type)
+    {
+    case 'f':
+      prec = 2;
+      break;
+
+    case 'd':
+      prec = 2;
+      /* The size of Double has been changed to 2 words ie 32 bits.  */
+      /* prec = 4; */
+      break;
+
+    default:
+      *sizeP = 0;
+      return _("bad call to md_atof");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+
+  *sizeP = prec * 2;
+
+  for (i = prec - 1; i >= 0; i--)
+    {
+      md_number_to_chars (litP, (valueT) words[i], 2);
+      litP += 2;
+    }
+
+  return NULL;
+}
+
+void
+maxq20_cons_fix_new (fragS * frag, unsigned int off, unsigned int len,
+		     expressionS * exp)
+{
+  int r = 0;
+
+  switch (len)
+    {
+    case 2:
+      r = MAXQ_WORDDATA;	/* Word+n */
+      break;
+    case 4:
+      r = MAXQ_LONGDATA;	/* Long+n */
+      break;
+    }
+
+  fix_new_exp (frag, off, len, exp, 0, r);
+  return;
+}
+
+short
+tc_coff_fix2rtype (fixS * fixP)
+{
+  return fixP->fx_r_type;
+}
+
+int
+tc_coff_sizemachdep (fragS *fragP)
+{
+  if (fragP->fr_next)
+    return (fragP->fr_next->fr_address - fragP->fr_address);
+
+  return 0;
+}
+
+/* GAS will call this for every rs_machine_dependent fragment. The
+   instruction is compleated using the data from the relaxation pass. It may
+   also create any necessary relocations.  */
+#ifdef BFD_ASSEMBLER
+void
+md_convert_frag (bfd *   headers ATTRIBUTE_UNUSED,
+		 segT    seg ATTRIBUTE_UNUSED,
+		 fragS * fragP)
+#else
+void
+md_convert_frag (object_headers * headers ATTRIBUTE_UNUSED,
+		 segT             sec ATTRIBUTE_UNUSED,
+		 fragS *          fragP)
+#endif
+{
+  unsigned char *opcode;
+  offsetT target_address;
+  offsetT opcode_address;
+  offsetT displacement_from_opcode_start;
+  int address;
+
+  opcode = fragP->fr_opcode;
+  address = 0;
+  target_address = opcode_address = displacement_from_opcode_start = 0;
+
+  target_address =
+    (S_GET_VALUE (fragP->fr_symbol) / MAXQ_OCTETS_PER_BYTE) +
+    (fragP->fr_offset / MAXQ_OCTETS_PER_BYTE);
+
+  opcode_address =
+    (fragP->fr_address / MAXQ_OCTETS_PER_BYTE) +
+    ((fragP->fr_fix - 2) / MAXQ_OCTETS_PER_BYTE);
+
+  displacement_from_opcode_start = (target_address - opcode_address);
+
+  if ((displacement_from_opcode_start >= -128
+       && displacement_from_opcode_start <= 127)
+      && (fragP->fr_subtype == SHORT_PREFIX
+	  || fragP->fr_subtype == NO_PREFIX))
+    {
+      /* Its a displacement.  */
+      char *p = (char *) &opcode[0];
+
+      *p = (char) displacement_from_opcode_start;
+    }
+  else
+    {
+      /* Its an absolute 16 bit jump. Now we have to
+	 load the prefix operator with the upper 8 bits.  */
+      if (fragP->fr_subtype == SHORT_PREFIX)
+	{
+	  as_bad (_("Cant make long jump/call into short jump/call : %d"),
+		  fragP->fr_line);
+	  return;
+	}
+
+      /* Check whether the symbol has been resolved or not.
+	 Otherwise we will have to generate a fixup.  */
+
+      if (fragP->fr_subtype != SHORT_PREFIX)
+	{
+	  RELOC_ENUM reloc_type;
+	  unsigned char *opcode;
+	  int old_fr_fix;
+	  int size = 2;
+
+	  /* Now this is a basolute jump/call.
+	     Hence we will have to create a fixup.  */
+	  if (fragP->fr_subtype == NO_PREFIX)
+	    fragP->fr_subtype = LONG_PREFIX;
+
+	  reloc_type =
+	    (fragP->fr_subtype ? fragP->fr_subtype : LONG_PREFIX);
+
+	  if (reloc_type == 1)
+	    size = 0;
+	  old_fr_fix = fragP->fr_fix;
+	  opcode = (unsigned char *) fragP->fr_opcode;
+
+	  fragP->fr_fix += (size);
+
+	  fix_new (fragP, old_fr_fix - 2, size + 2,
+		   fragP->fr_symbol, fragP->fr_offset, 0, reloc_type);
+	  frag_wane (fragP);
+	}
+    }
+}
+
+long
+md_pcrel_from (fixS *fixP)
+{
+  return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
+}
+
+/* Writes the val to the buf, where n is the nuumber of bytes to write.  */
+
+void
+maxq_number_to_chars (char *buf, valueT val, int n)
+{
+  if (target_big_endian)
+    number_to_chars_bigendian (buf, val, n);
+  else
+    number_to_chars_littleendian (buf, val, n);
+}
+
+/* GAS will call this for each fixup. It's main objective is to store the
+   correct value in the object file. 'fixup_segment' performs the generic
+   overflow check on the 'valueT *val' argument after md_apply_fix3 returns.
+   If the overflow check is relevant for the target machine, then
+   'md_apply_fix3' should modify 'valueT *val', typically to the value stored 
+   in the object file (not to be done in MAXQ).  */
+
+void
+md_apply_fix3 (fixS *fixP, valueT *valT, segT seg ATTRIBUTE_UNUSED)
+{
+  char *p = fixP->fx_frag->fr_literal + fixP->fx_where;
+  char *frag_to_fix_at =
+    fixP->fx_frag->fr_literal + fixP->fx_frag->fr_fix - 2;
+
+  if (fixP)
+    {
+      if (fixP->fx_frag && valT)
+	{
+	  /* If the relaxation substate is not defined we make it equal
+	     to the kind of relocation the fixup is generated for.  */
+	  if (!fixP->fx_frag->fr_subtype)
+	    fixP->fx_frag->fr_subtype = fixP->fx_r_type;
+
+	  /* For any instruction in which either we have specified an
+	     absolute address or it is a long jump we need to add a PFX0
+	     instruction to it. In this case as the instruction has already
+	     being written at 'fx_where' in the frag we copy it at the end of 
+	     the frag(which is where the relocation was generated) as when
+	     the relocation is generated the frag is grown by 2 type, this is 
+	     where we copy the contents of fx_where and add a pfx0 at
+	     fx_where.  */
+	  if ((fixP->fx_frag->fr_subtype == ABSOLUTE_ADDR_FOR_DATA)
+	      || (fixP->fx_frag->fr_subtype == LONG_PREFIX))
+	    {
+	      *(frag_to_fix_at + 1) = *(p + 1);
+	      maxq_number_to_chars (p + 1, PFX0, 1);
+	    }
+
+#ifdef BFD_ASSEMBLER
+	  /* Remember value for tc_gen_reloc.  */
+	  fixP->fx_addnumber = *valT;
+#endif
+	}
+
+      /* This prob can be fixed by defining tc_fix_adjustable.  */
+#ifndef BFD_ASSEMBLER
+      if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy))
+	segment_info[S_GET_SEGMENT (fixP->fx_addsy)].dot = NULL;
+#endif
+
+      /* Some fixups generated by GAS which gets resovled before this this
+         func. is called need to be wriiten to the frag as here we are going
+         to go away with the relocations fx_done=1.  */
+      if (fixP->fx_addsy == NULL)
+	{
+	  maxq_number_to_chars (p, *valT, fixP->fx_size);
+	  fixP->fx_addnumber = *valT;
+	  fixP->fx_done = 1;
+	}
+    }
+}
+
+/* Tables for lexical analysis.  */
+static char mnemonic_chars[256];
+static char register_chars[256];
+static char operand_chars[256];
+static char identifier_chars[256];
+static char digit_chars[256];
+
+/* Lexical Macros.  */
+#define is_mnemonic_char(x)   (mnemonic_chars[(unsigned char)(x)])
+#define is_register_char(x)   (register_chars[(unsigned char)(x)])
+#define is_operand_char(x)    (operand_chars[(unsigned char)(x)])
+#define is_space_char(x)      (x==' ')
+#define is_identifier_char(x) (identifier_chars[(unsigned char)(x)])
+#define is_digit_char(x)      (identifier_chars[(unsigned char)(x)])
+
+/* Special characters for operands.  */
+static char operand_special_chars[] = "[]@.-+";
+
+/* md_assemble() will always leave the instruction passed to it unaltered.
+   To do this we store the instruction in a special stack.  */
+static char save_stack[32];
+static char *save_stack_p;
+
+#define END_STRING_AND_SAVE(s)	\
+  do				\
+    {				\
+      *save_stack_p++ = *(s);	\
+      *s = '\0';		\
+    }				\
+  while (0)
+
+#define RESTORE_END_STRING(s)	\
+  do				\
+    {				\
+      *(s) = *(--save_stack_p);	\
+    }				\
+  while (0)
+
+/* The instruction we are assembling.  */
+static maxq20_insn i;
+
+/* The current template.  */
+static MAXQ20_OPCODES *current_templates;
+
+/* The displacement operand if any.  */
+static expressionS disp_expressions;
+
+/* Current Operand we are working on (0:1st operand,1:2nd operand).  */
+static int this_operand;
+
+/* The prefix instruction if used.  */
+static char PFX_INSN[2];
+static char INSERT_BUFFER[2];
+
+/* For interface with expression() ????? */
+extern char *input_line_pointer;
+
+/* The HASH Tables:  */
+
+/* Operand Hash Table.  */
+static struct hash_control *op_hash;
+
+/* Register Hash Table.  */
+static struct hash_control *reg_hash;
+
+/* Memory reference Hash Table.  */
+static struct hash_control *mem_hash;
+
+/* Bit hash table.  */
+static struct hash_control *bit_hash;
+
+/* Memory Access syntax table.  */
+static struct hash_control *mem_syntax_hash;
+
+/* This is a mapping from pseudo-op names to functions.  */
+
+const pseudo_typeS md_pseudo_table[] =
+{
+  {"int", cons, 2},		/* size of 'int' has been changed to 1 word
+				   (i.e) 16 bits.  */
+  {NULL, 0, 0},
+};
+
+#if defined(BFD_HEADERS)
+#ifdef RELSZ
+const int md_reloc_size = RELSZ;	/* Coff headers.  */
+#else
+const int md_reloc_size = 12;		/* Something else headers.  */
+#endif
+#else
+const int md_reloc_size = 12;		/* Not bfdized.  */
+#endif
+
+#define SET_PFX_ARG(x) (PFX_INSN[1] = x)
+
+
+/* This function sets the PFX value coresponding to the specs. Source
+   Destination Index Selection ---------------------------------- Write To|
+   SourceRegRange | Dest Addr Range
+   ------------------------------------------------------ PFX[0] | 0h-Fh |
+   0h-7h PFX[1] | 10h-1Fh | 0h-7h PFX[2] | 0h-Fh | 8h-Fh PFX[3] | 10h-1Fh |
+   8h-Fh PFX[4] | 0h-Fh | 10h-17h PFX[5] | 10h-1Fh | 10h-17h PFX[6] | 0h-Fh | 
+   18h-1Fh PFX[7] | 0h-Fh | 18h-1Fh */
+
+static void
+set_prefix (void)
+{
+  short int src_index = 0, dst_index = 0;
+
+  if (i.operands == 0)
+    return;
+  if (i.operands == 1)		/* Only SRC is Present */
+    {
+      if (i.types[0] == REG)
+	{
+	  if (!strcmp (i.op.name, "POP") || !strcmp (i.op.name, "POPI"))
+	    {
+	      dst_index = i.maxq20_op[0].reg[0].Mod_index;
+	      src_index = 0x00;
+	    }
+	  else
+	    {
+	      src_index = i.maxq20_op[0].reg[0].Mod_index;
+	      dst_index = 0x00;
+	    }
+	}
+    }
+
+  if (i.operands == 2)
+    {
+      if (i.types[0] == REG && i.types[1] == REG)
+	{
+	  dst_index = i.maxq20_op[0].reg[0].Mod_index;
+	  src_index = i.maxq20_op[1].reg[0].Mod_index;
+	}
+      else if (i.types[0] != REG && i.types[1] == REG)	/* DST is Absent */
+	{
+	  src_index = i.maxq20_op[1].reg[0].Mod_index;
+	  dst_index = 0x00;
+	}
+      else if (i.types[0] == REG && i.types[1] != REG)	/* Id SRC is Absent */
+	{
+	  dst_index = i.maxq20_op[0].reg[0].Mod_index;
+	  src_index = 0x00;
+	}
+      else if (i.types[0] == BIT && i.maxq20_op[0].r_bit)
+	{
+	  dst_index = i.maxq20_op[0].r_bit->reg->Mod_index;
+	  src_index = 0x00;
+	}
+
+      else if (i.types[1] == BIT && i.maxq20_op[1].r_bit)
+	{
+	  dst_index = 0x00;
+	  src_index = i.maxq20_op[1].r_bit->reg->Mod_index;
+	}
+    }
+
+  if (src_index >= 0x00 && src_index <= 0xF)
+    {
+      if (dst_index >= 0x00 && dst_index <= 0x07)
+	/* Set PFX[0] */
+	i.prefix = 0;
+
+      else if (dst_index >= 0x08 && dst_index <= 0x0F)
+	/* Set PFX[2] */
+	i.prefix = 2;
+
+      else if (dst_index >= 0x10 && dst_index <= 0x17)
+	/* Set PFX[4] */
+	i.prefix = 4;
+
+      else if (dst_index >= 0x18 && dst_index <= 0x1F)
+	/* Set PFX[6] */
+	i.prefix = 6;
+    }
+  else if (src_index >= 0x10 && src_index <= 0x1F)
+    {
+      if (dst_index >= 0x00 && dst_index <= 0x07)
+	/* Set PFX[1] */
+	i.prefix = 1;
+
+      else if (dst_index >= 0x08 && dst_index <= 0x0F)
+	/* Set PFX[3] */
+	i.prefix = 3;
+
+      else if (dst_index >= 0x10 && dst_index <= 0x17)
+	/* Set PFX[5] */
+	i.prefix = 5;
+
+      else if (dst_index >= 0x18 && dst_index <= 0x1F)
+	/* Set PFX[7] */
+	i.prefix = 7;
+    }
+}
+
+static unsigned char
+is_a_LSinstr (const char *ln_pointer)
+{
+  int i = 0;
+
+  for (i = 0; LSInstr[i] != NULL; i++)
+    if (!strcmp (LSInstr[i], ln_pointer))
+      return 1;
+
+  return 0;
+}
+
+static void
+LS_processing (const char *line)
+{
+  if (is_a_LSinstr (line))
+    {
+      if ((line[0] == 'L') || (line[0] == 'l'))
+	{
+	  i.prefix = 0;
+	  INSERT_BUFFER[0] = PFX0;
+	  i.Instr_Prefix = LONG_PREFIX;
+	}
+      else if ((line[0] == 'S') || (line[0] == 's'))
+	i.Instr_Prefix = SHORT_PREFIX;
+      else
+	i.Instr_Prefix = NO_PREFIX;
+    }
+  else
+    i.Instr_Prefix = LONG_PREFIX;
+}
+
+/* Separate mnemonics and the operands.  */
+
+static char *
+parse_insn (char *line, char *mnemonic)
+{
+  char *l = line;
+  char *token_start = l;
+  char *mnem_p;
+  char temp[MAX_MNEM_SIZE];
+  int ii = 0;
+
+  memset (temp, END_OF_INSN, MAX_MNEM_SIZE);
+  mnem_p = mnemonic;
+
+  while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
+    {
+      ii++;
+      mnem_p++;
+      if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
+	{
+	  as_bad (_("no such instruction: `%s'"), token_start);
+	  return NULL;
+	}
+      l++;
+    }
+
+  if (!is_space_char (*l) && *l != END_OF_INSN)
+    {
+      as_bad (_("invalid character %s in mnemonic"), l);
+      return NULL;
+    }
+
+  while (ii)
+    {
+      temp[ii - 1] = toupper ((char) mnemonic[ii - 1]);
+      ii--;
+    }
+
+  LS_processing (temp);
+
+  if (i.Instr_Prefix != 0 && is_a_LSinstr (temp))
+    /* Skip the optional L-S.  */
+    memcpy (temp, temp + 1, MAX_MNEM_SIZE);
+
+  /* Look up instruction (or prefix) via hash table.  */
+  current_templates = (MAXQ20_OPCODES *) hash_find (op_hash, temp);
+
+  if (current_templates != NULL)
+    return l;
+
+  as_bad (_("no such instruction: `%s'"), token_start);
+  return NULL;
+}
+
+/* Function to calculate x to the power of y.
+   Just to avoid including the math libraries.  */
+
+static int
+pwr (int x, int y)
+{
+  int k, ans = 1;
+
+  for (k = 0; k < y; k++)
+    ans *= x;
+
+  return ans;
+}
+
+static reg_entry *
+parse_reg_by_index (char *imm_start)
+{
+  int k = 0, mid = 0, rid = 0, val = 0, j = 0;
+  char temp[4] = { 0 };
+  reg_entry *reg = NULL;
+
+  do
+    {
+      if (isdigit (imm_start[k]))
+	temp[k] = imm_start[k] - '0';
+
+      else if (isalpha (imm_start[k])
+	       && (imm_start[k] = tolower (imm_start[k])) < 'g')
+	temp[k] = 10 + (int) (imm_start[k] - 'a');
+
+      else if (imm_start[k] == 'h')
+	break;
+
+      else if (imm_start[k] == END_OF_INSN)
+	{
+	  imm_start[k] = 'd';
+	  break;
+	}
+
+      else
+	return NULL;		/* not a hex digit */
+
+      k++;
+    }
+  while (imm_start[k] != '\n');
+
+  switch (imm_start[k])
+    {
+    case 'h':
+      for (j = 0; j < k; j++)
+	val += temp[j] * pwr (16, k - j - 1);
+      break;
+
+    case 'd':
+      for (j = 0; j < k; j++)
+	{
+	  if (temp[j] > 9)
+	    return NULL;	/* not a number */
+
+	  val += temp[j] * pwr (10, k - j - 1);
+	  break;
+	}
+    }
+
+  /* Get the module and register id's.  */
+  mid = val & 0x0f;
+  rid = (val >> 4) & 0x0f;
+
+  if (mid < 6)
+    {
+      /* Search the pheripheral reg table.  */
+      for (j = 0; j < num_of_reg; j++)
+	{
+	  if (new_reg_table[j].opcode == val)
+	    {
+	      reg = (reg_entry *) & new_reg_table[j];
+	      break;
+	    }
+	}
+    }
+
+  else
+    {
+      /* Search the system register table.  */
+      j = 0;
+
+      while (system_reg_table[j].reg_name != NULL)
+	{
+	  if (system_reg_table[j].opcode == val)
+	    {
+	      reg = (reg_entry *) & system_reg_table[j];
+	      break;
+	    }
+	  j++;
+	}
+    }
+
+  if (reg == NULL)
+    {
+      as_bad (_("Invalid register value %s"), imm_start);
+      return reg;
+    }
+
+#if CHANGE_PFX
+  if (this_operand == 0 && reg != NULL)
+    {
+      if (reg->Mod_index > 7)
+	i.prefix = 2;
+      else
+	i.prefix = 0;
+    }
+#endif
+  return (reg_entry *) reg;
+}
+
+/* REG_STRING starts *before* REGISTER_PREFIX.  */
+
+static reg_entry *
+parse_register (char *reg_string, char **end_op)
+{
+  char *s = reg_string;
+  char *p = NULL;
+  char reg_name_given[MAX_REG_NAME_SIZE + 1];
+  reg_entry *r = NULL;
+
+  r = NULL;
+  p = NULL;
+
+  /* Skip possible REGISTER_PREFIX and possible whitespace.  */
+  if (is_space_char (*s))
+    ++s;
+
+  p = reg_name_given;
+  while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
+    {
+      if (p >= reg_name_given + MAX_REG_NAME_SIZE)
+	return (reg_entry *) NULL;
+      s++;
+    }
+
+  *end_op = s;
+
+  r = (reg_entry *) hash_find (reg_hash, reg_name_given);
+
+#if CHANGE_PFX
+  if (this_operand == 0 && r != NULL)
+    {
+      if (r->Mod_index > 7)
+	i.prefix = 2;
+      else
+	i.prefix = 0;
+    }
+#endif
+  return r;
+}
+
+static reg_bit *
+parse_register_bit (char *reg_string, char **end_op)
+{
+  const char *s = reg_string;
+  short k = 0;
+  char diff = 0;
+  reg_bit *rb = NULL;
+  reg_entry *r = NULL;
+  bit_name *b = NULL;
+  char temp_bitname[MAX_REG_NAME_SIZE + 2];
+  char temp[MAX_REG_NAME_SIZE + 1];
+
+  memset (&temp, '\0', (MAX_REG_NAME_SIZE + 1));
+  memset (&temp_bitname, '\0', (MAX_REG_NAME_SIZE + 2));
+
+  diff = 0;
+  r = NULL;
+  rb = NULL;
+  rb = xmalloc (sizeof (reg_bit));
+  rb->reg = xmalloc (sizeof (reg_entry));
+  k = 0;
+
+  /* For supporting bit names.  */
+  b = (bit_name *) hash_find (bit_hash, reg_string);
+
+  if (b != NULL)
+    {
+      *end_op = reg_string + strlen (reg_string);
+      strcpy (temp_bitname, b->reg_bit);
+      s = temp_bitname;
+    }
+
+  if (strchr (s, '.'))
+    {
+      while (*s != '.')
+	{
+	  if (*s == '\0')
+	    return NULL;
+	  temp[k] = *s++;
+
+	  k++;
+	}
+      temp[k] = '\0';
+    }
+
+  if ((r = parse_register (temp, end_op)) == NULL)
+    return NULL;
+
+  rb->reg = r;
+
+  /* Skip the "."  */
+  s++;
+
+  if (isdigit ((char) *s))
+    rb->bit = atoi (s);
+  else if (isalpha ((char) *s))
+    {
+      rb->bit = (char) *s - 'a';
+      rb->bit += 10;
+      if (rb->bit > 15)
+	{
+	  as_bad (_("Invalid bit number : '%c'"), (char) *s);
+	  return NULL;
+	}
+    }
+
+  if (b != NULL)
+    diff = strlen (temp_bitname) - strlen (temp) - 1;
+  else
+    diff = strlen (reg_string) - strlen (temp) - 1;
+
+  if (*(s + diff) != '\0')
+    {
+      as_bad (_("Illegal character after operand '%s'"), reg_string);
+      return NULL;
+    }
+
+  return rb;
+}
+
+static void
+pfx_for_imm_val (int arg)
+{
+  if (i.prefix == -1)
+    return;
+
+  if (i.prefix == 0 && arg == 0 && PFX_INSN[1] == 0 && !(i.data_operands))
+    return;
+
+  if (!(i.prefix < 0) && !(i.prefix > 7))
+    PFX_INSN[0] = (i.prefix << 4) | PFX0;
+
+  if (!PFX_INSN[1])
+    PFX_INSN[1] = arg;
+
+}
+
+static int
+maxq20_immediate (char *imm_start)
+{
+  int val = 0, val_pfx = 0;
+  char sign_val = 0;
+  int k = 0, j;
+  int temp[4] = { 0 };
+
+  imm_start++;
+
+  if (imm_start[1] == '\0' && (imm_start[0] == '0' || imm_start[0] == '1')
+      && (this_operand == 1 && ((i.types[0] == BIT || i.types[0] == FLAG))))
+    {
+      val = imm_start[0] - '0';
+      i.imm_bit_operands++;
+      i.types[this_operand] = IMMBIT;
+      i.maxq20_op[this_operand].imms = (char) val;
+#if CHANGE_PFX
+      if (i.prefix == 2)
+	pfx_for_imm_val (0);
+#endif
+      return 1;
+    }
+
+  /* Check For Sign Charcater.  */
+  sign_val = 0;
+
+  do
+    {
+      if (imm_start[k] == '-' && k == 0)
+	sign_val = -1;
+
+      else if (imm_start[k] == '+' && k == 0)
+	sign_val = 1;
+
+      else if (isdigit (imm_start[k]))
+	temp[k] = imm_start[k] - '0';
+
+      else if (isalpha (imm_start[k])
+	       && (imm_start[k] = tolower (imm_start[k])) < 'g')
+	temp[k] = 10 + (int) (imm_start[k] - 'a');
+
+      else if (imm_start[k] == 'h')
+	break;
+
+      else if (imm_start[k] == '\0')
+	{
+	  imm_start[k] = 'd';
+	  break;
+	}
+      else
+	{
+	  as_bad (_("Invalid Character in immediate Value : %c"),
+		  imm_start[k]);
+	  return 0;
+	}
+      k++;
+    }
+  while (imm_start[k] != '\n');
+
+  switch (imm_start[k])
+    {
+    case 'h':
+      for (j = (sign_val ? 1 : 0); j < k; j++)
+	val += temp[j] * pwr (16, k - j - 1);
+      break;
+
+    case 'd':
+      for (j = (sign_val ? 1 : 0); j < k; j++)
+	{
+	  if (temp[j] > 9)
+	    {
+	      as_bad (_("Invalid Character in immediate value : %c"),
+		      imm_start[j]);
+	      return 0;
+	    }
+	  val += temp[j] * pwr (10, k - j - 1);
+	}
+    }
+
+  if (!sign_val)
+    sign_val = 1;
+
+  /* Now over here the value val stores the 8 bit/16 bit value. We will put a 
+     check if we are moving a 16 bit immediate value into an 8 bit register. 
+     In that case we will generate a warning and move only the lower 8 bits */
+  if (val > 65535)
+    {
+      as_bad (_("Immediate value greater than 16 bits"));
+      return 0;
+    }
+
+  val = val * sign_val;
+
+  /* If it is a stack pointer and the value is greater than the maximum
+     permissible size */
+  if (this_operand == 1)
+    {
+      if ((val * sign_val) > MAX_STACK && i.types[0] == REG
+	  && !strcmp (i.maxq20_op[0].reg->reg_name, "SP"))
+	{
+	  as_warn (_
+		   ("Attempt to move a value in the stack pointer greater than the size of the stack"));
+	  val = val & MAX_STACK;
+	}
+
+      /* Check the range for 8 bit registers.  */
+      else if (((val * sign_val) > 0xFF) && (i.types[0] == REG)
+	       && (i.maxq20_op[0].reg->rtype == Reg_8W))
+	{
+	  as_warn (_
+		   ("Attempt to move 16 bit value into an 8 bit register.Truncating..\n"));
+	  val = val & 0xfe;
+	}
+
+      else if (((sign_val == -1) || (val > 0xFF)) && (i.types[0] == REG)
+	       && (i.maxq20_op[0].reg->rtype == Reg_8W))
+	{
+	  val_pfx = val >> 8;
+	  val = ((val) & 0x00ff);
+	  SET_PFX_ARG (val_pfx);
+	  i.maxq20_op[this_operand].imms = (char) val;
+	}
+
+      else if ((val <= 0xff) && (i.types[0] == REG)
+	       && (i.maxq20_op[0].reg->rtype == Reg_8W))
+	i.maxq20_op[this_operand].imms = (char) val;
+
+
+      /* Check for 16 bit registers.  */
+      else if (((sign_val == -1) || val > 0xFE) && i.types[0] == REG
+	       && i.maxq20_op[0].reg->rtype == Reg_16W)
+	{
+	  /* Add PFX for any negative value -> 16bit register.  */
+	  val_pfx = val >> 8;
+	  val = ((val) & 0x00ff);
+	  SET_PFX_ARG (val_pfx);
+	  i.maxq20_op[this_operand].imms = (char) val;
+	}
+
+      else if (val < 0xFF && i.types[0] == REG
+	       && i.maxq20_op[0].reg->rtype == Reg_16W)
+	{
+	  i.maxq20_op[this_operand].imms = (char) val;
+	}
+
+      /* All the immediate memory access - no PFX.  */
+      else if (i.types[0] == MEM)
+	{
+	  if ((sign_val == -1) || val > 0xFE)
+	    {
+	      val_pfx = val >> 8;
+	      val = ((val) & 0x00ff);
+	      SET_PFX_ARG (val_pfx);
+	      i.maxq20_op[this_operand].imms = (char) val;
+	    }
+	  else
+	    i.maxq20_op[this_operand].imms = (char) val;
+	}
+
+      /* Special handling for immediate jumps like jump nz, #03h etc.  */
+      else if (val < 0xFF && i.types[0] == FLAG)
+	i.maxq20_op[this_operand].imms = (char) val;
+
+      else if ((((sign_val == -1) || val > 0xFE)) && i.types[0] == FLAG)
+	{
+	  val_pfx = val >> 8;
+	  val = ((val) & 0x00ff);
+	  SET_PFX_ARG (val_pfx);
+	  i.maxq20_op[this_operand].imms = (char) val;
+	}
+      else
+	{
+	  as_bad (_("Invalid immediate move operation"));
+	  return 0;
+	}
+    }
+  else
+    {
+      /* All the instruction with operation on ACC: like ADD src, etc.  */
+      if ((sign_val == -1) || val > 0xFE)
+	{
+	  val_pfx = val >> 8;
+	  val = ((val) & 0x00ff);
+	  SET_PFX_ARG (val_pfx);
+	  i.maxq20_op[this_operand].imms = (char) val;
+	}
+      else
+	i.maxq20_op[this_operand].imms = (char) val;
+    }
+
+  i.imm_operands++;
+  return 1;
+}
+
+static int
+extract_int_val (const char *imm_start)
+{
+  int k, j, val;
+  char sign_val;
+  int temp[4];
+
+  k = 0;
+  j = 0;
+  val = 0;
+  sign_val = 0;
+  do
+    {
+      if (imm_start[k] == '-' && k == 0)
+	sign_val = -1;
+
+      else if (imm_start[k] == '+' && k == 0)
+	sign_val = 1;
+
+      else if (isdigit (imm_start[k]))
+	temp[k] = imm_start[k] - '0';
+
+      else if (isalpha (imm_start[k]) && (tolower (imm_start[k])) < 'g')
+	temp[k] = 10 + (int) (tolower (imm_start[k]) - 'a');
+
+      else if (tolower (imm_start[k]) == 'h')
+	break;
+
+      else if ((imm_start[k] == '\0') || (imm_start[k] == ']'))
+	/* imm_start[k]='d'; */
+	break;
+
+      else
+	{
+	  as_bad (_("Invalid Character in immediate Value : %c"),
+		  imm_start[k]);
+	  return 0;
+	}
+      k++;
+    }
+  while (imm_start[k] != '\n');
+
+  switch (imm_start[k])
+    {
+    case 'h':
+      for (j = (sign_val ? 1 : 0); j < k; j++)
+	val += temp[j] * pwr (16, k - j - 1);
+      break;
+
+    default:
+      for (j = (sign_val ? 1 : 0); j < k; j++)
+	{
+	  if (temp[j] > 9)
+	    {
+	      as_bad (_("Invalid Character in immediate value : %c"),
+		      imm_start[j]);
+	      return 0;
+	    }
+	  val += temp[j] * pwr (10, k - j - 1);
+	}
+    }
+
+  if (!sign_val)
+    sign_val = 1;
+
+  return val * sign_val;
+}
+
+static char
+check_for_parse (const char *line)
+{
+  int val;
+
+  if (*(line + 1) == '[')
+    {
+      do
+	{
+	  line++;
+	  if ((*line == '-') || (*line == '+'))
+	    break;
+	}
+      while (!is_space_char (*line));
+
+      if ((*line == '-') || (*line == '+'))
+	val = extract_int_val (line);
+      else
+	val = extract_int_val (line + 1);
+
+      INSERT_BUFFER[0] = 0x3E;
+      INSERT_BUFFER[1] = val;
+
+      return 1;
+    }
+
+  return 0;
+}
+
+static mem_access *
+maxq20_mem_access (char *mem_string, char **end_op)
+{
+  char *s = mem_string;
+  char *p;
+  char mem_name_given[MAX_MEM_NAME_SIZE + 1];
+  mem_access *m;
+
+  m = NULL;
+
+  /* Skip possible whitespace.  */
+  if (is_space_char (*s))
+    ++s;
+
+  p = mem_name_given;
+  while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
+    {
+      if (p >= mem_name_given + MAX_MEM_NAME_SIZE)
+	return (mem_access *) NULL;
+      s++;
+    }
+
+  *end_op = s;
+
+  m = (mem_access *) hash_find (mem_hash, mem_name_given);
+
+  return m;
+}
+
+/* This function checks whether the operand is a variable in the data segment 
+   and if so, it returns its symbol entry from the symbol table.  */
+
+static symbolS *
+maxq20_data (char *op_string)
+{
+  symbolS *symbolP;
+  symbolP = symbol_find (op_string);
+
+  if (symbolP != NULL
+      && S_GET_SEGMENT (symbolP) != now_seg
+      && S_GET_SEGMENT (symbolP) !=
+#ifdef BFD_ASSEMBLER
+      bfd_und_section_ptr
+#else
+      SEG_UNKNOWN
+#endif
+      )
+    {
+      int val_pfx;
+
+#ifdef BFD_ASSEMBLER
+      val_pfx =	0;
+#else
+      val_pfx = (symbolP->sy_value.X_add_number) >> 8;
+#endif
+
+      /* In case we do not want to always include the prefix instruction and
+         let the loader handle the job or in case of a 8 bit addressing mode, 
+         we will just check for val_pfx to be equal to zero and then load the 
+         prefix instruction. Otherwise no prefix instruction needs to be
+         loaded.  */
+      /* The prefix register will have to be loaded automatically as we have 
+	 a 16 bit addressing field.  */
+      pfx_for_imm_val (val_pfx);
+      return symbolP;
+    }
+
+  return NULL;
+}
+
+static int
+maxq20_displacement (char *disp_start, char *disp_end)
+{
+  expressionS *exp;
+  segT exp_seg = 0;
+  char *save_input_line_pointer;
+#ifndef LEX_AT
+  char *gotfree_input_line;
+#endif
+
+  gotfree_input_line = NULL;
+  exp = &disp_expressions;
+  i.maxq20_op[this_operand].disps = exp;
+  i.disp_operands++;
+  save_input_line_pointer = input_line_pointer;
+  input_line_pointer = disp_start;
+
+  END_STRING_AND_SAVE (disp_end);
+
+#ifndef LEX_AT
+  /* gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); if
+     (gotfree_input_line) input_line_pointer = gotfree_input_line; */
+#endif
+  exp_seg = expression (exp);
+
+  SKIP_WHITESPACE ();
+  if (*input_line_pointer)
+    as_bad (_("junk `%s' after expression"), input_line_pointer);
+#if GCC_ASM_O_HACK
+  RESTORE_END_STRING (disp_end + 1);
+#endif
+  RESTORE_END_STRING (disp_end);
+  input_line_pointer = save_input_line_pointer;
+#ifndef LEX_AT
+  if (gotfree_input_line)
+    free (gotfree_input_line);
+#endif
+  if (exp->X_op == O_absent || exp->X_op == O_big)
+    {
+      /* Missing or bad expr becomes absolute 0.  */
+      as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
+	      disp_start);
+      exp->X_op = O_constant;
+      exp->X_add_number = 0;
+      exp->X_add_symbol = (symbolS *) 0;
+      exp->X_op_symbol = (symbolS *) 0;
+    }
+#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
+
+  if (exp->X_op != O_constant
+#ifdef BFD_ASSEMBLER
+      && OUTPUT_FLAVOR == bfd_target_aout_flavour
+#endif
+      && exp_seg != absolute_section
+      && exp_seg != text_section
+      && exp_seg != data_section
+      && exp_seg != bss_section && exp_seg != undefined_section
+#ifdef BFD_ASSEMBLER
+      && !bfd_is_com_section (exp_seg)
+#endif
+    )
+    {
+#ifdef BFD_ASSEMBLER
+      as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
+#else
+      as_bad (_("unimplemented segment type %d in operand"), exp_seg);
+#endif
+      return 0;
+    }
+#endif
+  i.maxq20_op[this_operand].disps = exp;
+  return 1;
+}
+
+/* Parse OPERAND_STRING into the maxq20_insn structure I.
+   Returns non-zero on error.  */
+
+static int
+maxq20_operand (char *operand_string)
+{
+  reg_entry *r = NULL;
+  reg_bit *rb = NULL;
+  mem_access *m = NULL;
+  char *end_op = NULL;
+  symbolS *sym = NULL;
+  char *base_string = NULL;
+  int ii = 0;
+  /* Start and end of displacement string expression (if found).  */
+  char *displacement_string_start = NULL;
+  char *displacement_string_end = NULL;
+  /* This maintains the  case sentivness.  */
+  char case_str_op_string[MAX_OPERAND_SIZE + 1];
+  char str_op_string[MAX_OPERAND_SIZE + 1];
+  char *org_case_op_string = case_str_op_string;
+  char *op_string = str_op_string;
+
+  
+  memset (op_string, END_OF_INSN, (MAX_OPERAND_SIZE + 1));
+  memset (org_case_op_string, END_OF_INSN, (MAX_OPERAND_SIZE + 1));
+
+  memcpy (op_string, operand_string, strlen (operand_string) + 1);
+  memcpy (org_case_op_string, operand_string, strlen (operand_string) + 1);
+
+  ii = strlen (operand_string) + 1;
+
+  if (ii > MAX_OPERAND_SIZE)
+    {
+      as_bad (_("Size of Operand '%s' greater than %d"), op_string,
+	      MAX_OPERAND_SIZE);
+      return 0;
+    }
+
+  while (ii)
+    {
+      op_string[ii - 1] = toupper ((char) op_string[ii - 1]);
+      ii--;
+    }
+
+  if (is_space_char (*op_string))
+    ++op_string;
+
+  if (isxdigit (operand_string[0]))
+    {
+      /* Now the operands can start with an Integer.  */
+      r = parse_reg_by_index (op_string);
+      if (r != NULL)
+	{
+	  if (is_space_char (*op_string))
+	    ++op_string;
+	  i.types[this_operand] = REG;	/* Set the type.  */
+	  i.maxq20_op[this_operand].reg = r;	/* Set the Register value.  */
+	  i.reg_operands++;
+	  return 1;
+	}
+
+      /* Get the origanal string.  */
+      memcpy (op_string, operand_string, strlen (operand_string) + 1);
+      ii = strlen (operand_string) + 1;
+
+      while (ii)
+	{
+	  op_string[ii - 1] = toupper ((char) op_string[ii - 1]);
+	  ii--;
+	}
+    }
+
+  /* Check for flags.  */
+  if (!strcmp (op_string, "Z"))
+    {
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = FLAG;		/* Set the type.  */
+      i.maxq20_op[this_operand].flag = FLAG_Z;	/* Set the Register value.  */
+
+      i.flag_operands++;
+
+      return 1;
+    }
+
+  else if (!strcmp (op_string, "NZ"))
+    {
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = FLAG;		/* Set the type.  */
+      i.maxq20_op[this_operand].flag = FLAG_NZ;	/* Set the Register value.  */
+      i.flag_operands++;
+      return 1;
+    }
+
+  else if (!strcmp (op_string, "NC"))
+    {
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = FLAG;		/* Set the type.  */
+      i.maxq20_op[this_operand].flag = FLAG_NC;	/* Set the Register value.  */
+      i.flag_operands++;
+      return 1;
+    }
+
+  else if (!strcmp (op_string, "E"))
+    {
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = FLAG;		/* Set the type.  */
+      i.maxq20_op[this_operand].flag = FLAG_E;	/* Set the Register value.  */
+
+      i.flag_operands++;
+
+      return 1;
+    }
+
+  else if (!strcmp (op_string, "S"))
+    {
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = FLAG;	/* Set the type.  */
+      i.maxq20_op[this_operand].flag = FLAG_S;	/* Set the Register value.  */
+
+      i.flag_operands++;
+
+      return 1;
+    }
+
+  else if (!strcmp (op_string, "C"))
+    {
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = FLAG;	/* Set the type.  */
+      i.maxq20_op[this_operand].flag = FLAG_C;	/* Set the Register value.  */
+
+      i.flag_operands++;
+
+      return 1;
+    }
+
+  else if (!strcmp (op_string, "NE"))
+    {
+
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = FLAG;	/* Set the type.  */
+
+      i.maxq20_op[this_operand].flag = FLAG_NE;	/* Set the Register value.  */
+
+      i.flag_operands++;
+
+      return 1;
+    }
+
+  /* CHECK FOR REGISTER BIT */
+  else if ((rb = parse_register_bit (op_string, &end_op)) != NULL)
+    {
+      op_string = end_op;
+
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = BIT;
+
+      i.maxq20_op[this_operand].r_bit = rb;
+
+      i.bit_operands++;
+
+      return 1;
+    }
+
+  else if (*op_string == IMMEDIATE_PREFIX)	/* FOR IMMEDITE.  */
+    {
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = IMM;
+
+      if (!maxq20_immediate (op_string))
+	{
+	  as_bad (_("illegal immediate operand '%s'"), op_string);
+	  return 0;
+	}
+      return 1;
+    }
+
+  else if (*op_string == ABSOLUTE_PREFIX || !strcmp (op_string, "NUL"))
+    {
+     if (is_space_char (*op_string))
+	++op_string;
+
+      /* For new requiremnt of copiler of for, @(BP,cons).  */
+      if (check_for_parse (op_string))
+	{
+	  memset (op_string, '\0', strlen (op_string) + 1);
+	  memcpy (op_string, "@BP[OFFS]\0", 11);
+	}
+
+      i.types[this_operand] = MEM;
+
+      if ((m = maxq20_mem_access (op_string, &end_op)) == NULL)
+	{
+	  as_bad (_("Invalid operand for memory access '%s'"), op_string);
+	  return 0;
+	}
+      i.maxq20_op[this_operand].mem = m;
+
+      i.mem_operands++;
+
+      return 1;
+    }
+
+  else if ((r = parse_register (op_string, &end_op)) != NULL)	/* Check for register.  */
+    {
+      op_string = end_op;
+
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = REG;	/* Set the type.  */
+      i.maxq20_op[this_operand].reg = r;	/* Set the Register value.  */
+      i.reg_operands++;
+      return 1;
+    }
+
+  if (this_operand == 1)
+    {
+      /* Changed for orginal case of data refrence on 30 Nov 2003.  */
+      /* The operand can either be a data reference or a symbol reference.  */
+      if ((sym = maxq20_data (org_case_op_string)) != NULL)	/* Check for data memory.  */
+	{
+	  while (is_space_char (*op_string))
+	    ++op_string;
+
+	  /* Set the type of the operand.  */
+	  i.types[this_operand] = DATA;
+
+	  /* Set the value of the data.  */
+	  i.maxq20_op[this_operand].data = sym;
+	  i.data_operands++;
+
+	  return 1;
+	}
+
+      else if (is_digit_char (*op_string) || is_identifier_char (*op_string))
+	{
+	  /* This is a memory reference of some sort. char *base_string;
+	     Start and end of displacement string expression (if found). char 
+	     *displacement_string_start; char *displacement_string_end.  */
+	  base_string = org_case_op_string + strlen (org_case_op_string);
+
+	  --base_string;
+	  if (is_space_char (*base_string))
+	    --base_string;
+
+	  /* If we only have a displacement, set-up for it to be parsed
+	     later.  */
+	  displacement_string_start = org_case_op_string;
+	  displacement_string_end = base_string + 1;
+	  if (displacement_string_start != displacement_string_end)
+	    {
+	      if (!maxq20_displacement (displacement_string_start,
+					displacement_string_end))
+		{
+		  as_bad (_("illegal displacement operand "));
+		  return 0;
+		}
+	      /* A displacement operand found.  */
+	      i.types[this_operand] = DISP;	/* Set the type.  */
+	      return 1;
+	    }
+	}
+    }
+  
+  /* Check for displacement.  */
+  else if (is_digit_char (*op_string) || is_identifier_char (*op_string))
+    {
+      /* This is a memory reference of some sort. char *base_string;
+         Start and end of displacement string expression (if found). char
+         *displacement_string_start; char *displacement_string_end;  */
+      base_string = org_case_op_string + strlen (org_case_op_string);
+
+      --base_string;
+      if (is_space_char (*base_string))
+	--base_string;
+
+      /* If we only have a displacement, set-up for it to be parsed later.  */
+      displacement_string_start = org_case_op_string;
+      displacement_string_end = base_string + 1;
+      if (displacement_string_start != displacement_string_end)
+	{
+	  if (!maxq20_displacement (displacement_string_start,
+				    displacement_string_end))
+	    return 0;
+	  /* A displacement operand found.  */
+	  i.types[this_operand] = DISP;	/* Set the type.  */
+	}
+    }
+  return 1;
+}
+
+/* Parse_operand takes as input instruction and operands and Parse operands
+   and makes entry in the template.  */
+
+static char *
+parse_operands (char *l, const char *mnemonic)
+{
+  char *token_start;
+
+  /* 1 if operand is pending after ','.  */
+  short int expecting_operand = 0;
+
+  /* Non-zero if operand parens not balanced.  */
+  short int paren_not_balanced;
+
+  int operand_ok;
+
+  /* For Overcoming Warning of unused variable.  */
+  if (mnemonic)
+    operand_ok = 0;
+
+  while (*l != END_OF_INSN)
+    {
+      /* Skip optional white space before operand.  */
+      if (is_space_char (*l))
+	++l;
+
+      if (!is_operand_char (*l) && *l != END_OF_INSN)
+	{
+	  as_bad (_("invalid character %c before operand %d"),
+		  (char) (*l), i.operands + 1);
+	  return NULL;
+	}
+      token_start = l;
+
+      paren_not_balanced = 0;
+      while (paren_not_balanced || *l != ',')
+	{
+	  if (*l == END_OF_INSN)
+	    {
+	      if (paren_not_balanced)
+		{
+		  as_bad (_("unbalanced brackets in operand %d."),
+			  i.operands + 1);
+		  return NULL;
+		}
+
+	      break;
+	    }
+	  else if (!is_operand_char (*l) && !is_space_char (*l))
+	    {
+	      as_bad (_("invalid character %c in operand %d"),
+		      (char) (*l), i.operands + 1);
+	      return NULL;
+	    }
+	  if (*l == '[')
+	    ++paren_not_balanced;
+	  if (*l == ']')
+	    --paren_not_balanced;
+	  l++;
+	}
+
+      if (l != token_start)
+	{
+	  /* Yes, we've read in another operand.  */
+	  this_operand = i.operands++;
+	  if (i.operands > MAX_OPERANDS)
+	    {
+	      as_bad (_("spurious operands; (%d operands/instruction max)"),
+		      MAX_OPERANDS);
+	      return NULL;
+	    }
+
+	  /* Now parse operand adding info to 'i' as we go along.  */
+	  END_STRING_AND_SAVE (l);
+
+	  operand_ok = maxq20_operand (token_start);
+
+	  RESTORE_END_STRING (l);
+
+	  if (!operand_ok)
+	    return NULL;
+	}
+      else
+	{
+	  if (expecting_operand)
+	    {
+	    expecting_operand_after_comma:
+	      as_bad (_("expecting operand after ','; got nothing"));
+	      return NULL;
+	    }
+	}
+
+      if (*l == ',')
+	{
+	  if (*(++l) == END_OF_INSN)
+	    /* Just skip it, if it's \n complain.  */
+	    goto expecting_operand_after_comma;
+
+	  expecting_operand = 1;
+	}
+    }
+
+  return l;
+}
+
+static int
+match_operands (int type, MAX_ARG_TYPE flag_type, MAX_ARG_TYPE arg_type,
+		int op_num)
+{
+  switch (type)
+    {
+    case REG:
+      if ((arg_type & A_REG) == A_REG)
+	return 1;
+      break;
+    case IMM:
+      if ((arg_type & A_IMM) == A_IMM)
+	return 1;
+      break;
+    case IMMBIT:
+      if ((arg_type & A_BIT_0) == A_BIT_0 && (i.maxq20_op[op_num].imms == 0))
+	return 1;
+      else if ((arg_type & A_BIT_1) == A_BIT_1
+	       && (i.maxq20_op[op_num].imms == 1))
+	return 1;
+      break;
+    case MEM:
+      if ((arg_type & A_MEM) == A_MEM)
+	return 1;
+      break;
+
+    case FLAG:
+      if ((arg_type & flag_type) == flag_type)
+	return 1;
+
+      break;
+
+    case BIT:
+      if ((arg_type & ACC_BIT) == ACC_BIT && !strcmp (i.maxq20_op[op_num].r_bit->reg->reg_name, "ACC"))
+	return 1;
+      else if ((arg_type & SRC_BIT) == SRC_BIT && (op_num == 1))
+	return 1;
+      else if ((op_num == 0) && (arg_type & DST_BIT) == DST_BIT)
+	return 1;
+      break;
+    case DISP:
+      if ((arg_type & A_DISP) == A_DISP)
+	return 1;
+    case DATA:
+      if ((arg_type & A_DATA) == A_DATA)
+	return 1;
+    case BIT_BUCKET:
+      if ((arg_type & A_BIT_BUCKET) == A_BIT_BUCKET)
+	return 1;
+    }
+  return 0;
+}
+
+static int
+match_template (void)
+{
+  /* Points to template once we've found it.  */
+  const MAXQ20_OPCODE_INFO *t;
+  char inv_oper;
+  inv_oper = 0;
+
+  for (t = current_templates->start; t < current_templates->end; t++)
+    {
+      /* Must have right number of operands.  */
+      if (i.operands != t->op_number)
+	continue;
+      else if (!t->op_number)
+	break;
+
+      switch (i.operands)
+	{
+	case 2:
+	  if (!match_operands (i.types[1], i.maxq20_op[1].flag, t->arg[1], 1))
+	    {
+	      inv_oper = 1;
+	      continue;
+	    }
+	case 1:
+	  if (!match_operands (i.types[0], i.maxq20_op[0].flag, t->arg[0], 0))
+	    {
+	      inv_oper = 2;
+	      continue;
+	    }
+	}
+      break;
+    }
+
+  if (t == current_templates->end)
+    {
+      /* We found no match.  */
+      as_bad (_("operand %d is invalid for `%s'"),
+	      inv_oper, current_templates->start->name);
+      return 0;
+    }
+
+  /* Copy the template we have found.  */
+  i.op = *t;
+  return 1;
+}
+
+/* This function filters out the various combinations of operands which are
+   not allowed for a particular instruction.  */
+
+static int
+match_filters (void)
+{
+  /* Now we have at our disposal the instruction i. We will be using the
+     following fields i.op.name : This is the mnemonic name. i.types[2] :
+     These are the types of the operands (REG/IMM/DISP/MEM/BIT/FLAG/IMMBIT)
+     i.maxq20_op[2] : This contains the specific info of the operands.  */
+
+  /* Our first filter : NO ALU OPERATIONS CAN HAVE THE ACTIVE ACCUMULATOR AS
+     SOURCE.  */
+  if (!strcmp (i.op.name, "AND") || !strcmp (i.op.name, "OR")
+      || !strcmp (i.op.name, "XOR") || !strcmp (i.op.name, "ADD")
+      || !strcmp (i.op.name, "ADDC") || !strcmp (i.op.name, "SUB")
+      || !strcmp (i.op.name, "SUBB"))
+    {
+      if (i.types[0] == REG)
+	{
+	  if (i.maxq20_op[0].reg->Mod_name == 0xa)
+	    {
+	      as_bad (_
+		      ("The Accumulator cannot be used as a source in ALU instructions\n"));
+	      return 0;
+	    }
+	}
+    }
+
+  if (!strcmp (i.op.name, "MOVE") && (i.types[0] == MEM || i.types[1] == MEM)
+      && i.operands == 2)
+    {
+      mem_access_syntax *mem_op = NULL;
+
+      if (i.types[0] == MEM)
+	{
+	  mem_op =
+	    (mem_access_syntax *) hash_find (mem_syntax_hash,
+					     i.maxq20_op[0].mem->name);
+	  if ((mem_op->type == SRC) && mem_op)
+	    {
+	      as_bad (_("'%s' operand cant be used as destination in %s"),
+		      mem_op->name, i.op.name);
+	      return 0;
+	    }
+	  else if ((mem_op->invalid_op != NULL) && (i.types[1] == MEM)
+		   && mem_op)
+	    {
+	      int k = 0;
+
+	      for (k = 0; k < 5 || !mem_op->invalid_op[k]; k++)
+		{
+		  if (mem_op->invalid_op[k] != NULL)
+		    if (!strcmp
+			(mem_op->invalid_op[k], i.maxq20_op[1].mem->name))
+		      {
+			as_bad (_
+				("Invalid Instruction '%s' operand cant be used with %s"),
+				mem_op->name, i.maxq20_op[1].mem->name);
+			return 0;
+		      }
+		}
+	    }
+	}
+
+      if (i.types[1] == MEM)
+	{
+	  mem_op = NULL;
+	  mem_op =
+	    (mem_access_syntax *) hash_find (mem_syntax_hash,
+					     i.maxq20_op[1].mem->name);
+	  if (mem_op->type == DST && mem_op)
+	    {
+	      as_bad (_("'%s' operand cant be used as source in %s"),
+		      mem_op->name, i.op.name);
+	      return 0;
+	    }
+	  else if (mem_op->invalid_op != NULL && i.types[0] == MEM && mem_op)
+	    {
+	      int k = 0;
+
+	      for (k = 0; k < 5 || !mem_op->invalid_op[k]; k++)
+		{
+		  if (mem_op->invalid_op[k] != NULL)
+		    if (!strcmp
+			(mem_op->invalid_op[k], i.maxq20_op[0].mem->name))
+		      {
+			as_bad (_
+				("Invalid Instruction '%s' operand cant be used with %s"),
+				mem_op->name, i.maxq20_op[0].mem->name);
+			return 0;
+		      }
+		}
+	    }
+	  else if (i.types[0] == REG
+		   && !strcmp (i.maxq20_op[0].reg->reg_name, "OFFS")
+		   && mem_op)
+	    {
+	      if (!strcmp (mem_op->name, "@BP[OFFS--]")
+		  || !strcmp (mem_op->name, "@BP[OFFS++]"))
+		{
+		  as_bad (_
+			  ("Invalid Instruction '%s' operand cant be used with %s"),
+			  mem_op->name, i.maxq20_op[0].mem->name);
+		  return 0;
+		}
+	    }
+	}
+    }
+
+  /* Added for SRC and DST in one operand instructioni i.e OR @--DP[1] added
+     on 10-March-2004.  */
+  if ((i.types[0] == MEM) && (i.operands == 1)
+      && !(!strcmp (i.op.name, "POP") || !strcmp (i.op.name, "POPI")))
+    {
+      mem_access_syntax *mem_op = NULL;
+
+      if (i.types[0] == MEM)
+	{
+	  mem_op =
+	    (mem_access_syntax *) hash_find (mem_syntax_hash,
+					     i.maxq20_op[0].mem->name);
+	  if (mem_op->type == DST && mem_op)
+	    {
+	      as_bad (_("'%s' operand cant be used as source in %s"),
+		      mem_op->name, i.op.name);
+	      return 0;
+	    }
+	}
+    }
+
+  if (i.operands == 2 && i.types[0] == IMM)
+    {
+      as_bad (_("'%s' instruction cant have first operand as Immediate vale"),
+	      i.op.name);
+      return 0;
+    }
+
+  /* Our second filter : SP or @SP-- cannot be used with PUSH or POP */
+  if (!strcmp (i.op.name, "PUSH") || !strcmp (i.op.name, "POP")
+      || !strcmp (i.op.name, "POPI"))
+    {
+      if (i.types[0] == REG)
+	{
+	  if (!strcmp (i.maxq20_op[0].reg->reg_name, "SP"))
+	    {
+	      as_bad (_("SP cannot be used with %s\n"), i.op.name);
+	      return 0;
+	    }
+	}
+      else if (i.types[0] == MEM
+	       && !strcmp (i.maxq20_op[0].mem->name, "@SP--"))
+	{
+	  as_bad (_("@SP-- cannot be used with PUSH\n"));
+	  return 0;
+	}
+    }
+
+  /* This filter checks that two memory references using DP's cannot be used
+     together in an instruction */
+  if (!strcmp (i.op.name, "MOVE") && i.mem_operands == 2)
+    {
+      if (strlen (i.maxq20_op[0].mem->name) != 6 ||
+	  strcmp (i.maxq20_op[0].mem->name, i.maxq20_op[1].mem->name))
+	{
+	  if (!strncmp (i.maxq20_op[0].mem->name, "@DP", 3)
+	      && !strncmp (i.maxq20_op[1].mem->name, "@DP", 3))
+	    {
+	      as_bad (_
+		      ("Operands either contradictory or use the data bus in read/write state together"));
+	      return 0;
+	    }
+
+	  if (!strncmp (i.maxq20_op[0].mem->name, "@SP", 3)
+	      && !strncmp (i.maxq20_op[1].mem->name, "@SP", 3))
+	    {
+	      as_bad (_
+		      ("Operands either contradictory or use the data bus in read/write state together"));
+	      return 0;
+	    }
+	}
+      if ((i.maxq20_op[1].mem != NULL)
+	  && !strncmp (i.maxq20_op[1].mem->name, "NUL", 3))
+	{
+	  as_bad (_("MOVE Cant Use NUL as SRC"));
+	  return 0;
+	}
+    }
+
+  /* This filter checks that contradictory movement between DP register and
+     Memory access using DP followed by increment or decrement.  */
+
+  if (!strcmp (i.op.name, "MOVE") && i.mem_operands == 1
+      && i.reg_operands == 1)
+    {
+      int memnum, regnum;
+
+      memnum = (i.types[0] == MEM) ? 0 : 1;
+      regnum = (memnum == 0) ? 1 : 0;
+      if (!strncmp (i.maxq20_op[regnum].reg->reg_name, "DP", 2) &&
+	  !strncmp ((i.maxq20_op[memnum].mem->name) + 1,
+		    i.maxq20_op[regnum].reg->reg_name, 5)
+	  && strcmp ((i.maxq20_op[memnum].mem->name) + 1,
+		     i.maxq20_op[regnum].reg->reg_name))
+	{
+	  as_bad (_
+		  ("Contradictory movement between DP register and memory access using DP"));
+	  return 0;
+	}
+      else if (!strcmp (i.maxq20_op[regnum].reg->reg_name, "SP") &&
+	       !strncmp ((i.maxq20_op[memnum].mem->name) + 1,
+			 i.maxq20_op[regnum].reg->reg_name, 2))
+	{
+	  as_bad (_
+		  ("SP and @SP-- cannot be used together in a move instruction"));
+	  return 0;
+	}
+    }
+
+  /* This filter restricts the instructions containing source and destination 
+     bits to only CTRL module of the serial registers. Peripheral registers
+     yet to be defined.  */
+
+  if (i.bit_operands == 1 && i.operands == 2)
+    {
+      int bitnum = (i.types[0] == BIT) ? 0 : 1;
+
+      if (strcmp (i.maxq20_op[bitnum].r_bit->reg->reg_name, "ACC"))
+	{
+	  if (i.maxq20_op[bitnum].r_bit->reg->Mod_name >= 0x7 &&
+	      i.maxq20_op[bitnum].r_bit->reg->Mod_name != CTRL)
+	    {
+	      as_bad (_
+		      ("Only Module 8 system registers allowed in this operation"));
+	      return 0;
+	    }
+	}
+    }
+
+  /* This filter is for checking the register bits.  */
+  if (i.bit_operands == 1 || i.operands == 2)
+    {
+      int bitnum = 0, size = 0;
+
+      bitnum = (i.types[0] == BIT) ? 0 : 1;
+      if (i.bit_operands == 1)
+	{
+	  switch (i.maxq20_op[bitnum].r_bit->reg->rtype)
+	    {
+	    case Reg_8W:
+	      size = 7;		/* 8 bit register, both read and write.  */
+	      break;
+	    case Reg_16W:
+	      size = 15;
+	      break;
+	    case Reg_8R:
+	      size = 7;
+	      if (bitnum == 0)
+		{
+		  as_fatal (_("Read only Register used as destination"));
+		  return 0;
+		}
+	      break;
+
+	    case Reg_16R:
+	      size = 15;
+	      if (bitnum == 0)
+		{
+		  as_fatal (_("Read only Register used as destination"));
+		  return 0;
+		}
+	      break;
+	    }
+
+	  if (size < (i.maxq20_op[bitnum].r_bit)->bit)
+	    {
+	      as_bad (_("Bit No '%d'exceeds register size in this operation"),
+		      (i.maxq20_op[bitnum].r_bit)->bit);
+	      return 0;
+	    }
+	}
+
+      if (i.bit_operands == 2)
+	{
+	  switch ((i.maxq20_op[0].r_bit)->reg->rtype)
+	    {
+	    case Reg_8W:
+	      size = 7;		/* 8 bit register, both read and write.  */
+	      break;
+	    case Reg_16W:
+	      size = 15;
+	      break;
+	    case Reg_8R:
+	    case Reg_16R:
+	      as_fatal (_("Read only Register used as destination"));
+	      return 0;
+	    }
+
+	  if (size < (i.maxq20_op[0].r_bit)->bit)
+	    {
+	      as_bad (_
+		      ("Bit No '%d' exceeds register size in this operation"),
+		      (i.maxq20_op[0].r_bit)->bit);
+	      return 0;
+	    }
+
+	  size = 0;
+	  switch ((i.maxq20_op[1].r_bit)->reg->rtype)
+	    {
+	    case Reg_8R:
+	    case Reg_8W:
+	      size = 7;		/* 8 bit register, both read and write.  */
+	      break;
+	    case Reg_16R:
+	    case Reg_16W:
+	      size = 15;
+	      break;
+	    }
+
+	  if (size < (i.maxq20_op[1].r_bit)->bit)
+	    {
+	      as_bad (_
+		      ("Bit No '%d' exceeds register size in this operation"),
+		      (i.maxq20_op[1].r_bit)->bit);
+	      return 0;
+	    }
+	}
+    }
+
+  /* No branch operations should occur into the data memory. Hence any memory 
+     references have to be filtered out when used with instructions like
+     jump, djnz[] and call.  */
+
+  if (!strcmp (i.op.name, "JUMP") || !strcmp (i.op.name, "CALL")
+      || !strncmp (i.op.name, "DJNZ", 4))
+    {
+      if (i.mem_operands)
+	as_warn (_
+		 ("Memory References cannot be used with branching operations\n"));
+    }
+
+  if (!strcmp (i.op.name, "DJNZ"))
+    {
+      if (!
+	  (strcmp (i.maxq20_op[0].reg->reg_name, "LC[0]")
+	   || strcmp (i.maxq20_op[0].reg->reg_name, "LC[1]")))
+	{
+	  as_bad (_("DJNZ uses only LC[n] register \n"));
+	  return 0;
+	}
+    }
+
+  /* No destination register used should be read only!  */
+  if ((i.operands == 2 && i.types[0] == REG) || !strcmp (i.op.name, "POP")
+      || !strcmp (i.op.name, "POPI"))
+    {				/* The destination is a register */
+      int regnum = 0;
+
+      if (!strcmp (i.op.name, "POP") || !strcmp (i.op.name, "POPI"))
+	{
+	  regnum = 0;
+
+	  if (i.types[regnum] == MEM)
+	    {
+	      mem_access_syntax *mem_op = NULL;
+
+	      mem_op =
+		(mem_access_syntax *) hash_find (mem_syntax_hash,
+						 i.maxq20_op[regnum].mem->
+						 name);
+	      if (mem_op->type == SRC && mem_op)
+		{
+		  as_bad (_
+			  ("'%s' operand cant be used as destination  in %s"),
+			  mem_op->name, i.op.name);
+		  return 0;
+		}
+	    }
+	}
+
+      if (i.maxq20_op[regnum].reg->rtype == Reg_8R
+	  || i.maxq20_op[regnum].reg->rtype == Reg_16R)
+	{
+	  as_bad (_("Read only register used for writing purposes '%s'"),
+		  i.maxq20_op[regnum].reg->reg_name);
+	  return 0;
+	}
+    }
+
+  /* While moving the address of a data in the data section, the destination
+     should be either data pointers only.  */
+  if ((i.data_operands) && (i.operands == 2))
+    {
+      if ((i.types[0] != REG) && (i.types[0] != MEM))
+	{
+	  as_bad (_("Invalid destination for this kind of source."));
+	  return 0;
+	}
+
+	if (i.types[0] == REG && i.maxq20_op[0].reg->rtype == Reg_8W)
+	  {
+	    as_bad (_
+		    ("Invalid register as destination for this kind of source.Only data pointers can be used."));
+	    return 0;
+	  }
+    }
+  return 1;
+}
+
+static int
+decode_insn (void)
+{
+  /* Check for the format Bit if defined.  */
+  if (i.op.format == 0 || i.op.format == 1)
+    i.instr[0] = i.op.format << 7;
+  else
+    {
+      /* Format bit not defined. We will have to be find it out ourselves.  */
+      if (i.imm_operands == 1 || i.data_operands == 1 || i.disp_operands == 1)
+	i.op.format = 0;
+      else
+	i.op.format = 1;
+      i.instr[0] = i.op.format << 7;
+    }
+
+  /* Now for the destination register.  */
+
+  /* If destination register is already defined . The conditions are the
+     following: (1) The second entry in the destination array should be 0 (2) 
+     If there are two operands then the first entry should not be a register,
+     memory or a register bit (3) If there are less than two operands and the
+     it is not a pop operation (4) The second argument is the carry
+     flag(applicable to move Acc.<b>,C.  */
+  if (i.op.dst[1] == 0
+      &&
+      ((i.types[0] != REG && i.types[0] != MEM && i.types[0] != BIT
+	&& i.operands == 2) || (i.operands < 2 && strcmp (i.op.name, "POP")
+				&& strcmp (i.op.name, "POPI"))
+       || (i.op.arg[1] == FLAG_C)))
+    {
+      i.op.dst[0] &= 0x7f;
+      i.instr[0] |= i.op.dst[0];
+    }
+  else if (i.op.dst[1] == 0 && !strcmp (i.op.name, "DJNZ")
+	   &&
+	   (((i.types[0] == REG)
+	     && (!strcmp (i.maxq20_op[0].reg->reg_name, "LC[0]")
+		 || !strcmp (i.maxq20_op[0].reg->reg_name, "LC[1]")))))
+    {
+      i.op.dst[0] &= 0x7f;
+      if (!strcmp (i.maxq20_op[0].reg->reg_name, "LC[0]"))
+	i.instr[0] |= 0x4D;
+
+      if (!strcmp (i.maxq20_op[0].reg->reg_name, "LC[1]"))
+	i.instr[0] |= 0x5D;
+    }
+  else
+    {
+      unsigned char temp;
+
+      /* Target register will have to be specified.  */
+      if (i.types[0] == REG
+	  && (i.op.dst[0] == REG || i.op.dst[0] == (REG | MEM)))
+	{
+	  temp = (i.maxq20_op[0].reg)->opcode;
+	  temp &= 0x7f;
+	  i.instr[0] |= temp;
+	}
+      else if (i.types[0] == MEM && (i.op.dst[0] == (REG | MEM)))
+	{
+	  temp = (i.maxq20_op[0].mem)->opcode;
+	  temp &= 0x7f;
+	  i.instr[0] |= temp;
+	}
+      else if (i.types[0] == BIT && (i.op.dst[0] == REG))
+	{
+	  temp = (i.maxq20_op[0].r_bit)->reg->opcode;
+	  temp &= 0x7f;
+	  i.instr[0] |= temp;
+	}
+      else if (i.types[1] == BIT && (i.op.dst[0] == BIT))
+	{
+	  temp = (i.maxq20_op[1].r_bit)->bit;
+	  temp = temp << 4;
+	  temp |= i.op.dst[1];
+	  temp &= 0x7f;
+	  i.instr[0] |= temp;
+	}
+      else
+	{
+	  as_bad (_("Invalid Instruction"));
+	  return 0;
+	}
+    }
+
+  /* Now for the source register.  */
+
+  /* If Source register is already known. The following conditions are
+     checked: (1) There are no operands (2) If there is only one operand and
+     it is a flag (3) If the operation is MOVE C,#0/#1 (4) If it is a POP
+     operation.  */
+
+  if (i.operands == 0 || (i.operands == 1 && i.types[0] == FLAG)
+      || (i.types[0] == FLAG && i.types[1] == IMMBIT)
+      || !strcmp (i.op.name, "POP") || !strcmp (i.op.name, "POPI"))
+    i.instr[1] = i.op.src[0];
+
+  else if (i.imm_operands == 1 && ((i.op.src[0] & IMM) == IMM))
+    i.instr[1] = i.maxq20_op[this_operand].imms;
+  
+  else if (i.types[this_operand] == REG && ((i.op.src[0] & REG) == REG))
+    i.instr[1] = (char) ((i.maxq20_op[this_operand].reg)->opcode);
+
+  else if (i.types[this_operand] == BIT && ((i.op.src[0] & REG) == REG))
+    i.instr[1] = (char) (i.maxq20_op[this_operand].r_bit->reg->opcode);
+
+  else if (i.types[this_operand] == MEM && ((i.op.src[0] & MEM) == MEM))
+    i.instr[1] = (char) ((i.maxq20_op[this_operand].mem)->opcode);
+
+  else if (i.types[this_operand] == DATA && ((i.op.src[0] & DATA) == DATA))
+    /* This will copy only the lower order bytes into the instruction. The
+       higher order bytes have already been copied into the prefix register.  */
+    i.instr[1] = 0;
+
+  /* Decoding the source in the case when the second array entry is not 0.
+     This means that the source register has been divided into two nibbles.  */
+
+  else if (i.op.src[1] != 0)
+    {
+      /* If the first operand is a accumulator bit then
+	 the first 4 bits will be filled with the bit number.  */
+      if (i.types[0] == BIT && ((i.op.src[0] & BIT) == BIT))
+	{
+	  unsigned char temp = (i.maxq20_op[0].r_bit)->bit;
+
+	  temp = temp << 4;
+	  temp |= i.op.src[1];
+	  i.instr[1] = temp;
+	}
+      /* In case of MOVE dst.<b>,#1 The first nibble in the source register
+         has to start with a zero. This is called a ZEROBIT */
+      else if (i.types[0] == BIT && ((i.op.src[0] & ZEROBIT) == ZEROBIT))
+	{
+	  char temp = (i.maxq20_op[0].r_bit)->bit;
+
+	  temp = temp << 4;
+	  temp |= i.op.src[1];
+	  temp &= 0x7f;
+	  i.instr[1] = temp;
+	}
+      /* Similarly for a ONEBIT */
+      else if (i.types[0] == BIT && ((i.op.src[0] & ONEBIT) == ONEBIT))
+	{
+	  char temp = (i.maxq20_op[0].r_bit)->bit;
+
+	  temp = temp << 4;
+	  temp |= i.op.src[1];
+	  temp |= 0x80;
+	  i.instr[1] = temp;
+	}
+      /* In case the second operand is a register bit (MOVE C,Acc.<b> or MOVE 
+         C,src.<b> */
+      else if (i.types[1] == BIT)
+	{
+	  if (i.op.src[1] == 0 && i.op.src[1] == REG)
+	    i.instr[1] = (i.maxq20_op[1].r_bit)->reg->opcode;
+
+	  else if (i.op.src[0] == BIT && i.op.src)
+	    {
+	      char temp = (i.maxq20_op[1].r_bit)->bit;
+
+	      temp = temp << 4;
+	      temp |= i.op.src[1];
+	      i.instr[1] = temp;
+	    }
+	}
+      else
+	{
+	  as_bad (_("Invalid Instruction"));
+	  return 0;
+	}
+    }
+  return 1;
+}
+
+/* This is a function for outputting displacement operands.  */
+
+static void
+output_disp (fragS *insn_start_frag, offsetT insn_start_off)
+{
+  char *p;
+  relax_substateT subtype;
+  symbolS *sym;
+  offsetT off;
+  int diff;
+
+  diff = 0;
+  insn_start_frag = frag_now;
+  insn_start_off = frag_now_fix ();
+
+  switch (i.Instr_Prefix)
+    {
+    case LONG_PREFIX:
+      subtype = EXPLICT_LONG_PREFIX;
+      break;
+    case SHORT_PREFIX:
+      subtype = SHORT_PREFIX;
+      break;
+    default:
+      subtype = NO_PREFIX;
+      break;
+    }
+
+  /* Its a symbol. Here we end the frag and start the relaxation. Now in our
+     case there is no need for relaxation. But we do need support for a
+     prefix operator. Hence we will check whethere is room for 4 bytes ( 2
+     for prefix + 2 for the current instruction ) Hence if at a particular
+     time we find out whether the prefix operator is reqd , we shift the
+     current instruction two places ahead and insert the prefix instruction.  */
+  frag_grow (2 + 2);
+  p = frag_more (2);
+
+  sym = i.maxq20_op[this_operand].disps->X_add_symbol;
+  off = i.maxq20_op[this_operand].disps->X_add_number;
+
+  if (i.maxq20_op[this_operand].disps->X_add_symbol != NULL && sym && frag_now
+      && (subtype != EXPLICT_LONG_PREFIX))
+    {
+      /* If in the same frag.  */
+      if (frag_now == symbol_get_frag (sym))
+	{
+	  diff =
+	    ((((expressionS *) symbol_get_value_expression (sym))->
+	      X_add_number) - insn_start_off);
+
+	  diff = diff / MAXQ_OCTETS_PER_BYTE;
+
+	  if (diff >= -128 && diff <= 127)
+	    {
+	      i.instr[1] = (char) diff;
+
+	      /* This will be overwritten later when the symbol is resolved.  */
+	      *p = i.instr[1];
+	      *(p + 1) = i.instr[0];
+
+	      /* No Need to create a FIXUP.  */
+	      return;
+	    }
+	}
+    }
+
+  /* This will be overwritten later when the symbol is resolved.  */
+  *p = i.instr[1];
+  *(p + 1) = i.instr[0];
+
+  if (i.maxq20_op[this_operand].disps->X_op != O_constant
+      && i.maxq20_op[this_operand].disps->X_op != O_symbol)
+    {
+      /* Handle complex expressions.  */
+      sym = make_expr_symbol (i.maxq20_op[this_operand].disps);
+      off = 0;
+    }
+
+  /* Vineet : This has been added for md_estimate_size_before_relax to
+     estimate the correct size.  */
+  if (subtype != SHORT_PREFIX)
+    i.reloc[this_operand] = LONG_PREFIX;
+
+  frag_var (rs_machine_dependent, 2, i.reloc[this_operand], subtype, sym, off,  p);
+}
+
+/* This is a function for outputting displacement operands.  */
+
+static void
+output_data (fragS *insn_start_frag, offsetT insn_start_off)
+{
+  char *p;
+  relax_substateT subtype;
+  symbolS *sym;
+  offsetT off;
+  int diff;
+
+  diff = 0;
+  off = 0;
+  insn_start_frag = frag_now;
+  insn_start_off = frag_now_fix ();
+
+  subtype = EXPLICT_LONG_PREFIX;
+
+  frag_grow (2 + 2);
+  p = frag_more (2);
+
+  sym = i.maxq20_op[this_operand].data;
+  off = 0;
+
+  /* This will be overwritten later when the symbol is resolved.  */
+  *p = i.instr[1];
+  *(p + 1) = i.instr[0];
+
+  if (i.maxq20_op[this_operand].disps->X_op != O_constant
+      && i.maxq20_op[this_operand].disps->X_op != O_symbol)
+    /* Handle complex expressions.  */
+    /* Because data is already in terms of symbol so no
+       need to convert it from expression to symbol.  */
+    off = 0;
+
+  frag_var (rs_machine_dependent, 2, i.reloc[this_operand], subtype, sym, off,  p);
+}
+
+static void
+output_insn (void)
+{
+  fragS *insn_start_frag;
+  offsetT insn_start_off;
+  char *p;
+
+  /* Tie dwarf2 debug info to the address at the start of the insn. We can't
+     do this after the insn has been output as the current frag may have been 
+     closed off.  eg. by frag_var.  */
+  dwarf2_emit_insn (0);
+
+  /* To ALign the text section on word.  */
+
+  frag_align (1, 0, 1);
+
+  /* We initialise the frags for this particular instruction.  */
+  insn_start_frag = frag_now;
+  insn_start_off = frag_now_fix ();
+
+  /* If there are displacement operators(unresolved) present, then handle
+     them separately.  */
+  if (i.disp_operands)
+    {
+      output_disp (insn_start_frag, insn_start_off);
+      return;
+    }
+
+  if (i.data_operands)
+    {
+      output_data (insn_start_frag, insn_start_off);
+      return;
+    }
+
+  /* Check whether the INSERT_BUFFER has to be written.  */
+  if (strcmp (INSERT_BUFFER, ""))
+    {
+      p = frag_more (2);
+
+      *p++ = INSERT_BUFFER[1];
+      *p = INSERT_BUFFER[0];
+    }
+
+  /* Check whether the prefix instruction has to be written.  */
+  if (strcmp (PFX_INSN, ""))
+    {
+      p = frag_more (2);
+
+      *p++ = PFX_INSN[1];
+      *p = PFX_INSN[0];
+    }
+
+  p = frag_more (2);
+  /* For Little endian.  */
+  *p++ = i.instr[1];
+  *p = i.instr[0];
+}
+
+static void
+make_new_reg_table (void)
+{
+  unsigned long size_pm = sizeof (peripheral_reg_table);
+  num_of_reg = ARRAY_SIZE (peripheral_reg_table);
+
+  new_reg_table = xmalloc (size_pm);
+  if (new_reg_table == NULL)
+    as_bad (_("Cannot allocate memory"));
+
+  memcpy (new_reg_table, peripheral_reg_table, size_pm);
+}
+
+/* pmmain performs the initilizations for the pheripheral modules. */
+
+static void
+pmmain (void)
+{
+  make_new_reg_table ();
+  return;
+}
+
+void
+md_begin (void)
+{
+  const char *hash_err = NULL;
+  int c = 0;
+  char *p;
+  const MAXQ20_OPCODE_INFO *optab;
+  MAXQ20_OPCODES *core_optab;	/* For opcodes of the same name. This will
+				   be inserted into the hash table.  */
+  struct reg *reg_tab;
+  struct mem_access_syntax const *memsyntab;
+  struct mem_access *memtab;
+  struct bit_name *bittab;
+
+  /* Initilize pherioipheral modules.  */
+  pmmain ();
+
+  /* Initialise the opcode hash table.  */
+  op_hash = hash_new ();
+
+  optab = op_table;		/* Initialise it to the first entry of the
+				   maxq20 operand table.  */
+
+  /* Setup for loop.  */
+  core_optab = xmalloc (sizeof (MAXQ20_OPCODES));
+  core_optab->start = optab;
+
+  while (1)
+    {
+      ++optab;
+      if (optab->name == NULL || strcmp (optab->name, (optab - 1)->name) != 0)
+	{
+	  /* different name --> ship out current template list; add to hash
+	     table; & begin anew.  */
+
+	  core_optab->end = optab;
+#ifdef MAXQ10S
+	  if (max_version == 10)
+	    {
+	      if (((optab - 1)->arch == MAXQ10) || ((optab - 1)->arch == MAX))
+		{
+		  hash_err = hash_insert (op_hash,
+					  (optab - 1)->name,
+					  (PTR) core_optab);
+		}
+	    }
+	  else if (max_version == 20)
+	    {
+	      /* MAXQ20 */
+	      if (((optab - 1)->arch == MAXQ20) || ((optab - 1)->arch == MAX))
+		{
+#endif
+		  hash_err = hash_insert (op_hash,
+					  (optab - 1)->name,
+					  (PTR) core_optab);
+#if MAXQ10S
+		}
+	    }
+	  else
+	    as_fatal (_("Internal Error: Illegal Architecure specified"));
+#endif
+	  if (hash_err)
+	    as_fatal (_("Internal Error:  Can't hash %s: %s"),
+		      (optab - 1)->name, hash_err);
+
+	  if (optab->name == NULL)
+	    break;
+	  core_optab = xmalloc (sizeof (MAXQ20_OPCODES));
+	  core_optab->start = optab;
+	}
+    }
+
+  /* Initialise a new register table.  */
+  reg_hash = hash_new ();
+
+  for (reg_tab = system_reg_table;
+       reg_tab < (system_reg_table + ARRAY_SIZE (system_reg_table));
+       reg_tab++)
+    {
+#if MAXQ10S
+      switch (max_version)
+	{
+	case 10:		/* MAXQ10 */
+	  if ((reg_tab->arch == MAXQ10) || (reg_tab->arch == MAX))
+	    hash_err = hash_insert (reg_hash, reg_tab->reg_name, (PTR) reg_tab);
+	  break;
+
+	case 20:		/* MAXQ20 */
+	  if ((reg_tab->arch == MAXQ20) || (reg_tab->arch == MAX))
+	    {
+#endif
+	      hash_err =
+		hash_insert (reg_hash, reg_tab->reg_name, (PTR) reg_tab);
+#if MAXQ10S
+	    }
+	  break;
+	default:
+	  as_fatal (_("Invalid architecture type"));
+	}
+#endif
+
+      if (hash_err)
+	as_fatal (_("Internal Error : Can't Hash %s : %s"),
+		  reg_tab->reg_name, hash_err);
+    }
+
+  /* Pheripheral Registers Entry.  */
+  for (reg_tab = new_reg_table;
+       reg_tab < (new_reg_table + num_of_reg - 1); reg_tab++)
+    {
+      hash_err = hash_insert (reg_hash, reg_tab->reg_name, (PTR) reg_tab);
+
+      if (hash_err)
+	as_fatal (_("Internal Error : Can't Hash %s : %s"),
+		  reg_tab->reg_name, hash_err);
+    }
+
+  /* Initialise a new memory operand table.  */
+  mem_hash = hash_new ();
+
+  for (memtab = mem_table;
+       memtab < mem_table + ARRAY_SIZE (mem_table);
+       memtab++)
+    {
+      hash_err = hash_insert (mem_hash, memtab->name, (PTR) memtab);
+      if (hash_err)
+	as_fatal (_("Internal Error : Can't Hash %s : %s"),
+		  memtab->name, hash_err);
+    }
+
+  bit_hash = hash_new ();
+
+  for (bittab = bit_table;
+       bittab < bit_table + ARRAY_SIZE (bit_table);
+       bittab++)
+    {
+      hash_err = hash_insert (bit_hash, bittab->name, (PTR) bittab);
+      if (hash_err)
+	as_fatal (_("Internal Error : Can't Hash %s : %s"),
+		  bittab->name, hash_err);
+    }
+
+  mem_syntax_hash = hash_new ();
+
+  for (memsyntab = mem_access_syntax_table;
+       memsyntab < mem_access_syntax_table + ARRAY_SIZE (mem_access_syntax_table);
+       memsyntab++)
+    {
+      hash_err =
+	hash_insert (mem_syntax_hash, memsyntab->name, (PTR) memsyntab);
+      if (hash_err)
+	as_fatal (_("Internal Error : Can't Hash %s : %s"),
+		  memsyntab->name, hash_err);
+    }
+
+  /* Initialise the lexical tables,mnemonic chars,operand chars.  */
+  for (c = 0; c < 256; c++)
+    {
+      if (ISDIGIT (c))
+	{
+	  digit_chars[c] = c;
+	  mnemonic_chars[c] = c;
+	  operand_chars[c] = c;
+	  register_chars[c] = c;
+	}
+      else if (ISLOWER (c))
+	{
+	  mnemonic_chars[c] = c;
+	  operand_chars[c] = c;
+	  register_chars[c] = c;
+	}
+      else if (ISUPPER (c))
+	{
+	  mnemonic_chars[c] = TOLOWER (c);
+	  register_chars[c] = c;
+	  operand_chars[c] = c;
+	}
+
+      if (ISALPHA (c) || ISDIGIT (c))
+	{
+	  identifier_chars[c] = c;
+	}
+      else if (c > 128)
+	{
+	  identifier_chars[c] = c;
+	  operand_chars[c] = c;
+	}
+    }
+
+  /* All the special characters.  */
+  register_chars['@'] = '@';
+  register_chars['+'] = '+';
+  register_chars['-'] = '-';
+  digit_chars['-'] = '-';
+  identifier_chars['_'] = '_';
+  identifier_chars['.'] = '.';
+  register_chars['['] = '[';
+  register_chars[']'] = ']';
+  operand_chars['_'] = '_';
+  operand_chars['#'] = '#';
+  mnemonic_chars['['] = '[';
+  mnemonic_chars[']'] = ']';
+
+  for (p = operand_special_chars; *p != '\0'; p++)
+    operand_chars[(unsigned char) *p] = (unsigned char) *p;
+}
+
+/* md_assemble - Parse Instr - Seprate menmonics and operands - lookup the
+   menmunonic in the operand table - Parse operands and populate the
+   structure/template - Match the operand with opcode and its validity -
+   Output Instr.  */
+
+void
+md_assemble (char *line)
+{
+  int j;
+
+  char mnemonic[MAX_MNEM_SIZE];
+  char temp4prev[256];
+  static char prev_insn[256];
+
+  /* Initialize globals.  */
+  memset (&i, '\0', sizeof (i));
+  for (j = 0; j < MAX_OPERANDS; j++)
+    i.reloc[j] = NO_RELOC;
+
+  i.prefix = -1;
+  PFX_INSN[0] = 0;
+  PFX_INSN[1] = 0;
+  INSERT_BUFFER[0] = 0;
+  INSERT_BUFFER[1] = 0;
+
+  memcpy (temp4prev, line, strlen (line) + 1);
+
+  save_stack_p = save_stack;
+
+  line = (char *) parse_insn (line, mnemonic);
+  if (line == NULL)
+    return;
+
+  line = (char *) parse_operands (line, mnemonic);
+  if (line == NULL)
+    return;
+
+  /* Next, we find a template that matches the given insn, making sure the
+     overlap of the given operands types is consistent with the template
+     operand types.  */
+  if (!match_template ())
+    return;
+
+  /* In the MAXQ20, there are certain register combinations, and other
+     restrictions which are not allowed. We will try to resolve these right
+     now.  */
+  if (!match_filters ())
+    return;
+
+  /* Check for the approprate PFX register.  */
+  set_prefix ();
+  pfx_for_imm_val (0);
+
+  if (!decode_insn ())		/* decode insn. */
+    need_pass_2 = 1;
+
+  /* Check for Exlipct PFX instruction.  */
+  if (PFX_INSN[0] && (strstr (prev_insn, "PFX") || strstr (prev_insn, "pfx")))
+    as_warn (_("Ineffective insntruction %s \n"), prev_insn);
+
+  memcpy (prev_insn, temp4prev, strlen (temp4prev) + 1);
+
+  /* We are ready to output the insn.  */
+  output_insn ();
+}
diff --git a/gas/config/tc-maxq.h b/gas/config/tc-maxq.h
new file mode 100644
index 0000000..73ba9a9
--- /dev/null
+++ b/gas/config/tc-maxq.h
@@ -0,0 +1,172 @@
+/* tc-maxq.h -- Header file for the asssembler(MAXQ)
+
+   Copyright 2004  Free Software Foundation, Inc.
+
+   Contributed by HCL Technologies Pvt. Ltd.
+
+   Written by Vineet Sharma(vineets@noida.hcltech.com) Inderpreet
+   S.(inderpreetb@noida.hcltech.com)
+
+   This file is part of GAS.
+
+   GAS is free software; you can redistribute it and/or modify it under the
+   terms of the GNU General Public License as published by the Free Software
+   Foundation; either version 2, or (at your option) any later version.
+
+   GAS is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+   details.
+
+   You should have received a copy of the GNU General Public License along
+   with GAS; see the file COPYING.  If not, write to the Free Software
+   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef  _TC_MAXQ_H_
+#define  _TC_MAXQ_H_
+
+#ifndef NO_RELOC
+#define NO_RELOC 0
+#endif
+
+/* `md_short_jump_size' `md_long_jump_size' `md_create_short_jump'
+   `md_create_long_jump' If `WORKING_DOT_WORD' is defined, GAS will not do
+   broken word processing (*note Broken words::.).  Otherwise, you should set
+   `md_short_jump_size' to the size of a short jump (a jump that is just long
+   enough to jump around a long jmp) and `md_long_jump_size' to the size of a
+   long jump (a jump that can go anywhere in the function), You should define
+   `md_create_short_jump' to create a short jump around a long jump, and
+   define `md_create_long_jump' to create a long jump.  */
+#define WORKING_DOT_WORD
+typedef enum _RELOC_ENUM
+{
+  MAXQ_WORDDATA = 5,		/* Word+n.  */
+  MAXQ_LONGDATA = 2,		/* Long+n.  */
+  MAXQ_INTERSEGMENT = 4,	/* Text to any other segment.  */
+  MAXQ_SHORTJUMP = BFD_RELOC_16_PCREL_S2,	/* PC Relative.  */
+  MAXQ_LONGJUMP = 6,		/* Absolute Jump.  */
+  EXTERNAL_RELOC = 8,
+  INTERSEGMENT_RELOC
+}
+RELOC_ENUM;
+
+#ifndef NEED_FX_R_TYPE
+#define NEED_FX_R_TYPE		/* For defining our own rloc type.  */
+#endif
+
+#ifndef MAX_STACK
+#define MAX_STACK 0xf
+#endif
+
+#ifndef TC_MAXQ20
+#define TC_MAXQ20 1
+#endif
+
+#ifndef MAX_OPERAND_SIZE
+#define MAX_OPERAND_SIZE 255
+#endif
+
+#ifndef MAXQ_INSTRUCTION_SIZE
+#define MAXQ_INSTRUCTION_SIZE 2	/* 16 - BITS */
+#endif
+
+#if MAXQ_INSTRUCTION_SIZE
+#define MAXQ_OCTETS_PER_BYTE 	MAXQ_INSTRUCTION_SIZE
+#else
+#define MAXQ_OCTETS_PER_BYTE 	OCTETS_PER_BYTE
+#endif
+
+/* if this macro is defined gas will use this instead of comment_chars.  */
+#define tc_comments_chars maxq20_comment_chars
+
+#define tc_coff_symbol_emit_hook(a)     ;	/* not used */
+
+#define md_section_align(SEGMENT, SIZE)     (SIZE)
+
+/* Locally defined symbol shoudnot be adjusted to section symbol.  */
+#define tc_fix_adjustable(FIX) 0
+
+#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep (frag)
+extern int tc_coff_sizemachdep (fragS * frag);
+
+/* This specifies that the target has been defined as little endian -
+   default.  */
+#define TARGET_BYTES_BIG_ENDIAN 0
+
+#define MAX_MEM_NAME_SIZE 12
+#define MAX_REG_NAME_SIZE  7
+#define MAX_MNEM_SIZE      8
+
+#define END_OF_INSN '\0'
+
+/* This macro is the BFD archetectureto pass to 'bfd_set_arch_mach'.  */
+#define TARGET_ARCH		bfd_arch_maxq
+
+/* This macro is the BFD machine number to pass to 'bfd_set_arch_mach'.
+   If not defines GAS will use 0.  */
+#define TARGET_MACH     	maxq20_mach ()
+extern unsigned long maxq20_mach (void);
+
+/* COFF format.  */
+#ifndef BFD_ASSEMBLER
+
+/* Defines the magic number we are using for the maxq-coff. defined in coff.h.  */
+#define COFF_MAGIC   MAXQ20MAGIC
+#define BFD_ARCH     bfd_arch_maxq
+
+/* Whether the reloc should be outputted to the file or not. This
+   is only true if the symbol we are relocating for is not empty.  */
+#define TC_COUNT_RELOC(fixp) ((fixp) -> fx_addsy != NULL)
+
+/* This macro translates between an internal fix and an coff reloc type.  */
+#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype (fixP)
+extern short tc_coff_fix2rtype (struct fix *);
+
+#endif /* BFD_ASSEMBLER */
+
+#ifndef LEX_AT
+/* We define this macro to generate a fixup for a data allocation pseudo-op.  */
+#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) maxq20_cons_fix_new (FRAG,OFF,LEN,EXP)
+extern void maxq20_cons_fix_new (fragS *, unsigned int, unsigned int, expressionS *);
+#endif
+
+/* Define md_number_to_chars as the appropriate standard big endian or This
+   should just call either `number_to_chars_bigendian' or
+   `number_to_chars_littleendian', whichever is appropriate.  On targets like 
+   the MIPS which support options to change the endianness, which function to 
+   call is a runtime decision.  On other targets, `md_number_to_chars' can be 
+   a simple macro.  */
+#define md_number_to_chars maxq_number_to_chars
+extern void maxq_number_to_chars (char *, valueT, int);
+
+/* If this macro is defined, it is a pointer to a NULL terminated list of
+   chracters which may appear in an operand. GAS already assumes that all
+   alphanumeric chracters, and '$', '.', and '_' may appear in an
+   operand("symbol_char"in app.c). This macro may be defined to treat
+   additional chracters as appearing in an operand. This affects the way in
+   which GAS removes whitespaces before passing the string to md_assemble.  */
+#define tc_symbol_chars_extra_symbol_chars
+
+/* Define away the call to md_operand in the expression parsing code. This is 
+   called whenever the expression parser can't parse the input and gives the
+   assembler backend a chance to deal with it instead.  */
+#define md_operand(x)
+
+#define MAX_OPERANDS           2	/* Max operands per instruction.  */
+#define MAX_IMMEDIATE_OPERANDS 1	/* Max immediate operands per instruction.  */
+#define MAX_MEMORY_OPERANDS    1	/* Max memory operands per instruction.  */
+
+/* Define the prefix we are using while trying to use an immediate value in
+   an instruction. e.g move A[0], #03h.  */
+#define IMMEDIATE_PREFIX '#'
+
+#define ABSOLUTE_PREFIX '@'
+
+/* This here defines the opcode of the nop operation on the MAXQ. We did
+   declare it here when we tried to fill the align bites with nop's but GAS
+   only expects nop's to be single byte instruction.  */
+#define NOP_OPCODE (char)0xDA3A
+
+#define SIZE_OF_PM sizeof(pmodule)	/* Size of the structure.  */
+
+#endif /* TC_MAXQ_H */
diff --git a/gas/configure b/gas/configure
index 14647bc..f3ef240 100755
--- a/gas/configure
+++ b/gas/configure
@@ -971,7 +971,7 @@ esac
     else
       echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2
     fi
-    cd "$ac_popdir"
+    cd $ac_popdir
   done
 fi
 
@@ -1994,7 +1994,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2052,7 +2053,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2168,7 +2170,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2222,7 +2225,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2267,7 +2271,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2311,7 +2316,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2389,7 +2395,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2443,7 +2450,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -3803,7 +3811,7 @@ test x"$pic_mode" = xno && libtool_flags="$libtool_flags --prefer-non-pic"
 case $host in
 *-*-irix6*)
   # Find out which ABI we are using.
-  echo '#line 3806 "configure"' > conftest.$ac_ext
+  echo '#line 3814 "configure"' > conftest.$ac_ext
   if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   (eval $ac_compile) 2>&5
   ac_status=$?
@@ -3899,7 +3907,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -4194,6 +4203,7 @@ _ACEOF
       m683??)		cpu_type=m68k ;;
       m5200)		cpu_type=m68k ;;
       m8*)		cpu_type=m88k ;;
+      maxq)             cpu_type=maxq ;;
       mips*el)		cpu_type=mips endian=little ;;
       mips*)		cpu_type=mips endian=big ;;
       or32*)		cpu_type=or32 endian=big ;;
@@ -4432,6 +4442,8 @@ echo "$as_me: WARNING: GAS support for ${generic_target} is preliminary and a wo
       m88k-motorola-sysv3*)		fmt=coff em=delt88 ;;
       m88k-*-coff*)			fmt=coff ;;
 
+      maxq-*-coff)      		fmt=coff ;;
+
       mcore-*-elf)			fmt=elf ;;
       mcore-*-pe)			fmt=coff em=pe bfd_gas=yes ;;
 
@@ -5576,7 +5588,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5634,7 +5647,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5750,7 +5764,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5804,7 +5819,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5849,7 +5865,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5893,7 +5910,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6055,7 +6073,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6121,7 +6140,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6210,7 +6230,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6613,7 +6634,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6820,7 +6842,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6880,7 +6903,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6959,7 +6983,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7024,7 +7049,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7089,7 +7115,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7153,7 +7180,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7234,7 +7262,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7375,7 +7404,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7513,7 +7543,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7697,7 +7728,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7948,7 +7980,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8142,7 +8175,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8245,7 +8279,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8316,7 +8351,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8418,7 +8454,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8554,7 +8591,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8618,7 +8656,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8673,7 +8712,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8813,7 +8853,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8946,7 +8987,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9214,7 +9256,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9435,7 +9478,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9599,7 +9643,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9680,7 +9725,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9821,7 +9867,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9953,7 +10000,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10066,7 +10114,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10169,7 +10218,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10249,7 +10299,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10310,7 +10361,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10373,7 +10425,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10450,7 +10503,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10536,7 +10590,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10602,7 +10657,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10668,7 +10724,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10734,7 +10791,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10800,7 +10858,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10873,7 +10932,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -11832,6 +11892,11 @@ esac
   *) ac_INSTALL=$ac_top_builddir$INSTALL ;;
   esac
 
+  if test x"$ac_file" != x-; then
+    { echo "$as_me:$LINENO: creating $ac_file" >&5
+echo "$as_me: creating $ac_file" >&6;}
+    rm -f "$ac_file"
+  fi
   # Let's still pretend it is `configure' which instantiates (i.e., don't
   # use $as_me), people would be surprised to read:
   #    /* config.h.  Generated by config.status.  */
@@ -11870,12 +11935,6 @@ echo "$as_me: error: cannot find input file: $f" >&2;}
 	 fi;;
       esac
     done` || { (exit 1); exit 1; }
-
-  if test x"$ac_file" != x-; then
-    { echo "$as_me:$LINENO: creating $ac_file" >&5
-echo "$as_me: creating $ac_file" >&6;}
-    rm -f "$ac_file"
-  fi
 _ACEOF
 cat >>$CONFIG_STATUS <<_ACEOF
   sed "$ac_vpsub
diff --git a/gas/configure.in b/gas/configure.in
index e8d11f3..0de1d75 100644
--- a/gas/configure.in
+++ b/gas/configure.in
@@ -149,6 +149,7 @@ changequote([,])dnl
       m683??)		cpu_type=m68k ;;
       m5200)		cpu_type=m68k ;;
       m8*)		cpu_type=m88k ;;
+      maxq)             cpu_type=maxq ;;
       mips*el)		cpu_type=mips endian=little ;;
       mips*)		cpu_type=mips endian=big ;;
       or32*)		cpu_type=or32 endian=big ;;
@@ -380,6 +381,8 @@ changequote([,])dnl
       m88k-motorola-sysv3*)		fmt=coff em=delt88 ;;
       m88k-*-coff*)			fmt=coff ;;
 
+      maxq-*-coff)      		fmt=coff ;;
+
       mcore-*-elf)			fmt=elf ;;
       mcore-*-pe)			fmt=coff em=pe bfd_gas=yes ;;
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 479b55c..9102803 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
+	    Vineet Sharma      <vineets@noida.hcltech.com>
+
+	* gas/maxq10: New directory.  Contains tests for maxq port.
+	* gas/maxq20: Likewise.
+
 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* gas/i386/general.s: Add movzb.
diff --git a/gas/testsuite/gas/maxq10/bits.d b/gas/testsuite/gas/maxq10/bits.d
new file mode 100644
index 0000000..b5f295a
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/bits.d
@@ -0,0 +1,56 @@
+#objdump: -dw
+#name: call operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <foo>:
+   0:	0a ea [ 	]*MOVE C,Acc.0
+   2:	1a ea [ 	]*MOVE C,Acc.1
+   4:	2a ea [ 	]*MOVE C,Acc.2
+   6:	3a ea [ 	]*MOVE C,Acc.3
+   8:	4a ea [ 	]*MOVE C,Acc.4
+   a:	5a ea [ 	]*MOVE C,Acc.5
+   c:	6a ea [ 	]*MOVE C,Acc.6
+   e:	7a ea [ 	]*MOVE C,Acc.7
+  10:	0a da [ 	]*MOVE C,#0
+  12:	1a da [ 	]*MOVE C,#1
+  14:	0a fa  [ 	]*MOVE Acc.0,C
+  16:	1a fa  [ 	]*MOVE Acc.1,C
+  18:	2a fa [ 	]*MOVE Acc.2,C
+  1a:	3a fa  [ 	]*MOVE Acc.3,C
+  1c:	4a fa [ 	]*MOVE Acc.4,C
+  1e:	5a fa  [ 	]*MOVE Acc.5,C
+  20:	6a fa  [ 	]*MOVE Acc.6,C
+  22:	7a fa  [ 	]*MOVE Acc.7,C
+  24:	2a da [ 	]*CPL C
+  26:	0a 9a [ 	]*AND Acc.0
+  28:	1a 9a [ 	]*AND Acc.1
+  2a:	2a 9a [ 	]*AND Acc.2
+  2c:	3a 9a [ 	]*AND Acc.3
+  2e:	4a 9a [ 	]*AND Acc.4
+  30:	5a 9a [ 	]*AND Acc.5
+  32:	6a 9a [ 	]*AND Acc.6
+  34:	7a 9a [ 	]*AND Acc.7
+  36:	0a aa [ 	]*OR Acc.0
+  38:	1a aa [ 	]*OR Acc.1
+  3a:	2a aa [ 	]*OR Acc.2
+  3c:	3a aa [ 	]*OR Acc.3
+  3e:	4a aa [ 	]*OR Acc.4
+  40:	5a aa [ 	]*OR Acc.5
+  42:	6a aa [ 	]*OR Acc.6
+  44:	7a aa [ 	]*OR Acc.7
+  46:	0a ba [ 	]*XOR Acc.0
+  48:	1a ba [ 	]*XOR Acc.1
+  4a:	2a ba [ 	]*XOR Acc.2
+  4c:	3a ba [ 	]*XOR Acc.3
+  4e:	4a ba [ 	]*XOR Acc.4
+  50:	5a ba [ 	]*XOR Acc.5
+  52:	6a ba [ 	]*XOR Acc.6
+  54:	7a ba [ 	]*XOR Acc.7
+  56:	88 97 [ 	]*MOVE C , SC.1
+  58:	68 87 [ 	]*MOVE C , IMR.0
+  5a:	58 87 [ 	]*MOVE C , IC.0
+  5c:	48 87 [ 	]*MOVE C , PSF.0
+	...
diff --git a/gas/testsuite/gas/maxq10/bits.s b/gas/testsuite/gas/maxq10/bits.s
new file mode 100644
index 0000000..075fb7f
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/bits.s
@@ -0,0 +1,52 @@
+;# bits.s

+;# checks all the bit operations in MAXQ10

+

+.text

+foo:

+ MOVE C, ACC.0	

+ MOVE C, ACC.1

+ MOVE C, ACC.2

+ MOVE C, ACC.3

+ MOVE C, ACC.4

+ MOVE C, ACC.5

+ MOVE C, ACC.6

+ MOVE C, ACC.7		;8 bits on a MAXQ10 machine

+ MOVE C, #0

+ MOVE C, #1

+ MOVE ACC.0, C	

+ MOVE ACC.1, C 

+ MOVE ACC.2, C

+ MOVE ACC.3, C

+ MOVE ACC.4, C

+ MOVE ACC.5, C

+ MOVE ACC.6, C

+ MOVE ACC.7, C		;8 bits on a MAXQ10 machine

+ CPL C

+ AND ACC.0	;AND with carry

+ AND ACC.1	

+ AND ACC.2	

+ AND ACC.3	

+ AND ACC.4	

+ AND ACC.5	

+ AND ACC.6	

+ AND ACC.7	

+ OR ACC.0	;OR with carry

+ OR ACC.1	

+ OR ACC.2	

+ OR ACC.3	

+ OR ACC.4	

+ OR ACC.5	

+ OR ACC.6	

+ OR ACC.7	

+ XOR ACC.0	;XOR with carry

+ XOR ACC.1	

+ XOR ACC.2	

+ XOR ACC.3	

+ XOR ACC.4	

+ XOR ACC.5	

+ XOR ACC.6	

+ XOR ACC.7	

+ MOVE C, SC.1

+ MOVE C, IMR.0

+ MOVE C, IC.0

+ MOVE C, PSF.0		;move program status flag bit 0

diff --git a/gas/testsuite/gas/maxq10/call.d b/gas/testsuite/gas/maxq10/call.d
new file mode 100644
index 0000000..125e165
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/call.d
@@ -0,0 +1,36 @@
+#objdump:  -dw

+#name: call operations

+

+.*: +file format .*

+

+Disassembly of section .text:

+0+000 <foo>:

+   0:	02 3d [ 	]*CALL  #02h

+   2:	00 0b [ 	]*MOVE  PFX\[0\], #00h

+

+0+004 <SmallCall>:

+   4:	0d 8c [ 	]*RET 

+   6:	0d ac [ 	]*RET C

+   8:	0d 9c [ 	]*RET Z

+   a:	0d dc [ 	]*RET NZ

+   c:	0d cc [ 	]*RET S

+   e:	8d 8c [ 	]*RETI 

+  10:	8d ac [ 	]*RETI C

+  12:	8d 9c [ 	]*RETI Z

+  14:	8d dc [ 	]*RETI NZ

+  16:	8d cc [ 	]*RETI S

+  18:	10 7d [ 	]*MOVE  LC\[1\], #10h

+  1a:	00 3d [ 	]*CALL  #00h

+  1c:	ff 5d [ 	]*DJNZ  LC\[1\], #ffh

+  1e:	10 7d [ 	]*MOVE  LC\[1\], #10h

+  20:	00 3d [ 	]*CALL  #00h

+	...

+ 422:	00 0b [ 	]*MOVE  PFX\[0\], #00h

+ 424:	1c 5d [ 	]*DJNZ  LC\[1\], #1ch

+

+ 426:	8d 8c [ 	]*RETI 

+ 428:	8d ac [ 	]*RETI C

+ 42a:	8d 9c [ 	]*RETI Z

+ 42c:	8d dc [ 	]*RETI NZ

+ 42e:	8d cc [ 	]*RETI S

+	...

diff --git a/gas/testsuite/gas/maxq10/call.s b/gas/testsuite/gas/maxq10/call.s
new file mode 100644
index 0000000..f8b4c0f
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/call.s
@@ -0,0 +1,32 @@
+;# calls.s
+;# check program flow instruction involving CALL & RET in MAXQ10
+.text
+foo:
+	Call SmallCall
+	Call LongCall
+SmallCall:
+	RET
+	RET C
+	RET Z
+	RET NZ
+	RET S 
+	RETI
+	RETI C
+	RETI Z
+	RETI NZ
+	RETI S
+	MOVE LC[1], #10h
+LoopTop:
+	Call LoopTop
+	DJNZ LC[1], LoopTop
+	MOVE LC[1], #10h
+LoopTop1:
+	Call LoopTop1
+	.fill 0x200, 2, 0 
+	DJNZ LC[1], LoopTop
+LongCall:
+	RETI
+	RETI C
+	RETI Z
+	RETI NZ
+	RETI S
diff --git a/gas/testsuite/gas/maxq10/data.s b/gas/testsuite/gas/maxq10/data.s
new file mode 100644
index 0000000..36176c6
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/data.s
@@ -0,0 +1,977 @@
+;# data.s	
+;# checks all the data transfer instructions for MAXQ10
+foo:
+;	XCH			; Not in MAXQ10
+	XCHN
+	MOVE NUL, #01h
+	MOVE NUL, AP
+	MOVE NUL, APC
+	MOVE NUL, PSF
+	MOVE NUL, IC
+	MOVE NUL, IMR
+	MOVE NUL, SC
+	MOVE NUL, IIR
+	MOVE NUL, CKCN
+	MOVE NUL, WDCN
+	MOVE NUL, A[0]		;Just Check two boundary conditions
+	MOVE NUL, A[15]   
+	MOVE NUL, ACC
+	MOVE NUL, A[AP]
+	MOVE NUL, IP
+	MOVE NUL, @SP--
+	MOVE NUL, SP
+	MOVE NUL, IV
+	MOVE NUL, LC[0]
+	MOVE NUL, LC[1]
+	MOVE NUL, @BP[OFFS++]
+	MOVE NUL, @BP[OFFS--]
+	MOVE NUL, OFFS
+	MOVE NUL, DPC
+	MOVE NUL, GR
+	MOVE NUL, GRL
+	MOVE NUL, BP
+	MOVE NUL, GRS
+	MOVE NUL, GRH
+	MOVE NUL, GRXL
+	MOVE NUL, FP
+	MOVE NUL, @DP[0]	
+	MOVE NUL, @DP[1]	
+	MOVE NUL, @DP[0]++		
+	MOVE NUL, @DP[1]++
+	MOVE NUL, @DP[0]--
+	MOVE NUL, @DP[1]--
+	MOVE AP, #01h
+	MOVE AP, APC
+	MOVE AP, PSF
+	MOVE AP, IC
+	MOVE AP, IMR
+	MOVE AP, SC
+	MOVE AP, IIR
+	MOVE AP, CKCN
+	MOVE AP, WDCN
+	MOVE AP, A[0]		;Just Check two boundary conditions
+	MOVE AP, A[15]   
+	MOVE AP, ACC
+	MOVE AP, A[AP]
+	MOVE AP, IP
+	MOVE AP, @SP--
+	MOVE AP, SP
+	MOVE AP, IV
+	MOVE AP, LC[0]
+	MOVE AP, LC[1]
+	MOVE AP, @BP[OFFS++]
+	MOVE AP, @BP[OFFS--]
+	MOVE AP, OFFS
+	MOVE AP, DPC
+	MOVE AP, GR
+	MOVE AP, GRL
+	MOVE AP, BP
+	MOVE AP, GRS
+	MOVE AP, GRH
+	MOVE AP, GRXL
+	MOVE AP, FP
+	MOVE AP, @DP[0]	
+	MOVE AP, @DP[1]	
+	MOVE AP, @DP[0]++		
+	MOVE AP, @DP[1]++
+	MOVE AP, @DP[0]--
+	MOVE AP, @DP[1]--
+	MOVE APC, #01h
+	MOVE APC, AP
+	MOVE APC, PSF
+	MOVE APC, IC
+	MOVE APC, IMR
+	MOVE APC, SC
+	MOVE APC, IIR
+	MOVE APC, CKCN
+	MOVE APC, WDCN
+	MOVE APC, A[0]		;Just Check two boundary conditions
+	MOVE APC, A[15]   
+	MOVE APC, ACC
+	MOVE APC, A[AP]
+	MOVE APC, IP
+	MOVE APC, @SP--
+	MOVE APC, SP
+	MOVE APC, IV
+	MOVE APC, LC[0]
+	MOVE APC, LC[1]
+	MOVE APC, @BP[OFFS++]
+	MOVE APC, @BP[OFFS--]
+	MOVE APC, OFFS
+	MOVE APC, DPC
+	MOVE APC, GR
+	MOVE APC, GRL
+	MOVE APC, BP
+	MOVE APC, GRS
+	MOVE APC, GRH
+	MOVE APC, GRXL
+	MOVE APC, FP
+	MOVE APC, @DP[0]	
+	MOVE APC, @DP[1]	
+	MOVE APC, @DP[0]++		
+	MOVE APC, @DP[1]++
+	MOVE APC, @DP[0]--
+	MOVE APC, @DP[1]--
+	MOVE PSF, #01h
+	MOVE PSF, AP
+	MOVE PSF, APC
+	MOVE PSF, IC
+	MOVE PSF, IMR
+	MOVE PSF, SC
+	MOVE PSF, IIR
+	MOVE PSF, CKCN
+	MOVE PSF, WDCN
+	MOVE PSF, A[0]		;Just Check two boundary conditions
+	MOVE PSF, A[15]   
+	MOVE PSF, ACC
+	MOVE PSF, A[AP]
+	MOVE PSF, IP
+	MOVE PSF, @SP--
+	MOVE PSF, SP
+	MOVE PSF, IV
+	MOVE PSF, LC[0]
+	MOVE PSF, LC[1]
+	MOVE PSF, @BP[OFFS++]
+	MOVE PSF, @BP[OFFS--]
+	MOVE PSF, OFFS
+	MOVE PSF, DPC
+	MOVE PSF, GR
+	MOVE PSF, GRL
+	MOVE PSF, BP
+	MOVE PSF, GRS
+	MOVE PSF, GRH
+	MOVE PSF, GRXL
+	MOVE PSF, FP
+	MOVE PSF, @DP[0]	
+	MOVE PSF, @DP[1]	
+	MOVE PSF, @DP[0]++		
+	MOVE PSF, @DP[1]++
+	MOVE PSF, @DP[0]--
+	MOVE PSF, @DP[1]--
+	MOVE IC, #01h
+	MOVE IC, AP
+	MOVE IC, APC
+	MOVE IC, PSF
+	MOVE IC, IMR
+	MOVE IC, SC
+	MOVE IC, IIR
+	MOVE IC, CKCN
+	MOVE IC, WDCN
+	MOVE IC, A[0]		;Just Check two boundary conditions
+	MOVE IC, A[15]   
+	MOVE IC, ACC
+	MOVE IC, A[AP]
+	MOVE IC, IP
+	MOVE IC, @SP--
+	MOVE IC, SP
+	MOVE IC, IV
+	MOVE IC, LC[0]
+	MOVE IC, LC[1]
+	MOVE IC, @BP[OFFS++]
+	MOVE IC, @BP[OFFS--]
+	MOVE IC, OFFS
+	MOVE IC, DPC
+	MOVE IC, GR
+	MOVE IC, GRL
+	MOVE IC, BP
+	MOVE IC, GRS
+	MOVE IC, GRH
+	MOVE IC, GRXL
+	MOVE IC, FP
+	MOVE IC, @DP[0]	
+	MOVE IC, @DP[1]	
+	MOVE IC, @DP[0]++		
+	MOVE IC, @DP[1]++
+	MOVE IC, @DP[0]--
+	MOVE IC, @DP[1]--
+	MOVE IMR, #01h
+	MOVE IMR, AP
+	MOVE IMR, APC
+	MOVE IMR, PSF
+	MOVE IMR, IC
+	MOVE IMR, SC
+	MOVE IMR, IIR
+	MOVE IMR, CKCN
+	MOVE IMR, WDCN
+	MOVE IMR, A[0]		;Just Check two boundary conditions
+	MOVE IMR, A[15]   
+	MOVE IMR, ACC
+	MOVE IMR, A[AP]
+	MOVE IMR, IP
+	MOVE IMR, @SP--
+	MOVE IMR, SP
+	MOVE IMR, IV
+	MOVE IMR, LC[0]
+	MOVE IMR, LC[1]
+	MOVE IMR, @BP[OFFS++]
+	MOVE IMR, @BP[OFFS--]
+	MOVE IMR, OFFS
+	MOVE IMR, DPC
+	MOVE IMR, GR
+	MOVE IMR, GRL
+	MOVE IMR, BP
+	MOVE IMR, GRS
+	MOVE IMR, GRH
+	MOVE IMR, GRXL
+	MOVE IMR, FP
+	MOVE IMR, @DP[0]	
+	MOVE IMR, @DP[1]	
+	MOVE IMR, @DP[0]++		
+	MOVE IMR, @DP[1]++
+	MOVE IMR, @DP[0]--
+	MOVE IMR, @DP[1]--
+	MOVE A[0], #01h
+	MOVE A[0], AP
+	MOVE A[0], APC
+	MOVE A[0], PSF
+	MOVE A[0], IC
+	MOVE A[0], IMR
+	MOVE A[0], SC
+	MOVE A[0], IIR
+	MOVE A[0], CKCN
+	MOVE A[0], WDCN
+	MOVE A[0], ACC
+	MOVE A[0], A[AP]
+	MOVE A[0], IP
+	MOVE A[0], @SP--
+	MOVE A[0], SP
+	MOVE A[0], IV
+	MOVE A[0], LC[0]
+	MOVE A[0], LC[1]
+	MOVE A[0], @BP[OFFS++]
+	MOVE A[0], @BP[OFFS--]
+	MOVE A[0], OFFS
+	MOVE A[0], DPC
+	MOVE A[0], GR
+	MOVE A[0], GRL
+	MOVE A[0], BP
+	MOVE A[0], GRS
+	MOVE A[0], GRH
+	MOVE A[0], GRXL
+	MOVE A[0], FP
+	MOVE A[0], @DP[0]	
+	MOVE A[0], @DP[1]	
+	MOVE A[0], @DP[0]++		
+	MOVE A[0], @DP[1]++
+	MOVE A[0], @DP[0]--
+	MOVE A[0], @DP[1]--
+	MOVE ACC, #01h
+	MOVE ACC, AP
+	MOVE ACC, APC
+	MOVE ACC, PSF
+	MOVE ACC, IC
+	MOVE ACC, IMR
+	MOVE ACC, SC
+	MOVE ACC, IIR
+	MOVE ACC, CKCN
+	MOVE ACC, WDCN
+	MOVE ACC, A[0]		;Just Check two boundary conditions
+	MOVE ACC, A[15]   
+	MOVE ACC, IP
+	MOVE ACC, @SP--
+	MOVE ACC, SP
+	MOVE ACC, IV
+	MOVE ACC, LC[0]
+	MOVE ACC, LC[1]
+	MOVE ACC, @BP[OFFS++]
+	MOVE ACC, @BP[OFFS--]
+	MOVE ACC, OFFS
+	MOVE ACC, DPC
+	MOVE ACC, GR
+	MOVE ACC, GRL
+	MOVE ACC, BP
+	MOVE ACC, GRS
+	MOVE ACC, GRH
+	MOVE ACC, GRXL
+	MOVE ACC, FP
+	MOVE ACC, @DP[0]	
+	MOVE ACC, @DP[1]	
+	MOVE ACC, @DP[0]++		
+	MOVE ACC, @DP[1]++
+	MOVE ACC, @DP[0]--
+	MOVE ACC, @DP[1]--
+	MOVE @++SP, #01h
+	MOVE @++SP, AP
+	MOVE @++SP, APC
+	MOVE @++SP, PSF
+	MOVE @++SP, IC
+	MOVE @++SP, IMR
+	MOVE @++SP, SC
+	MOVE @++SP, IIR
+	MOVE @++SP, CKCN
+	MOVE @++SP, WDCN
+	MOVE @++SP, A[0]		;Just Check two boundary conditions
+	MOVE @++SP, A[15]   
+	MOVE @++SP, ACC
+	MOVE @++SP, A[AP]
+	MOVE @++SP, IP
+	MOVE @++SP, SP
+	MOVE @++SP, IV
+	MOVE @++SP, LC[0]
+	MOVE @++SP, LC[1]
+	MOVE @++SP, @BP[OFFS++]
+	MOVE @++SP, @BP[OFFS--]
+	MOVE @++SP, OFFS
+	MOVE @++SP, DPC
+	MOVE @++SP, GR
+	MOVE @++SP, GRL
+	MOVE @++SP, BP
+	MOVE @++SP, GRS
+	MOVE @++SP, GRH
+	MOVE @++SP, GRXL
+	MOVE @++SP, FP
+	MOVE @++SP, @DP[0]	
+	MOVE @++SP, @DP[1]	
+	MOVE @++SP, @DP[0]++		
+	MOVE @++SP, @DP[1]++
+	MOVE @++SP, @DP[0]--
+	MOVE @++SP, @DP[1]--
+	MOVE SP, #01h
+	MOVE SP, AP
+	MOVE SP, APC
+	MOVE SP, PSF
+	MOVE SP, IC
+	MOVE SP, IMR
+	MOVE SP, SC
+	MOVE SP, IIR
+	MOVE SP, CKCN
+	MOVE SP, WDCN
+	MOVE SP, A[0]		;Just Check two boundary conditions
+	MOVE SP, A[15]   
+	MOVE SP, ACC
+	MOVE SP, A[AP]
+	MOVE SP, IP
+	MOVE SP, IV
+	MOVE SP, LC[0]
+	MOVE SP, LC[1]
+	MOVE SP, @BP[OFFS++]
+	MOVE SP, @BP[OFFS--]
+	MOVE SP, OFFS
+	MOVE SP, DPC
+	MOVE SP, GR
+	MOVE SP, GRL
+	MOVE SP, BP
+	MOVE SP, GRS
+	MOVE SP, GRH
+	MOVE SP, GRXL
+	MOVE SP, FP
+	MOVE SP, @DP[0]	
+	MOVE SP, @DP[1]	
+	MOVE SP, @DP[0]++		
+	MOVE SP, @DP[1]++
+	MOVE SP, @DP[0]--
+	MOVE SP, @DP[1]--
+	MOVE IV, #01h
+	MOVE IV, AP
+	MOVE IV, APC
+	MOVE IV, PSF
+	MOVE IV, IC
+	MOVE IV, IMR
+	MOVE IV, SC
+	MOVE IV, IIR
+	MOVE IV, CKCN
+	MOVE IV, WDCN
+	MOVE IV, A[0]		;Just Check two boundary conditions
+	MOVE IV, A[15]   
+	MOVE IV, ACC
+	MOVE IV, A[AP]
+	MOVE IV, IP
+	MOVE IV, @SP--
+	MOVE IV, SP
+	MOVE IV, IV
+	MOVE IV, LC[0]
+	MOVE IV, LC[1]
+	MOVE IV, @BP[OFFS++]
+	MOVE IV, @BP[OFFS--]
+	MOVE IV, OFFS
+	MOVE IV, DPC
+	MOVE IV, GR
+	MOVE IV, GRL
+	MOVE IV, BP
+	MOVE IV, GRS
+	MOVE IV, GRH
+	MOVE IV, GRXL
+	MOVE IV, FP
+	MOVE IV, @DP[0]	
+	MOVE IV, @DP[1]	
+	MOVE IV, @DP[0]++		
+	MOVE IV, @DP[1]++
+	MOVE IV, @DP[0]--
+	MOVE IV, @DP[1]--
+	MOVE LC[0], #01h
+	MOVE LC[0], AP
+	MOVE LC[0], APC
+	MOVE LC[0], PSF
+	MOVE LC[0], IC
+	MOVE LC[0], IMR
+	MOVE LC[0], SC
+	MOVE LC[0], IIR
+	MOVE LC[0], CKCN
+	MOVE LC[0], WDCN
+	MOVE LC[0], A[0]		;Just Check two boundary conditions
+	MOVE LC[0], A[15]   
+	MOVE LC[0], ACC
+	MOVE LC[0], A[AP]
+	MOVE LC[0], IP
+	MOVE LC[0], @SP--
+	MOVE LC[0], SP
+	MOVE LC[0], IV
+	MOVE LC[0], @BP[OFFS++]
+	MOVE LC[0], @BP[OFFS--]
+	MOVE LC[0], OFFS
+	MOVE LC[0], DPC
+	MOVE LC[0], GR
+	MOVE LC[0], GRL
+	MOVE LC[0], BP
+	MOVE LC[0], GRS
+	MOVE LC[0], GRH
+	MOVE LC[0], GRXL
+	MOVE LC[0], FP
+	MOVE LC[0], @DP[0]	
+	MOVE LC[0], @DP[1]	
+	MOVE LC[0], @DP[0]++		
+	MOVE LC[0], @DP[1]++
+	MOVE LC[0], @DP[0]--
+	MOVE LC[0], @DP[1]--
+	MOVE @BP[OFFS], #01h
+	MOVE @BP[OFFS], AP
+	MOVE @BP[OFFS], APC
+	MOVE @BP[OFFS], PSF
+	MOVE @BP[OFFS], IC
+	MOVE @BP[OFFS], IMR
+	MOVE @BP[OFFS], SC
+	MOVE @BP[OFFS], IIR
+	MOVE @BP[OFFS], CKCN
+	MOVE @BP[OFFS], WDCN
+	MOVE @BP[OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[OFFS], A[15]   
+	MOVE @BP[OFFS], ACC
+	MOVE @BP[OFFS], A[AP]
+	MOVE @BP[OFFS], IP
+	MOVE @BP[OFFS], @SP--
+	MOVE @BP[OFFS], SP
+	MOVE @BP[OFFS], IV
+	MOVE @BP[OFFS], LC[0]
+	MOVE @BP[OFFS], LC[1]
+	MOVE @BP[OFFS], OFFS
+	MOVE @BP[OFFS], DPC
+	MOVE @BP[OFFS], GR
+	MOVE @BP[OFFS], GRL
+	MOVE @BP[OFFS], BP
+	MOVE @BP[OFFS], GRS
+	MOVE @BP[OFFS], GRH
+	MOVE @BP[OFFS], GRXL
+	MOVE @BP[OFFS], FP
+	MOVE @BP[OFFS], @DP[0]	
+	MOVE @BP[OFFS], @DP[1]	
+	MOVE @BP[OFFS], @DP[0]++		
+	MOVE @BP[OFFS], @DP[1]++
+	MOVE @BP[OFFS], @DP[0]--
+	MOVE @BP[OFFS], @DP[1]--
+	MOVE @BP[++OFFS], #01h
+	MOVE @BP[++OFFS], AP
+	MOVE @BP[++OFFS], APC
+	MOVE @BP[++OFFS], PSF
+	MOVE @BP[++OFFS], IC
+	MOVE @BP[++OFFS], IMR
+	MOVE @BP[++OFFS], SC
+	MOVE @BP[++OFFS], IIR
+	MOVE @BP[++OFFS], CKCN
+	MOVE @BP[++OFFS], WDCN
+	MOVE @BP[++OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[++OFFS], A[15]   
+	MOVE @BP[++OFFS], ACC
+	MOVE @BP[++OFFS], A[AP]
+	MOVE @BP[++OFFS], IP
+	MOVE @BP[++OFFS], SP
+	MOVE @BP[++OFFS], IV
+	MOVE @BP[++OFFS], LC[0]
+	MOVE @BP[++OFFS], LC[1]
+	MOVE @BP[++OFFS], OFFS
+	MOVE @BP[++OFFS], DPC
+	MOVE @BP[++OFFS], GR
+	MOVE @BP[++OFFS], GRL
+	MOVE @BP[++OFFS], BP
+	MOVE @BP[++OFFS], GRS
+	MOVE @BP[++OFFS], GRH
+	MOVE @BP[++OFFS], GRXL
+	MOVE @BP[++OFFS], FP
+	MOVE @BP[++OFFS], @DP[0]	
+	MOVE @BP[++OFFS], @DP[1]	
+	MOVE @BP[++OFFS], @DP[0]--
+	MOVE @BP[++OFFS], @DP[1]--
+	MOVE @BP[--OFFS], #01h
+	MOVE @BP[--OFFS], AP
+	MOVE @BP[--OFFS], APC
+	MOVE @BP[--OFFS], PSF
+	MOVE @BP[--OFFS], IC
+	MOVE @BP[--OFFS], IMR
+	MOVE @BP[--OFFS], SC
+	MOVE @BP[--OFFS], IIR
+	MOVE @BP[--OFFS], CKCN
+	MOVE @BP[--OFFS], WDCN
+	MOVE @BP[--OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[--OFFS], A[15]   
+	MOVE @BP[--OFFS], ACC
+	MOVE @BP[--OFFS], A[AP]
+	MOVE @BP[--OFFS], IP
+	MOVE @BP[--OFFS], SP
+	MOVE @BP[--OFFS], IV
+	MOVE @BP[--OFFS], LC[0]
+	MOVE @BP[--OFFS], LC[1]
+	MOVE @BP[--OFFS], OFFS
+	MOVE @BP[--OFFS], DPC
+	MOVE @BP[--OFFS], GR
+	MOVE @BP[--OFFS], GRL
+	MOVE @BP[--OFFS], BP
+	MOVE @BP[--OFFS], GRS
+	MOVE @BP[--OFFS], GRH
+	MOVE @BP[--OFFS], GRXL
+	MOVE @BP[--OFFS], FP
+	MOVE @BP[--OFFS], @DP[0]	
+	MOVE @BP[--OFFS], @DP[1]	
+	MOVE OFFS, #01h
+	MOVE OFFS, AP
+	MOVE OFFS, APC
+	MOVE OFFS, PSF
+	MOVE OFFS, IC
+	MOVE OFFS, IMR
+	MOVE OFFS, SC
+	MOVE OFFS, IIR
+	MOVE OFFS, CKCN
+	MOVE OFFS, WDCN
+	MOVE OFFS, A[0]		;Just Check two boundary conditions
+	MOVE OFFS, A[15]   
+	MOVE OFFS, ACC
+	MOVE OFFS, A[AP]
+	MOVE OFFS, IP
+	MOVE OFFS, @SP--
+	MOVE OFFS, SP
+	MOVE OFFS, IV
+	MOVE OFFS, LC[0]
+	MOVE OFFS, LC[1]
+	MOVE OFFS, DPC
+	MOVE OFFS, GR
+	MOVE OFFS, GRL
+	MOVE OFFS, BP
+	MOVE OFFS, GRS
+	MOVE OFFS, GRH
+	MOVE OFFS, GRXL
+	MOVE OFFS, FP
+	MOVE OFFS, @DP[0]	
+	MOVE OFFS, @DP[1]	
+	MOVE OFFS, @DP[0]++		
+	MOVE OFFS, @DP[1]++
+	MOVE OFFS, @DP[0]--
+	MOVE OFFS, @DP[1]--
+	MOVE DPC, #01h
+	MOVE DPC, AP
+	MOVE DPC, APC
+	MOVE DPC, PSF
+	MOVE DPC, IC
+	MOVE DPC, IMR
+	MOVE DPC, SC
+	MOVE DPC, IIR
+	MOVE DPC, CKCN
+	MOVE DPC, WDCN
+	MOVE DPC, A[0]		;Just Check two boundary conditions
+	MOVE DPC, A[15]   
+	MOVE DPC, ACC
+	MOVE DPC, A[AP]
+	MOVE DPC, IP
+	MOVE DPC, @SP--
+	MOVE DPC, SP
+	MOVE DPC, IV
+	MOVE DPC, LC[0]
+	MOVE DPC, LC[1]
+	MOVE DPC, @BP[OFFS++]
+	MOVE DPC, @BP[OFFS--]
+	MOVE DPC, OFFS
+	MOVE DPC, GR
+	MOVE DPC, GRL
+	MOVE DPC, BP
+	MOVE DPC, GRS
+	MOVE DPC, GRH
+	MOVE DPC, GRXL
+	MOVE DPC, FP
+	MOVE DPC, @DP[0]	
+	MOVE DPC, @DP[1]	
+	MOVE DPC, @DP[0]++		
+	MOVE DPC, @DP[1]++
+	MOVE DPC, @DP[0]--
+	MOVE DPC, @DP[1]--
+	MOVE GR, #01h
+	MOVE GR, AP
+	MOVE GR, APC
+	MOVE GR, PSF
+	MOVE GR, IC
+	MOVE GR, IMR
+	MOVE GR, SC
+	MOVE GR, IIR
+	MOVE GR, CKCN
+	MOVE GR, WDCN
+	MOVE GR, A[0]		;Just Check two boundary conditions
+	MOVE GR, A[15]   
+	MOVE GR, ACC
+	MOVE GR, A[AP]
+	MOVE GR, IP
+	MOVE GR, @SP--
+	MOVE GR, SP
+	MOVE GR, IV
+	MOVE GR, LC[0]
+	MOVE GR, LC[1]
+	MOVE GR, @BP[OFFS++]
+	MOVE GR, @BP[OFFS--]
+	MOVE GR, OFFS
+	MOVE GR, DPC
+	MOVE GR, GRL
+	MOVE GR, BP
+	MOVE GR, GRS
+	MOVE GR, GRH
+	MOVE GR, GRXL
+	MOVE GR, FP
+	MOVE GR, @DP[0]	
+	MOVE GR, @DP[1]	
+	MOVE GR, @DP[0]++		
+	MOVE GR, @DP[1]++
+	MOVE GR, @DP[0]--
+	MOVE GR, @DP[1]--
+	MOVE GRL, #01h
+	MOVE GRL, AP
+	MOVE GRL, APC
+	MOVE GRL, PSF
+	MOVE GRL, IC
+	MOVE GRL, IMR
+	MOVE GRL, SC
+	MOVE GRL, IIR
+	MOVE GRL, CKCN
+	MOVE GRL, WDCN
+	MOVE GRL, A[0]		;Just Check two boundary conditions
+	MOVE GRL, A[15]   
+	MOVE GRL, ACC
+	MOVE GRL, A[AP]
+	MOVE GRL, IP
+	MOVE GRL, @SP--
+	MOVE GRL, SP
+	MOVE GRL, IV
+	MOVE GRL, LC[0]
+	MOVE GRL, LC[1]
+	MOVE GRL, @BP[OFFS++]
+	MOVE GRL, @BP[OFFS--]
+	MOVE GRL, OFFS
+	MOVE GRL, DPC
+	MOVE GRL, GR
+	MOVE GRL, BP
+	MOVE GRL, GRS
+	MOVE GRL, GRH
+	MOVE GRL, GRXL
+	MOVE GRL, FP
+	MOVE GRL, @DP[0]	
+	MOVE GRL, @DP[1]	
+	MOVE GRL, @DP[0]++		
+	MOVE GRL, @DP[1]++
+	MOVE GRL, @DP[0]--
+	MOVE GRL, @DP[1]--
+	MOVE BP, #01h
+	MOVE BP, AP
+	MOVE BP, APC
+	MOVE BP, PSF
+	MOVE BP, IC
+	MOVE BP, IMR
+	MOVE BP, SC
+	MOVE BP, IIR
+	MOVE BP, CKCN
+	MOVE BP, WDCN
+	MOVE BP, A[0]		;Just Check two boundary conditions
+	MOVE BP, A[15]   
+	MOVE BP, ACC
+	MOVE BP, A[AP]
+	MOVE BP, IP
+	MOVE BP, @SP--
+	MOVE BP, SP
+	MOVE BP, IV
+	MOVE BP, LC[0]
+	MOVE BP, LC[1]
+	MOVE BP, @BP[OFFS++]
+	MOVE BP, @BP[OFFS--]
+	MOVE BP, OFFS
+	MOVE BP, DPC
+	MOVE BP, GR
+	MOVE BP, GRL
+	MOVE BP, GRS
+	MOVE BP, GRH
+	MOVE BP, GRXL
+	MOVE BP, FP
+	MOVE BP, @DP[0]	
+	MOVE BP, @DP[1]	
+	MOVE BP, @DP[0]++		
+	MOVE BP, @DP[1]++
+	MOVE BP, @DP[0]--
+	MOVE BP, @DP[1]--
+	MOVE @DP[0], #01h
+	MOVE @DP[0], AP
+	MOVE @DP[0], APC
+	MOVE @DP[0], PSF
+	MOVE @DP[0], IC
+	MOVE @DP[0], IMR
+	MOVE @DP[0], SC
+	MOVE @DP[0], IIR
+	MOVE @DP[0], CKCN
+	MOVE @DP[0], WDCN
+	MOVE @DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @DP[0], A[15]   
+	MOVE @DP[0], ACC
+	MOVE @DP[0], A[AP]
+	MOVE @DP[0], IP
+	MOVE @DP[0], @SP--
+	MOVE @DP[0], SP
+	MOVE @DP[0], IV
+	MOVE @DP[0], LC[0]
+	MOVE @DP[0], LC[1]
+	MOVE @DP[0], @BP[OFFS++]
+	MOVE @DP[0], @BP[OFFS--]
+	MOVE @DP[0], OFFS
+	MOVE @DP[0], DPC
+	MOVE @DP[0], GR
+	MOVE @DP[0], GRL
+	MOVE @DP[0], BP
+	MOVE @DP[0], GRS
+	MOVE @DP[0], GRH
+	MOVE @DP[0], GRXL
+	MOVE @DP[0], FP
+	MOVE @++DP[0], #01h
+	MOVE @++DP[0], AP
+	MOVE @++DP[0], APC
+	MOVE @++DP[0], PSF
+	MOVE @++DP[0], IC
+	MOVE @++DP[0], IMR
+	MOVE @++DP[0], SC
+	MOVE @++DP[0], IIR
+	MOVE @++DP[0], CKCN
+	MOVE @++DP[0], WDCN
+	MOVE @++DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @++DP[0], A[15]   
+	MOVE @++DP[0], ACC
+	MOVE @++DP[0], A[AP]
+	MOVE @++DP[0], IP
+	MOVE @++DP[0], @SP--
+	MOVE @++DP[0], SP
+	MOVE @++DP[0], IV
+	MOVE @++DP[0], LC[0]
+	MOVE @++DP[0], LC[1]
+	MOVE @++DP[0], @BP[OFFS++]
+	MOVE @++DP[0], @BP[OFFS--]
+	MOVE @++DP[0], OFFS
+	MOVE @++DP[0], DPC
+	MOVE @++DP[0], GR
+	MOVE @++DP[0], GRL
+	MOVE @++DP[0], BP
+	MOVE @++DP[0], GRS
+	MOVE @++DP[0], GRH
+	MOVE @++DP[0], GRXL
+	MOVE @++DP[0], FP
+	MOVE @--DP[0], #01h
+	MOVE @--DP[0], AP
+	MOVE @--DP[0], APC
+	MOVE @--DP[0], PSF
+	MOVE @--DP[0], IC
+	MOVE @--DP[0], IMR
+	MOVE @--DP[0], SC
+	MOVE @--DP[0], IIR
+	MOVE @--DP[0], CKCN
+	MOVE @--DP[0], WDCN
+	MOVE @--DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @--DP[0], A[15]   
+	MOVE @--DP[0], ACC
+	MOVE @--DP[0], A[AP]
+	MOVE @--DP[0], IP
+	MOVE @--DP[0], @SP--
+	MOVE @--DP[0], SP
+	MOVE @--DP[0], IV
+	MOVE @--DP[0], LC[0]
+	MOVE @--DP[0], LC[1]
+	MOVE @--DP[0], @BP[OFFS++]
+	MOVE @--DP[0], @BP[OFFS--]
+	MOVE @--DP[0], OFFS
+	MOVE @--DP[0], DPC
+	MOVE @--DP[0], GR
+	MOVE @--DP[0], GRL
+	MOVE @--DP[0], BP
+	MOVE @--DP[0], GRS
+	MOVE @--DP[0], GRH
+	MOVE @--DP[0], GRXL
+	MOVE @--DP[0], FP
+	MOVE DP[0], #01h
+	MOVE DP[0], AP
+	MOVE DP[0], APC
+	MOVE DP[0], PSF
+	MOVE DP[0], IC
+	MOVE DP[0], IMR
+	MOVE DP[0], SC
+	MOVE DP[0], IIR
+	MOVE DP[0], CKCN
+	MOVE DP[0], WDCN
+	MOVE DP[0], A[0]		;Just Check two boundary conditions
+	MOVE DP[0], A[15]   
+	MOVE DP[0], ACC
+	MOVE DP[0], A[AP]
+	MOVE DP[0], IP
+	MOVE DP[0], @SP--
+	MOVE DP[0], SP
+	MOVE DP[0], IV
+	MOVE DP[0], LC[0]
+	MOVE DP[0], LC[1]
+	MOVE DP[0], @BP[OFFS++]
+	MOVE DP[0], @BP[OFFS--]
+	MOVE DP[0], OFFS
+	MOVE DP[0], DPC
+	MOVE DP[0], GR
+	MOVE DP[0], GRL
+	MOVE DP[0], BP
+	MOVE DP[0], GRS
+	MOVE DP[0], GRH
+	MOVE DP[0], GRXL
+	MOVE DP[0], FP
+	MOVE SC, #01h
+	MOVE SC, AP
+	MOVE SC, APC
+	MOVE SC, PSF
+	MOVE SC, IC
+	MOVE SC, IMR
+	MOVE SC, IIR
+	MOVE SC, CKCN
+	MOVE SC, WDCN
+	MOVE SC, A[0]		;Just Check two boundary conditions
+	MOVE SC, A[15]   
+	MOVE SC, ACC
+	MOVE SC, A[AP]
+	MOVE SC, IP
+	MOVE SC, @SP--
+	MOVE SC, SP
+	MOVE SC, IV
+	MOVE SC, LC[0]
+	MOVE SC, LC[1]
+	MOVE SC, @BP[OFFS++]
+	MOVE SC, @BP[OFFS--]
+	MOVE SC, OFFS
+	MOVE SC, DPC
+	MOVE SC, GR
+	MOVE SC, GRL
+	MOVE SC, BP
+	MOVE SC, GRS
+	MOVE SC, GRH
+	MOVE SC, GRXL
+	MOVE SC, FP
+	MOVE SC, @DP[0]	
+	MOVE SC, @DP[1]	
+	MOVE SC, @DP[0]++		
+	MOVE SC, @DP[1]++
+	MOVE SC, @DP[0]--
+	MOVE SC, @DP[1]--
+	MOVE CKCN, #01h
+	MOVE CKCN, AP
+	MOVE CKCN, APC
+	MOVE CKCN, PSF
+	MOVE CKCN, IC
+	MOVE CKCN, IMR
+	MOVE CKCN, SC
+	MOVE CKCN, IIR
+	MOVE CKCN, WDCN
+	MOVE CKCN, A[0]		;Just Check two boundary conditions
+	MOVE CKCN, A[15]   
+	MOVE CKCN, ACC
+	MOVE CKCN, A[AP]
+	MOVE CKCN, IP
+	MOVE CKCN, @SP--
+	MOVE CKCN, SP
+	MOVE CKCN, IV
+	MOVE CKCN, LC[0]
+	MOVE CKCN, LC[1]
+	MOVE CKCN, @BP[OFFS++]
+	MOVE CKCN, @BP[OFFS--]
+	MOVE CKCN, OFFS
+	MOVE CKCN, DPC
+	MOVE CKCN, GR
+	MOVE CKCN, GRL
+	MOVE CKCN, BP
+	MOVE CKCN, GRS
+	MOVE CKCN, GRH
+	MOVE CKCN, GRXL
+	MOVE CKCN, FP
+	MOVE CKCN, @DP[0]	
+	MOVE CKCN, @DP[1]	
+	MOVE CKCN, @DP[0]++		
+	MOVE CKCN, @DP[1]++
+	MOVE CKCN, @DP[0]--
+	MOVE CKCN, @DP[1]--
+	MOVE A[0], #01h
+	MOVE A[0], AP
+	MOVE A[0], APC
+	MOVE A[0], PSF
+	MOVE A[0], IC
+	MOVE A[0], IMR
+	MOVE A[0], SC
+	MOVE A[0], IIR
+	MOVE A[0], CKCN
+	MOVE A[0], WDCN
+	MOVE A[0], ACC
+	MOVE A[0], A[AP]
+	MOVE A[0], IP
+	MOVE A[0], @SP--
+	MOVE A[0], SP
+	MOVE A[0], IV
+	MOVE A[0], LC[0]
+	MOVE A[0], LC[1]
+	MOVE A[0], @BP[OFFS++]
+	MOVE A[0], @BP[OFFS--]
+	MOVE A[0], OFFS
+	MOVE A[0], DPC
+	MOVE A[0], GR
+	MOVE A[0], GRL
+	MOVE A[0], BP
+	MOVE A[0], GRS
+	MOVE A[0], GRH
+	MOVE A[0], GRXL
+	MOVE A[0], FP
+	MOVE A[0], @DP[0]	
+	MOVE A[0], @DP[1]	
+	MOVE A[0], @DP[0]++		
+	MOVE A[0], @DP[1]++
+	MOVE A[0], @DP[0]--
+	MOVE A[0], @DP[1]--
+	MOVE GRH, #01h
+	MOVE GRH, AP
+	MOVE GRH, APC
+	MOVE GRH, PSF
+	MOVE GRH, IC
+	MOVE GRH, IMR
+	MOVE GRH, SC
+	MOVE GRH, IIR
+	MOVE GRH, CKCN
+	MOVE GRH, WDCN
+	MOVE GRH, A[0]		;Just Check two boundary conditions
+	MOVE GRH, A[15]   
+	MOVE GRH, ACC
+	MOVE GRH, A[AP]
+	MOVE GRH, IP
+	MOVE GRH, @SP--
+	MOVE GRH, SP
+	MOVE GRH, IV
+	MOVE GRH, LC[0]
+	MOVE GRH, LC[1]
+	MOVE GRH, @BP[OFFS++]
+	MOVE GRH, @BP[OFFS--]
+	MOVE GRH, OFFS
+	MOVE GRH, DPC
+	MOVE GRH, GR
+	MOVE GRH, GRL
+	MOVE GRH, BP
+	MOVE GRH, GRS
+	MOVE GRH, GRXL
+	MOVE GRH, FP
+	MOVE GRH, @DP[0]	
+	MOVE GRH, @DP[1]	
+	MOVE GRH, @DP[0]++		
+	MOVE GRH, @DP[1]++
+	MOVE GRH, @DP[0]--
+	MOVE GRH, @DP[1]--
diff --git a/gas/testsuite/gas/maxq10/data2.d b/gas/testsuite/gas/maxq10/data2.d
new file mode 100644
index 0000000..d0fc205
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/data2.d
@@ -0,0 +1,459 @@
+#objdump: -dw
+#name: 2nd Move operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	01 48 [ 	]*MOVE  PSF, #01h
+   2:	08 c8 [ 	]*MOVE  PSF, AP
+   4:	18 c8 [ 	]*MOVE  PSF, APC
+   6:	58 c8 [ 	]*MOVE  PSF, IC
+   8:	68 c8 [ 	]*MOVE  PSF, IMR
+   a:	88 c8 [ 	]*MOVE  PSF, SC
+   c:	b8 c8 [ 	]*MOVE  PSF, IIR
+   e:	e8 c8 [ 	]*MOVE  PSF, CKCN
+  10:	f8 c8 [ 	]*MOVE  PSF, WDCN
+  12:	09 c8 [ 	]*MOVE  PSF, A\[0\]
+  14:	f9 c8 [ 	]*MOVE  PSF, A\[15\]
+  16:	0a c8 [ 	]*MOVE  PSF, ACC
+  18:	1a c8 [ 	]*MOVE  PSF, A\[AP\]
+  1a:	0c c8 [ 	]*MOVE  PSF, IP
+  1c:	0d c8 [ 	]*MOVE  PSF, @SP\-\-
+  1e:	1d c8 [ 	]*MOVE  PSF, SP
+  20:	2d c8 [ 	]*MOVE  PSF, IV
+  22:	6d c8 [ 	]*MOVE  PSF, LC\[0\]
+  24:	7d c8 [ 	]*MOVE  PSF, LC\[1\]
+  26:	1e c8 [ 	]*MOVE  PSF, @BP\[OFFS\+\+\]
+  28:	2e c8 [ 	]*MOVE  PSF, @BP\[OFFS\-\-\]
+  2a:	3e c8 [ 	]*MOVE  PSF, OFFS
+  2c:	4e c8 [ 	]*MOVE  PSF, DPC
+  2e:	5e c8 [ 	]*MOVE  PSF, GR
+  30:	6e c8 [ 	]*MOVE  PSF, GRL
+  32:	7e c8 [ 	]*MOVE  PSF, BP
+  34:	8e c8 [ 	]*MOVE  PSF, GRS
+  36:	9e c8 [ 	]*MOVE  PSF, GRH
+  38:	ae c8 [ 	]*MOVE  PSF, GRXL
+  3a:	be c8 [ 	]*MOVE  PSF, FP
+  3c:	0f c8 [ 	]*MOVE  PSF, @DP\[0\]
+  3e:	4f c8 [ 	]*MOVE  PSF, @DP\[1\]
+  40:	1f c8 [ 	]*MOVE  PSF, @DP\[0\]\+\+
+  42:	5f c8 [ 	]*MOVE  PSF, @DP\[1\]\+\+
+  44:	2f c8 [ 	]*MOVE  PSF, @DP\[0\]\-\-
+  46:	6f c8 [ 	]*MOVE  PSF, @DP\[1\]\-\-
+  48:	01 58 [ 	]*MOVE  IC, #01h
+  4a:	08 d8 [ 	]*MOVE  IC, AP
+  4c:	18 d8 [ 	]*MOVE  IC, APC
+  4e:	48 d8 [ 	]*MOVE  IC, PSF
+  50:	68 d8 [ 	]*MOVE  IC, IMR
+  52:	88 d8 [ 	]*MOVE  IC, SC
+  54:	b8 d8 [ 	]*MOVE  IC, IIR
+  56:	e8 d8 [ 	]*MOVE  IC, CKCN
+  58:	f8 d8 [ 	]*MOVE  IC, WDCN
+  5a:	09 d8 [ 	]*MOVE  IC, A\[0\]
+  5c:	f9 d8 [ 	]*MOVE  IC, A\[15\]
+  5e:	0a d8 [ 	]*MOVE  IC, ACC
+  60:	1a d8 [ 	]*MOVE  IC, A\[AP\]
+  62:	0c d8 [ 	]*MOVE  IC, IP
+  64:	0d d8 [ 	]*MOVE  IC, @SP\-\-
+  66:	1d d8 [ 	]*MOVE  IC, SP
+  68:	2d d8 [ 	]*MOVE  IC, IV
+  6a:	6d d8 [ 	]*MOVE  IC, LC\[0\]
+  6c:	7d d8 [ 	]*MOVE  IC, LC\[1\]
+  6e:	1e d8 [ 	]*MOVE  IC, @BP\[OFFS\+\+\]
+  70:	2e d8 [ 	]*MOVE  IC, @BP\[OFFS\-\-\]
+  72:	3e d8 [ 	]*MOVE  IC, OFFS
+  74:	4e d8 [ 	]*MOVE  IC, DPC
+  76:	5e d8 [ 	]*MOVE  IC, GR
+  78:	6e d8 [ 	]*MOVE  IC, GRL
+  7a:	7e d8 [ 	]*MOVE  IC, BP
+  7c:	8e d8 [ 	]*MOVE  IC, GRS
+  7e:	9e d8 [ 	]*MOVE  IC, GRH
+  80:	ae d8 [ 	]*MOVE  IC, GRXL
+  82:	be d8 [ 	]*MOVE  IC, FP
+  84:	0f d8 [ 	]*MOVE  IC, @DP\[0\]
+  86:	4f d8 [ 	]*MOVE  IC, @DP\[1\]
+  88:	1f d8 [ 	]*MOVE  IC, @DP\[0\]\+\+
+  8a:	5f d8 [ 	]*MOVE  IC, @DP\[1\]\+\+
+  8c:	2f d8 [ 	]*MOVE  IC, @DP\[0\]\-\-
+  8e:	6f d8 [ 	]*MOVE  IC, @DP\[1\]\-\-
+  90:	01 68 [ 	]*MOVE  IMR, #01h
+  92:	08 e8 [ 	]*MOVE  IMR, AP
+  94:	18 e8 [ 	]*MOVE  IMR, APC
+  96:	48 e8 [ 	]*MOVE  IMR, PSF
+  98:	58 e8 [ 	]*MOVE  IMR, IC
+  9a:	88 e8 [ 	]*MOVE  IMR, SC
+  9c:	b8 e8 [ 	]*MOVE  IMR, IIR
+  9e:	e8 e8 [ 	]*MOVE  IMR, CKCN
+  a0:	f8 e8 [ 	]*MOVE  IMR, WDCN
+  a2:	09 e8 [ 	]*MOVE  IMR, A\[0\]
+  a4:	f9 e8 [ 	]*MOVE  IMR, A\[15\]
+  a6:	0a e8 [ 	]*MOVE  IMR, ACC
+  a8:	1a e8 [ 	]*MOVE  IMR, A\[AP\]
+  aa:	0c e8 [ 	]*MOVE  IMR, IP
+  ac:	0d e8 [ 	]*MOVE  IMR, @SP\-\-
+  ae:	1d e8 [ 	]*MOVE  IMR, SP
+  b0:	2d e8 [ 	]*MOVE  IMR, IV
+  b2:	6d e8 [ 	]*MOVE  IMR, LC\[0\]
+  b4:	7d e8 [ 	]*MOVE  IMR, LC\[1\]
+  b6:	1e e8 [ 	]*MOVE  IMR, @BP\[OFFS\+\+\]
+  b8:	2e e8 [ 	]*MOVE  IMR, @BP\[OFFS\-\-\]
+  ba:	3e e8 [ 	]*MOVE  IMR, OFFS
+  bc:	4e e8 [ 	]*MOVE  IMR, DPC
+  be:	5e e8 [ 	]*MOVE  IMR, GR
+  c0:	6e e8 [ 	]*MOVE  IMR, GRL
+  c2:	7e e8 [ 	]*MOVE  IMR, BP
+  c4:	8e e8 [ 	]*MOVE  IMR, GRS
+  c6:	9e e8 [ 	]*MOVE  IMR, GRH
+  c8:	ae e8 [ 	]*MOVE  IMR, GRXL
+  ca:	be e8 [ 	]*MOVE  IMR, FP
+  cc:	0f e8 [ 	]*MOVE  IMR, @DP\[0\]
+  ce:	4f e8 [ 	]*MOVE  IMR, @DP\[1\]
+  d0:	1f e8 [ 	]*MOVE  IMR, @DP\[0\]\+\+
+  d2:	5f e8 [ 	]*MOVE  IMR, @DP\[1\]\+\+
+  d4:	2f e8 [ 	]*MOVE  IMR, @DP\[0\]\-\-
+  d6:	6f e8 [ 	]*MOVE  IMR, @DP\[1\]\-\-
+  d8:	01 09 [ 	]*MOVE  A\[0\], #01h
+  da:	08 89 [ 	]*MOVE  A\[0\], AP
+  dc:	18 89 [ 	]*MOVE  A\[0\], APC
+  de:	48 89 [ 	]*MOVE  A\[0\], PSF
+  e0:	58 89 [ 	]*MOVE  A\[0\], IC
+  e2:	68 89 [ 	]*MOVE  A\[0\], IMR
+  e4:	88 89 [ 	]*MOVE  A\[0\], SC
+  e6:	b8 89 [ 	]*MOVE  A\[0\], IIR
+  e8:	e8 89 [ 	]*MOVE  A\[0\], CKCN
+  ea:	f8 89 [ 	]*MOVE  A\[0\], WDCN
+  ec:	0a 89 [ 	]*MOVE  A\[0\], ACC
+  ee:	1a 89 [ 	]*MOVE  A\[0\], A\[AP\]
+  f0:	0c 89 [ 	]*MOVE  A\[0\], IP
+  f2:	0d 89 [ 	]*MOVE  A\[0\], @SP\-\-
+  f4:	1d 89 [ 	]*MOVE  A\[0\], SP
+  f6:	2d 89 [ 	]*MOVE  A\[0\], IV
+  f8:	6d 89 [ 	]*MOVE  A\[0\], LC\[0\]
+  fa:	7d 89 [ 	]*MOVE  A\[0\], LC\[1\]
+  fc:	1e 89 [ 	]*MOVE  A\[0\], @BP\[OFFS\+\+\]
+  fe:	2e 89 [ 	]*MOVE  A\[0\], @BP\[OFFS\-\-\]
+ 100:	3e 89 [ 	]*MOVE  A\[0\], OFFS
+ 102:	4e 89 [ 	]*MOVE  A\[0\], DPC
+ 104:	5e 89 [ 	]*MOVE  A\[0\], GR
+ 106:	6e 89 [ 	]*MOVE  A\[0\], GRL
+ 108:	7e 89 [ 	]*MOVE  A\[0\], BP
+ 10a:	8e 89 [ 	]*MOVE  A\[0\], GRS
+ 10c:	9e 89 [ 	]*MOVE  A\[0\], GRH
+ 10e:	ae 89 [ 	]*MOVE  A\[0\], GRXL
+ 110:	be 89 [ 	]*MOVE  A\[0\], FP
+ 112:	0f 89 [ 	]*MOVE  A\[0\], @DP\[0\]
+ 114:	4f 89 [ 	]*MOVE  A\[0\], @DP\[1\]
+ 116:	1f 89 [ 	]*MOVE  A\[0\], @DP\[0\]\+\+
+ 118:	5f 89 [ 	]*MOVE  A\[0\], @DP\[1\]\+\+
+ 11a:	2f 89 [ 	]*MOVE  A\[0\], @DP\[0\]\-\-
+ 11c:	6f 89 [ 	]*MOVE  A\[0\], @DP\[1\]\-\-
+ 11e:	01 0a [ 	]*MOVE  ACC, #01h
+ 120:	08 8a [ 	]*MOVE  ACC, AP
+ 122:	18 8a [ 	]*MOVE  ACC, APC
+ 124:	48 8a [ 	]*MOVE  ACC, PSF
+ 126:	58 8a [ 	]*MOVE  ACC, IC
+ 128:	68 8a [ 	]*MOVE  ACC, IMR
+ 12a:	88 8a [ 	]*MOVE  ACC, SC
+ 12c:	b8 8a [ 	]*MOVE  ACC, IIR
+ 12e:	e8 8a [ 	]*MOVE  ACC, CKCN
+ 130:	f8 8a [ 	]*MOVE  ACC, WDCN
+ 132:	09 8a [ 	]*MOVE  ACC, A\[0\]
+ 134:	f9 8a [ 	]*MOVE  ACC, A\[15\]
+ 136:	0c 8a [ 	]*MOVE  ACC, IP
+ 138:	0d 8a [ 	]*MOVE  ACC, @SP\-\-
+ 13a:	1d 8a [ 	]*MOVE  ACC, SP
+ 13c:	2d 8a [ 	]*MOVE  ACC, IV
+ 13e:	6d 8a [ 	]*MOVE  ACC, LC\[0\]
+ 140:	7d 8a [ 	]*MOVE  ACC, LC\[1\]
+ 142:	1e 8a [ 	]*MOVE  ACC, @BP\[OFFS\+\+\]
+ 144:	2e 8a [ 	]*MOVE  ACC, @BP\[OFFS\-\-\]
+ 146:	3e 8a [ 	]*MOVE  ACC, OFFS
+ 148:	4e 8a [ 	]*MOVE  ACC, DPC
+ 14a:	5e 8a [ 	]*MOVE  ACC, GR
+ 14c:	6e 8a [ 	]*MOVE  ACC, GRL
+ 14e:	7e 8a [ 	]*MOVE  ACC, BP
+ 150:	8e 8a [ 	]*MOVE  ACC, GRS
+ 152:	9e 8a [ 	]*MOVE  ACC, GRH
+ 154:	ae 8a [ 	]*MOVE  ACC, GRXL
+ 156:	be 8a [ 	]*MOVE  ACC, FP
+ 158:	0f 8a [ 	]*MOVE  ACC, @DP\[0\]
+ 15a:	4f 8a [ 	]*MOVE  ACC, @DP\[1\]
+ 15c:	1f 8a [ 	]*MOVE  ACC, @DP\[0\]\+\+
+ 15e:	5f 8a [ 	]*MOVE  ACC, @DP\[1\]\+\+
+ 160:	2f 8a [ 	]*MOVE  ACC, @DP\[0\]\-\-
+ 162:	6f 8a [ 	]*MOVE  ACC, @DP\[1\]\-\-
+ 164:	01 0d [ 	]*MOVE  @\+\+SP, #01h
+ 166:	08 8d [ 	]*MOVE  @\+\+SP, AP
+ 168:	18 8d [ 	]*MOVE  @\+\+SP, APC
+ 16a:	48 8d [ 	]*MOVE  @\+\+SP, PSF
+ 16c:	58 8d [ 	]*MOVE  @\+\+SP, IC
+ 16e:	68 8d [ 	]*MOVE  @\+\+SP, IMR
+ 170:	88 8d [ 	]*MOVE  @\+\+SP, SC
+ 172:	b8 8d [ 	]*MOVE  @\+\+SP, IIR
+ 174:	e8 8d [ 	]*MOVE  @\+\+SP, CKCN
+ 176:	f8 8d [ 	]*MOVE  @\+\+SP, WDCN
+ 178:	09 8d [ 	]*MOVE  @\+\+SP, A\[0\]
+ 17a:	f9 8d [ 	]*MOVE  @\+\+SP, A\[15\]
+ 17c:	0a 8d [ 	]*MOVE  @\+\+SP, ACC
+ 17e:	1a 8d [ 	]*MOVE  @\+\+SP, A\[AP\]
+ 180:	0c 8d [ 	]*MOVE  @\+\+SP, IP
+ 182:	1d 8d [ 	]*MOVE  @\+\+SP, SP
+ 184:	2d 8d [ 	]*MOVE  @\+\+SP, IV
+ 186:	6d 8d [ 	]*MOVE  @\+\+SP, LC\[0\]
+ 188:	7d 8d [ 	]*MOVE  @\+\+SP, LC\[1\]
+ 18a:	1e 8d [ 	]*MOVE  @\+\+SP, @BP\[OFFS\+\+\]
+ 18c:	2e 8d [ 	]*MOVE  @\+\+SP, @BP\[OFFS\-\-\]
+ 18e:	3e 8d [ 	]*MOVE  @\+\+SP, OFFS
+ 190:	4e 8d [ 	]*MOVE  @\+\+SP, DPC
+ 192:	5e 8d [ 	]*MOVE  @\+\+SP, GR
+ 194:	6e 8d [ 	]*MOVE  @\+\+SP, GRL
+ 196:	7e 8d [ 	]*MOVE  @\+\+SP, BP
+ 198:	8e 8d [ 	]*MOVE  @\+\+SP, GRS
+ 19a:	9e 8d [ 	]*MOVE  @\+\+SP, GRH
+ 19c:	ae 8d [ 	]*MOVE  @\+\+SP, GRXL
+ 19e:	be 8d [ 	]*MOVE  @\+\+SP, FP
+ 1a0:	0f 8d [ 	]*MOVE  @\+\+SP, @DP\[0\]
+ 1a2:	4f 8d [ 	]*MOVE  @\+\+SP, @DP\[1\]
+ 1a4:	1f 8d [ 	]*MOVE  @\+\+SP, @DP\[0\]\+\+
+ 1a6:	5f 8d [ 	]*MOVE  @\+\+SP, @DP\[1\]\+\+
+ 1a8:	2f 8d [ 	]*MOVE  @\+\+SP, @DP\[0\]\-\-
+ 1aa:	6f 8d [ 	]*MOVE  @\+\+SP, @DP\[1\]\-\-
+ 1ac:	01 1d [ 	]*MOVE  SP, #01h
+ 1ae:	08 9d [ 	]*MOVE  SP, AP
+ 1b0:	18 9d [ 	]*MOVE  SP, APC
+ 1b2:	48 9d [ 	]*MOVE  SP, PSF
+ 1b4:	58 9d [ 	]*MOVE  SP, IC
+ 1b6:	68 9d [ 	]*MOVE  SP, IMR
+ 1b8:	88 9d [ 	]*MOVE  SP, SC
+ 1ba:	b8 9d [ 	]*MOVE  SP, IIR
+ 1bc:	e8 9d [ 	]*MOVE  SP, CKCN
+ 1be:	f8 9d [ 	]*MOVE  SP, WDCN
+ 1c0:	09 9d [ 	]*MOVE  SP, A\[0\]
+ 1c2:	f9 9d [ 	]*MOVE  SP, A\[15\]
+ 1c4:	0a 9d [ 	]*MOVE  SP, ACC
+ 1c6:	1a 9d [ 	]*MOVE  SP, A\[AP\]
+ 1c8:	0c 9d [ 	]*MOVE  SP, IP
+ 1ca:	2d 9d [ 	]*MOVE  SP, IV
+ 1cc:	6d 9d [ 	]*MOVE  SP, LC\[0\]
+ 1ce:	7d 9d [ 	]*MOVE  SP, LC\[1\]
+ 1d0:	1e 9d [ 	]*MOVE  SP, @BP\[OFFS\+\+\]
+ 1d2:	2e 9d [ 	]*MOVE  SP, @BP\[OFFS\-\-\]
+ 1d4:	3e 9d [ 	]*MOVE  SP, OFFS
+ 1d6:	4e 9d [ 	]*MOVE  SP, DPC
+ 1d8:	5e 9d [ 	]*MOVE  SP, GR
+ 1da:	6e 9d [ 	]*MOVE  SP, GRL
+ 1dc:	7e 9d [ 	]*MOVE  SP, BP
+ 1de:	8e 9d [ 	]*MOVE  SP, GRS
+ 1e0:	9e 9d [ 	]*MOVE  SP, GRH
+ 1e2:	ae 9d [ 	]*MOVE  SP, GRXL
+ 1e4:	be 9d [ 	]*MOVE  SP, FP
+ 1e6:	0f 9d [ 	]*MOVE  SP, @DP\[0\]
+ 1e8:	4f 9d [ 	]*MOVE  SP, @DP\[1\]
+ 1ea:	1f 9d [ 	]*MOVE  SP, @DP\[0\]\+\+
+ 1ec:	5f 9d [ 	]*MOVE  SP, @DP\[1\]\+\+
+ 1ee:	2f 9d [ 	]*MOVE  SP, @DP\[0\]\-\-
+ 1f0:	6f 9d [ 	]*MOVE  SP, @DP\[1\]\-\-
+ 1f2:	01 2d [ 	]*MOVE  IV, #01h
+ 1f4:	08 ad [ 	]*MOVE  IV, AP
+ 1f6:	18 ad [ 	]*MOVE  IV, APC
+ 1f8:	48 ad [ 	]*MOVE  IV, PSF
+ 1fa:	58 ad [ 	]*MOVE  IV, IC
+ 1fc:	68 ad [ 	]*MOVE  IV, IMR
+ 1fe:	88 ad [ 	]*MOVE  IV, SC
+ 200:	b8 ad [ 	]*MOVE  IV, IIR
+ 202:	e8 ad [ 	]*MOVE  IV, CKCN
+ 204:	f8 ad [ 	]*MOVE  IV, WDCN
+ 206:	09 ad [ 	]*MOVE  IV, A\[0\]
+ 208:	f9 ad [ 	]*MOVE  IV, A\[15\]
+ 20a:	0a ad [ 	]*MOVE  IV, ACC
+ 20c:	1a ad [ 	]*MOVE  IV, A\[AP\]
+ 20e:	0c ad [ 	]*MOVE  IV, IP
+ 210:	0d ad [ 	]*MOVE  IV, @SP\-\-
+ 212:	1d ad [ 	]*MOVE  IV, SP
+ 214:	2d ad [ 	]*MOVE  IV, IV
+ 216:	6d ad [ 	]*MOVE  IV, LC\[0\]
+ 218:	7d ad [ 	]*MOVE  IV, LC\[1\]
+ 21a:	1e ad [ 	]*MOVE  IV, @BP\[OFFS\+\+\]
+ 21c:	2e ad [ 	]*MOVE  IV, @BP\[OFFS\-\-\]
+ 21e:	3e ad [ 	]*MOVE  IV, OFFS
+ 220:	4e ad [ 	]*MOVE  IV, DPC
+ 222:	5e ad [ 	]*MOVE  IV, GR
+ 224:	6e ad [ 	]*MOVE  IV, GRL
+ 226:	7e ad [ 	]*MOVE  IV, BP
+ 228:	8e ad [ 	]*MOVE  IV, GRS
+ 22a:	9e ad [ 	]*MOVE  IV, GRH
+ 22c:	ae ad [ 	]*MOVE  IV, GRXL
+ 22e:	be ad [ 	]*MOVE  IV, FP
+ 230:	0f ad [ 	]*MOVE  IV, @DP\[0\]
+ 232:	4f ad [ 	]*MOVE  IV, @DP\[1\]
+ 234:	1f ad [ 	]*MOVE  IV, @DP\[0\]\+\+
+ 236:	5f ad [ 	]*MOVE  IV, @DP\[1\]\+\+
+ 238:	2f ad [ 	]*MOVE  IV, @DP\[0\]\-\-
+ 23a:	6f ad [ 	]*MOVE  IV, @DP\[1\]\-\-
+ 23c:	01 6d [ 	]*MOVE  LC\[0\], #01h
+ 23e:	08 ed [ 	]*MOVE  LC\[0\], AP
+ 240:	18 ed [ 	]*MOVE  LC\[0\], APC
+ 242:	48 ed [ 	]*MOVE  LC\[0\], PSF
+ 244:	58 ed [ 	]*MOVE  LC\[0\], IC
+ 246:	68 ed [ 	]*MOVE  LC\[0\], IMR
+ 248:	88 ed [ 	]*MOVE  LC\[0\], SC
+ 24a:	b8 ed [ 	]*MOVE  LC\[0\], IIR
+ 24c:	e8 ed [ 	]*MOVE  LC\[0\], CKCN
+ 24e:	f8 ed [ 	]*MOVE  LC\[0\], WDCN
+ 250:	09 ed [ 	]*MOVE  LC\[0\], A\[0\]
+ 252:	f9 ed [ 	]*MOVE  LC\[0\], A\[15\]
+ 254:	0a ed [ 	]*MOVE  LC\[0\], ACC
+ 256:	1a ed [ 	]*MOVE  LC\[0\], A\[AP\]
+ 258:	0c ed [ 	]*MOVE  LC\[0\], IP
+ 25a:	0d ed [ 	]*MOVE  LC\[0\], @SP\-\-
+ 25c:	1d ed [ 	]*MOVE  LC\[0\], SP
+ 25e:	2d ed [ 	]*MOVE  LC\[0\], IV
+ 260:	1e ed [ 	]*MOVE  LC\[0\], @BP\[OFFS\+\+\]
+ 262:	2e ed [ 	]*MOVE  LC\[0\], @BP\[OFFS\-\-\]
+ 264:	3e ed [ 	]*MOVE  LC\[0\], OFFS
+ 266:	4e ed [ 	]*MOVE  LC\[0\], DPC
+ 268:	5e ed [ 	]*MOVE  LC\[0\], GR
+ 26a:	6e ed [ 	]*MOVE  LC\[0\], GRL
+ 26c:	7e ed [ 	]*MOVE  LC\[0\], BP
+ 26e:	8e ed [ 	]*MOVE  LC\[0\], GRS
+ 270:	9e ed [ 	]*MOVE  LC\[0\], GRH
+ 272:	ae ed [ 	]*MOVE  LC\[0\], GRXL
+ 274:	be ed [ 	]*MOVE  LC\[0\], FP
+ 276:	0f ed [ 	]*MOVE  LC\[0\], @DP\[0\]
+ 278:	4f ed [ 	]*MOVE  LC\[0\], @DP\[1\]
+ 27a:	1f ed [ 	]*MOVE  LC\[0\], @DP\[0\]\+\+
+ 27c:	5f ed [ 	]*MOVE  LC\[0\], @DP\[1\]\+\+
+ 27e:	2f ed [ 	]*MOVE  LC\[0\], @DP\[0\]\-\-
+ 280:	6f ed [ 	]*MOVE  LC\[0\], @DP\[1\]\-\-
+ 282:	01 0e [ 	]*MOVE  @BP\[OFFS\], #01h
+ 284:	08 8e [ 	]*MOVE  @BP\[OFFS\], AP
+ 286:	18 8e [ 	]*MOVE  @BP\[OFFS\], APC
+ 288:	48 8e [ 	]*MOVE  @BP\[OFFS\], PSF
+ 28a:	58 8e [ 	]*MOVE  @BP\[OFFS\], IC
+ 28c:	68 8e [ 	]*MOVE  @BP\[OFFS\], IMR
+ 28e:	88 8e [ 	]*MOVE  @BP\[OFFS\], SC
+ 290:	b8 8e [ 	]*MOVE  @BP\[OFFS\], IIR
+ 292:	e8 8e [ 	]*MOVE  @BP\[OFFS\], CKCN
+ 294:	f8 8e [ 	]*MOVE  @BP\[OFFS\], WDCN
+ 296:	09 8e [ 	]*MOVE  @BP\[OFFS\], A\[0\]
+ 298:	f9 8e [ 	]*MOVE  @BP\[OFFS\], A\[15\]
+ 29a:	0a 8e [ 	]*MOVE  @BP\[OFFS\], ACC
+ 29c:	1a 8e [ 	]*MOVE  @BP\[OFFS\], A\[AP\]
+ 29e:	0c 8e [ 	]*MOVE  @BP\[OFFS\], IP
+ 2a0:	0d 8e [ 	]*MOVE  @BP\[OFFS\], @SP\-\-
+ 2a2:	1d 8e [ 	]*MOVE  @BP\[OFFS\], SP
+ 2a4:	2d 8e [ 	]*MOVE  @BP\[OFFS\], IV
+ 2a6:	6d 8e [ 	]*MOVE  @BP\[OFFS\], LC\[0\]
+ 2a8:	7d 8e [ 	]*MOVE  @BP\[OFFS\], LC\[1\]
+ 2aa:	3e 8e [ 	]*MOVE  @BP\[OFFS\], OFFS
+ 2ac:	4e 8e [ 	]*MOVE  @BP\[OFFS\], DPC
+ 2ae:	5e 8e [ 	]*MOVE  @BP\[OFFS\], GR
+ 2b0:	6e 8e [ 	]*MOVE  @BP\[OFFS\], GRL
+ 2b2:	7e 8e [ 	]*MOVE  @BP\[OFFS\], BP
+ 2b4:	8e 8e [ 	]*MOVE  @BP\[OFFS\], GRS
+ 2b6:	9e 8e [ 	]*MOVE  @BP\[OFFS\], GRH
+ 2b8:	ae 8e [ 	]*MOVE  @BP\[OFFS\], GRXL
+ 2ba:	be 8e [ 	]*MOVE  @BP\[OFFS\], FP
+ 2bc:	0f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[0\]
+ 2be:	4f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[1\]
+ 2c0:	1f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[0\]\+\+
+ 2c2:	5f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[1\]\+\+
+ 2c4:	2f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[0\]\-\-
+ 2c6:	6f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[1\]\-\-
+ 2c8:	01 1e [ 	]*MOVE  @BP\[\+\+OFFS\], #01h
+ 2ca:	08 9e [ 	]*MOVE  @BP\[\+\+OFFS\], AP
+ 2cc:	18 9e [ 	]*MOVE  @BP\[\+\+OFFS\], APC
+ 2ce:	48 9e [ 	]*MOVE  @BP\[\+\+OFFS\], PSF
+ 2d0:	58 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IC
+ 2d2:	68 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IMR
+ 2d4:	88 9e [ 	]*MOVE  @BP\[\+\+OFFS\], SC
+ 2d6:	b8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IIR
+ 2d8:	e8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], CKCN
+ 2da:	f8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], WDCN
+ 2dc:	09 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[0\]
+ 2de:	f9 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[15\]
+ 2e0:	0a 9e [ 	]*MOVE  @BP\[\+\+OFFS\], ACC
+ 2e2:	1a 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[AP\]
+ 2e4:	0c 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IP
+ 2e6:	1d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], SP
+ 2e8:	2d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IV
+ 2ea:	6d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], LC\[0\]
+ 2ec:	7d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], LC\[1\]
+ 2ee:	3e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], OFFS
+ 2f0:	4e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], DPC
+ 2f2:	5e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GR
+ 2f4:	6e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRL
+ 2f6:	7e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], BP
+ 2f8:	8e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRS
+ 2fa:	9e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRH
+ 2fc:	ae 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRXL
+ 2fe:	be 9e [ 	]*MOVE  @BP\[\+\+OFFS\], FP
+ 300:	0f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]
+ 302:	4f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]
+ 304:	2f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]\-\-
+ 306:	6f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]\-\-
+ 308:	01 2e [ 	]*MOVE  @BP\[\-\-OFFS\], #01h
+ 30a:	08 ae [ 	]*MOVE  @BP\[\-\-OFFS\], AP
+ 30c:	18 ae [ 	]*MOVE  @BP\[\-\-OFFS\], APC
+ 30e:	48 ae [ 	]*MOVE  @BP\[\-\-OFFS\], PSF
+ 310:	58 ae [ 	]*MOVE  @BP\[\-\-OFFS\], IC
+ 312:	68 ae [ 	]*MOVE  @BP\[\-\-OFFS\], IMR
+ 314:	88 ae [ 	]*MOVE  @BP\[\-\-OFFS\], SC
+ 316:	b8 ae [ 	]*MOVE  @BP\[\-\-OFFS\], IIR
+ 318:	e8 ae [ 	]*MOVE  @BP\[\-\-OFFS\], CKCN
+ 31a:	f8 ae [ 	]*MOVE  @BP\[\-\-OFFS\], WDCN
+ 31c:	09 ae [ 	]*MOVE  @BP\[\-\-OFFS\], A\[0\]
+ 31e:	f9 ae [ 	]*MOVE  @BP\[\-\-OFFS\], A\[15\]
+ 320:	0a ae [ 	]*MOVE  @BP\[\-\-OFFS\], ACC
+ 322:	1a ae [ 	]*MOVE  @BP\[\-\-OFFS\], A\[AP\]
+ 324:	0c ae [ 	]*MOVE  @BP\[\-\-OFFS\], IP
+ 326:	1d ae [ 	]*MOVE  @BP\[\-\-OFFS\], SP
+ 328:	2d ae [ 	]*MOVE  @BP\[\-\-OFFS\], IV
+ 32a:	6d ae [ 	]*MOVE  @BP\[\-\-OFFS\], LC\[0\]
+ 32c:	7d ae [ 	]*MOVE  @BP\[\-\-OFFS\], LC\[1\]
+ 32e:	3e ae [ 	]*MOVE  @BP\[\-\-OFFS\], OFFS
+ 330:	4e ae [ 	]*MOVE  @BP\[\-\-OFFS\], DPC
+ 332:	5e ae [ 	]*MOVE  @BP\[\-\-OFFS\], GR
+ 334:	6e ae [ 	]*MOVE  @BP\[\-\-OFFS\], GRL
+ 336:	7e ae [ 	]*MOVE  @BP\[\-\-OFFS\], BP
+ 338:	8e ae [ 	]*MOVE  @BP\[\-\-OFFS\], GRS
+ 33a:	9e ae [ 	]*MOVE  @BP\[\-\-OFFS\], GRH
+ 33c:	ae ae [ 	]*MOVE  @BP\[\-\-OFFS\], GRXL
+ 33e:	be ae [ 	]*MOVE  @BP\[\-\-OFFS\], FP
+ 340:	0f ae [ 	]*MOVE  @BP\[\-\-OFFS\], @DP\[0\]
+ 342:	4f ae [ 	]*MOVE  @BP\[\-\-OFFS\], @DP\[1\]
+ 344:	01 3e [ 	]*MOVE  OFFS, #01h
+ 346:	08 be [ 	]*MOVE  OFFS, AP
+ 348:	18 be [ 	]*MOVE  OFFS, APC
+ 34a:	48 be [ 	]*MOVE  OFFS, PSF
+ 34c:	58 be [ 	]*MOVE  OFFS, IC
+ 34e:	68 be [ 	]*MOVE  OFFS, IMR
+ 350:	88 be [ 	]*MOVE  OFFS, SC
+ 352:	b8 be [ 	]*MOVE  OFFS, IIR
+ 354:	e8 be [ 	]*MOVE  OFFS, CKCN
+ 356:	f8 be [ 	]*MOVE  OFFS, WDCN
+ 358:	09 be [ 	]*MOVE  OFFS, A\[0\]
+ 35a:	f9 be [ 	]*MOVE  OFFS, A\[15\]
+ 35c:	0a be [ 	]*MOVE  OFFS, ACC
+ 35e:	1a be [ 	]*MOVE  OFFS, A\[AP\]
+ 360:	0c be [ 	]*MOVE  OFFS, IP
+ 362:	0d be [ 	]*MOVE  OFFS, @SP\-\-
+ 364:	1d be [ 	]*MOVE  OFFS, SP
+ 366:	2d be [ 	]*MOVE  OFFS, IV
+ 368:	6d be [ 	]*MOVE  OFFS, LC\[0\]
+ 36a:	7d be [ 	]*MOVE  OFFS, LC\[1\]
+ 36c:	4e be [ 	]*MOVE  OFFS, DPC
+ 36e:	5e be [ 	]*MOVE  OFFS, GR
+ 370:	6e be [ 	]*MOVE  OFFS, GRL
+ 372:	7e be [ 	]*MOVE  OFFS, BP
+ 374:	8e be [ 	]*MOVE  OFFS, GRS
+ 376:	9e be [ 	]*MOVE  OFFS, GRH
+ 378:	ae be [ 	]*MOVE  OFFS, GRXL
+ 37a:	be be [ 	]*MOVE  OFFS, FP
+ 37c:	0f be [ 	]*MOVE  OFFS, @DP\[0\]
+ 37e:	4f be [ 	]*MOVE  OFFS, @DP\[1\]
+ 380:	1f be [ 	]*MOVE  OFFS, @DP\[0\]\+\+
+ 382:	5f be [ 	]*MOVE  OFFS, @DP\[1\]\+\+
+ 384:	2f be [ 	]*MOVE  OFFS, @DP\[0\]\-\-
+ 386:	6f be [ 	]*MOVE  OFFS, @DP\[1\]\-\-
diff --git a/gas/testsuite/gas/maxq10/data2.s b/gas/testsuite/gas/maxq10/data2.s
new file mode 100644
index 0000000..94cc70b
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/data2.s
@@ -0,0 +1,455 @@
+;# data.s	
+;# checks all the data transfer instructions
+foo:
+	MOVE PSF, #01h
+	MOVE PSF, AP
+	MOVE PSF, APC
+	MOVE PSF, IC
+	MOVE PSF, IMR
+	MOVE PSF, SC
+	MOVE PSF, IIR
+	MOVE PSF, CKCN
+	MOVE PSF, WDCN
+	MOVE PSF, A[0]		;Just Check two boundary conditions
+	MOVE PSF, A[15]   
+	MOVE PSF, ACC
+	MOVE PSF, A[AP]
+	MOVE PSF, IP
+	MOVE PSF, @SP--
+	MOVE PSF, SP
+	MOVE PSF, IV
+	MOVE PSF, LC[0]
+	MOVE PSF, LC[1]
+	MOVE PSF, @BP[OFFS++]
+	MOVE PSF, @BP[OFFS--]
+	MOVE PSF, OFFS
+	MOVE PSF, DPC
+	MOVE PSF, GR
+	MOVE PSF, GRL
+	MOVE PSF, BP
+	MOVE PSF, GRS
+	MOVE PSF, GRH
+	MOVE PSF, GRXL
+	MOVE PSF, FP
+	MOVE PSF, @DP[0]	
+	MOVE PSF, @DP[1]	
+	MOVE PSF, @DP[0]++		
+	MOVE PSF, @DP[1]++
+	MOVE PSF, @DP[0]--
+	MOVE PSF, @DP[1]--
+	MOVE IC, #01h
+	MOVE IC, AP
+	MOVE IC, APC
+	MOVE IC, PSF
+	MOVE IC, IMR
+	MOVE IC, SC
+	MOVE IC, IIR
+	MOVE IC, CKCN
+	MOVE IC, WDCN
+	MOVE IC, A[0]		;Just Check two boundary conditions
+	MOVE IC, A[15]   
+	MOVE IC, ACC
+	MOVE IC, A[AP]
+	MOVE IC, IP
+	MOVE IC, @SP--
+	MOVE IC, SP
+	MOVE IC, IV
+	MOVE IC, LC[0]
+	MOVE IC, LC[1]
+	MOVE IC, @BP[OFFS++]
+	MOVE IC, @BP[OFFS--]
+	MOVE IC, OFFS
+	MOVE IC, DPC
+	MOVE IC, GR
+	MOVE IC, GRL
+	MOVE IC, BP
+	MOVE IC, GRS
+	MOVE IC, GRH
+	MOVE IC, GRXL
+	MOVE IC, FP
+	MOVE IC, @DP[0]	
+	MOVE IC, @DP[1]	
+	MOVE IC, @DP[0]++		
+	MOVE IC, @DP[1]++
+	MOVE IC, @DP[0]--
+	MOVE IC, @DP[1]--
+	MOVE IMR, #01h
+	MOVE IMR, AP
+	MOVE IMR, APC
+	MOVE IMR, PSF
+	MOVE IMR, IC
+	MOVE IMR, SC
+	MOVE IMR, IIR
+	MOVE IMR, CKCN
+	MOVE IMR, WDCN
+	MOVE IMR, A[0]		;Just Check two boundary conditions
+	MOVE IMR, A[15]   
+	MOVE IMR, ACC
+	MOVE IMR, A[AP]
+	MOVE IMR, IP
+	MOVE IMR, @SP--
+	MOVE IMR, SP
+	MOVE IMR, IV
+	MOVE IMR, LC[0]
+	MOVE IMR, LC[1]
+	MOVE IMR, @BP[OFFS++]
+	MOVE IMR, @BP[OFFS--]
+	MOVE IMR, OFFS
+	MOVE IMR, DPC
+	MOVE IMR, GR
+	MOVE IMR, GRL
+	MOVE IMR, BP
+	MOVE IMR, GRS
+	MOVE IMR, GRH
+	MOVE IMR, GRXL
+	MOVE IMR, FP
+	MOVE IMR, @DP[0]	
+	MOVE IMR, @DP[1]	
+	MOVE IMR, @DP[0]++		
+	MOVE IMR, @DP[1]++
+	MOVE IMR, @DP[0]--
+	MOVE IMR, @DP[1]--
+	MOVE A[0], #01h
+	MOVE A[0], AP
+	MOVE A[0], APC
+	MOVE A[0], PSF
+	MOVE A[0], IC
+	MOVE A[0], IMR
+	MOVE A[0], SC
+	MOVE A[0], IIR
+	MOVE A[0], CKCN
+	MOVE A[0], WDCN
+	MOVE A[0], ACC
+	MOVE A[0], A[AP]
+	MOVE A[0], IP
+	MOVE A[0], @SP--
+	MOVE A[0], SP
+	MOVE A[0], IV
+	MOVE A[0], LC[0]
+	MOVE A[0], LC[1]
+	MOVE A[0], @BP[OFFS++]
+	MOVE A[0], @BP[OFFS--]
+	MOVE A[0], OFFS
+	MOVE A[0], DPC
+	MOVE A[0], GR
+	MOVE A[0], GRL
+	MOVE A[0], BP
+	MOVE A[0], GRS
+	MOVE A[0], GRH
+	MOVE A[0], GRXL
+	MOVE A[0], FP
+	MOVE A[0], @DP[0]	
+	MOVE A[0], @DP[1]	
+	MOVE A[0], @DP[0]++		
+	MOVE A[0], @DP[1]++
+	MOVE A[0], @DP[0]--
+	MOVE A[0], @DP[1]--
+	MOVE ACC, #01h
+	MOVE ACC, AP
+	MOVE ACC, APC
+	MOVE ACC, PSF
+	MOVE ACC, IC
+	MOVE ACC, IMR
+	MOVE ACC, SC
+	MOVE ACC, IIR
+	MOVE ACC, CKCN
+	MOVE ACC, WDCN
+	MOVE ACC, A[0]		;Just Check two boundary conditions
+	MOVE ACC, A[15]   
+	MOVE ACC, IP
+	MOVE ACC, @SP--
+	MOVE ACC, SP
+	MOVE ACC, IV
+	MOVE ACC, LC[0]
+	MOVE ACC, LC[1]
+	MOVE ACC, @BP[OFFS++]
+	MOVE ACC, @BP[OFFS--]
+	MOVE ACC, OFFS
+	MOVE ACC, DPC
+	MOVE ACC, GR
+	MOVE ACC, GRL
+	MOVE ACC, BP
+	MOVE ACC, GRS
+	MOVE ACC, GRH
+	MOVE ACC, GRXL
+	MOVE ACC, FP
+	MOVE ACC, @DP[0]	
+	MOVE ACC, @DP[1]	
+	MOVE ACC, @DP[0]++		
+	MOVE ACC, @DP[1]++
+	MOVE ACC, @DP[0]--
+	MOVE ACC, @DP[1]--
+	MOVE @++SP, #01h
+	MOVE @++SP, AP
+	MOVE @++SP, APC
+	MOVE @++SP, PSF
+	MOVE @++SP, IC
+	MOVE @++SP, IMR
+	MOVE @++SP, SC
+	MOVE @++SP, IIR
+	MOVE @++SP, CKCN
+	MOVE @++SP, WDCN
+	MOVE @++SP, A[0]		;Just Check two boundary conditions
+	MOVE @++SP, A[15]   
+	MOVE @++SP, ACC
+	MOVE @++SP, A[AP]
+	MOVE @++SP, IP
+	MOVE @++SP, SP
+	MOVE @++SP, IV
+	MOVE @++SP, LC[0]
+	MOVE @++SP, LC[1]
+	MOVE @++SP, @BP[OFFS++]
+	MOVE @++SP, @BP[OFFS--]
+	MOVE @++SP, OFFS
+	MOVE @++SP, DPC
+	MOVE @++SP, GR
+	MOVE @++SP, GRL
+	MOVE @++SP, BP
+	MOVE @++SP, GRS
+	MOVE @++SP, GRH
+	MOVE @++SP, GRXL
+	MOVE @++SP, FP
+	MOVE @++SP, @DP[0]	
+	MOVE @++SP, @DP[1]	
+	MOVE @++SP, @DP[0]++		
+	MOVE @++SP, @DP[1]++
+	MOVE @++SP, @DP[0]--
+	MOVE @++SP, @DP[1]--
+	MOVE SP, #01h
+	MOVE SP, AP
+	MOVE SP, APC
+	MOVE SP, PSF
+	MOVE SP, IC
+	MOVE SP, IMR
+	MOVE SP, SC
+	MOVE SP, IIR
+	MOVE SP, CKCN
+	MOVE SP, WDCN
+	MOVE SP, A[0]		;Just Check two boundary conditions
+	MOVE SP, A[15]   
+	MOVE SP, ACC
+	MOVE SP, A[AP]
+	MOVE SP, IP
+	MOVE SP, IV
+	MOVE SP, LC[0]
+	MOVE SP, LC[1]
+	MOVE SP, @BP[OFFS++]
+	MOVE SP, @BP[OFFS--]
+	MOVE SP, OFFS
+	MOVE SP, DPC
+	MOVE SP, GR
+	MOVE SP, GRL
+	MOVE SP, BP
+	MOVE SP, GRS
+	MOVE SP, GRH
+	MOVE SP, GRXL
+	MOVE SP, FP
+	MOVE SP, @DP[0]	
+	MOVE SP, @DP[1]	
+	MOVE SP, @DP[0]++		
+	MOVE SP, @DP[1]++
+	MOVE SP, @DP[0]--
+	MOVE SP, @DP[1]--
+	MOVE IV, #01h
+	MOVE IV, AP
+	MOVE IV, APC
+	MOVE IV, PSF
+	MOVE IV, IC
+	MOVE IV, IMR
+	MOVE IV, SC
+	MOVE IV, IIR
+	MOVE IV, CKCN
+	MOVE IV, WDCN
+	MOVE IV, A[0]		;Just Check two boundary conditions
+	MOVE IV, A[15]   
+	MOVE IV, ACC
+	MOVE IV, A[AP]
+	MOVE IV, IP
+	MOVE IV, @SP--
+	MOVE IV, SP
+	MOVE IV, IV
+	MOVE IV, LC[0]
+	MOVE IV, LC[1]
+	MOVE IV, @BP[OFFS++]
+	MOVE IV, @BP[OFFS--]
+	MOVE IV, OFFS
+	MOVE IV, DPC
+	MOVE IV, GR
+	MOVE IV, GRL
+	MOVE IV, BP
+	MOVE IV, GRS
+	MOVE IV, GRH
+	MOVE IV, GRXL
+	MOVE IV, FP
+	MOVE IV, @DP[0]	
+	MOVE IV, @DP[1]	
+	MOVE IV, @DP[0]++		
+	MOVE IV, @DP[1]++
+	MOVE IV, @DP[0]--
+	MOVE IV, @DP[1]--
+	MOVE LC[0], #01h
+	MOVE LC[0], AP
+	MOVE LC[0], APC
+	MOVE LC[0], PSF
+	MOVE LC[0], IC
+	MOVE LC[0], IMR
+	MOVE LC[0], SC
+	MOVE LC[0], IIR
+	MOVE LC[0], CKCN
+	MOVE LC[0], WDCN
+	MOVE LC[0], A[0]		;Just Check two boundary conditions
+	MOVE LC[0], A[15]   
+	MOVE LC[0], ACC
+	MOVE LC[0], A[AP]
+	MOVE LC[0], IP
+	MOVE LC[0], @SP--
+	MOVE LC[0], SP
+	MOVE LC[0], IV
+	MOVE LC[0], @BP[OFFS++]
+	MOVE LC[0], @BP[OFFS--]
+	MOVE LC[0], OFFS
+	MOVE LC[0], DPC
+	MOVE LC[0], GR
+	MOVE LC[0], GRL
+	MOVE LC[0], BP
+	MOVE LC[0], GRS
+	MOVE LC[0], GRH
+	MOVE LC[0], GRXL
+	MOVE LC[0], FP
+	MOVE LC[0], @DP[0]	
+	MOVE LC[0], @DP[1]	
+	MOVE LC[0], @DP[0]++		
+	MOVE LC[0], @DP[1]++
+	MOVE LC[0], @DP[0]--
+	MOVE LC[0], @DP[1]--
+	MOVE @BP[OFFS], #01h
+	MOVE @BP[OFFS], AP
+	MOVE @BP[OFFS], APC
+	MOVE @BP[OFFS], PSF
+	MOVE @BP[OFFS], IC
+	MOVE @BP[OFFS], IMR
+	MOVE @BP[OFFS], SC
+	MOVE @BP[OFFS], IIR
+	MOVE @BP[OFFS], CKCN
+	MOVE @BP[OFFS], WDCN
+	MOVE @BP[OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[OFFS], A[15]   
+	MOVE @BP[OFFS], ACC
+	MOVE @BP[OFFS], A[AP]
+	MOVE @BP[OFFS], IP
+	MOVE @BP[OFFS], @SP--
+	MOVE @BP[OFFS], SP
+	MOVE @BP[OFFS], IV
+	MOVE @BP[OFFS], LC[0]
+	MOVE @BP[OFFS], LC[1]
+	MOVE @BP[OFFS], OFFS
+	MOVE @BP[OFFS], DPC
+	MOVE @BP[OFFS], GR
+	MOVE @BP[OFFS], GRL
+	MOVE @BP[OFFS], BP
+	MOVE @BP[OFFS], GRS
+	MOVE @BP[OFFS], GRH
+	MOVE @BP[OFFS], GRXL
+	MOVE @BP[OFFS], FP
+	MOVE @BP[OFFS], @DP[0]	
+	MOVE @BP[OFFS], @DP[1]	
+	MOVE @BP[OFFS], @DP[0]++		
+	MOVE @BP[OFFS], @DP[1]++
+	MOVE @BP[OFFS], @DP[0]--
+	MOVE @BP[OFFS], @DP[1]--
+	MOVE @BP[++OFFS], #01h
+	MOVE @BP[++OFFS], AP
+	MOVE @BP[++OFFS], APC
+	MOVE @BP[++OFFS], PSF
+	MOVE @BP[++OFFS], IC
+	MOVE @BP[++OFFS], IMR
+	MOVE @BP[++OFFS], SC
+	MOVE @BP[++OFFS], IIR
+	MOVE @BP[++OFFS], CKCN
+	MOVE @BP[++OFFS], WDCN
+	MOVE @BP[++OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[++OFFS], A[15]   
+	MOVE @BP[++OFFS], ACC
+	MOVE @BP[++OFFS], A[AP]
+	MOVE @BP[++OFFS], IP
+	MOVE @BP[++OFFS], SP
+	MOVE @BP[++OFFS], IV
+	MOVE @BP[++OFFS], LC[0]
+	MOVE @BP[++OFFS], LC[1]
+	MOVE @BP[++OFFS], OFFS
+	MOVE @BP[++OFFS], DPC
+	MOVE @BP[++OFFS], GR
+	MOVE @BP[++OFFS], GRL
+	MOVE @BP[++OFFS], BP
+	MOVE @BP[++OFFS], GRS
+	MOVE @BP[++OFFS], GRH
+	MOVE @BP[++OFFS], GRXL
+	MOVE @BP[++OFFS], FP
+	MOVE @BP[++OFFS], @DP[0]	
+	MOVE @BP[++OFFS], @DP[1]	
+	MOVE @BP[++OFFS], @DP[0]--
+	MOVE @BP[++OFFS], @DP[1]--
+	MOVE @BP[--OFFS], #01h
+	MOVE @BP[--OFFS], AP
+	MOVE @BP[--OFFS], APC
+	MOVE @BP[--OFFS], PSF
+	MOVE @BP[--OFFS], IC
+	MOVE @BP[--OFFS], IMR
+	MOVE @BP[--OFFS], SC
+	MOVE @BP[--OFFS], IIR
+	MOVE @BP[--OFFS], CKCN
+	MOVE @BP[--OFFS], WDCN
+	MOVE @BP[--OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[--OFFS], A[15]   
+	MOVE @BP[--OFFS], ACC
+	MOVE @BP[--OFFS], A[AP]
+	MOVE @BP[--OFFS], IP
+	MOVE @BP[--OFFS], SP
+	MOVE @BP[--OFFS], IV
+	MOVE @BP[--OFFS], LC[0]
+	MOVE @BP[--OFFS], LC[1]
+	MOVE @BP[--OFFS], OFFS
+	MOVE @BP[--OFFS], DPC
+	MOVE @BP[--OFFS], GR
+	MOVE @BP[--OFFS], GRL
+	MOVE @BP[--OFFS], BP
+	MOVE @BP[--OFFS], GRS
+	MOVE @BP[--OFFS], GRH
+	MOVE @BP[--OFFS], GRXL
+	MOVE @BP[--OFFS], FP
+	MOVE @BP[--OFFS], @DP[0]	
+	MOVE @BP[--OFFS], @DP[1]	
+	MOVE OFFS, #01h
+	MOVE OFFS, AP
+	MOVE OFFS, APC
+	MOVE OFFS, PSF
+	MOVE OFFS, IC
+	MOVE OFFS, IMR
+	MOVE OFFS, SC
+	MOVE OFFS, IIR
+	MOVE OFFS, CKCN
+	MOVE OFFS, WDCN
+	MOVE OFFS, A[0]		;Just Check two boundary conditions
+	MOVE OFFS, A[15]   
+	MOVE OFFS, ACC
+	MOVE OFFS, A[AP]
+	MOVE OFFS, IP
+	MOVE OFFS, @SP--
+	MOVE OFFS, SP
+	MOVE OFFS, IV
+	MOVE OFFS, LC[0]
+	MOVE OFFS, LC[1]
+	MOVE OFFS, DPC
+	MOVE OFFS, GR
+	MOVE OFFS, GRL
+	MOVE OFFS, BP
+	MOVE OFFS, GRS
+	MOVE OFFS, GRH
+	MOVE OFFS, GRXL
+	MOVE OFFS, FP
+	MOVE OFFS, @DP[0]	
+	MOVE OFFS, @DP[1]	
+	MOVE OFFS, @DP[0]++		
+	MOVE OFFS, @DP[1]++
+	MOVE OFFS, @DP[0]--
+	MOVE OFFS, @DP[1]--
diff --git a/gas/testsuite/gas/maxq10/data3.d b/gas/testsuite/gas/maxq10/data3.d
new file mode 100644
index 0000000..2b6dad4
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/data3.d
@@ -0,0 +1,491 @@
+#objdump:  -dw
+#name: 3rd Move operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	01 4e [ 	]*MOVE  DPC, #01h
+   2:	08 ce [ 	]*MOVE  DPC, AP
+   4:	18 ce [ 	]*MOVE  DPC, APC
+   6:	48 ce [ 	]*MOVE  DPC, PSF
+   8:	58 ce [ 	]*MOVE  DPC, IC
+   a:	68 ce [ 	]*MOVE  DPC, IMR
+   c:	88 ce [ 	]*MOVE  DPC, SC
+   e:	b8 ce [ 	]*MOVE  DPC, IIR
+  10:	e8 ce [ 	]*MOVE  DPC, CKCN
+  12:	f8 ce [ 	]*MOVE  DPC, WDCN
+  14:	09 ce [ 	]*MOVE  DPC, A\[0\]
+  16:	f9 ce [ 	]*MOVE  DPC, A\[15\]
+  18:	0a ce [ 	]*MOVE  DPC, ACC
+  1a:	1a ce [ 	]*MOVE  DPC, A\[AP\]
+  1c:	0c ce [ 	]*MOVE  DPC, IP
+  1e:	0d ce [ 	]*MOVE  DPC, @SP\-\-
+  20:	1d ce [ 	]*MOVE  DPC, SP
+  22:	2d ce [ 	]*MOVE  DPC, IV
+  24:	6d ce [ 	]*MOVE  DPC, LC\[0\]
+  26:	7d ce [ 	]*MOVE  DPC, LC\[1\]
+  28:	1e ce [ 	]*MOVE  DPC, @BP\[OFFS\+\+\]
+  2a:	2e ce [ 	]*MOVE  DPC, @BP\[OFFS\-\-\]
+  2c:	3e ce [ 	]*MOVE  DPC, OFFS
+  2e:	5e ce [ 	]*MOVE  DPC, GR
+  30:	6e ce [ 	]*MOVE  DPC, GRL
+  32:	7e ce [ 	]*MOVE  DPC, BP
+  34:	8e ce [ 	]*MOVE  DPC, GRS
+  36:	9e ce [ 	]*MOVE  DPC, GRH
+  38:	ae ce [ 	]*MOVE  DPC, GRXL
+  3a:	be ce [ 	]*MOVE  DPC, FP
+  3c:	0f ce [ 	]*MOVE  DPC, @DP\[0\]
+  3e:	4f ce [ 	]*MOVE  DPC, @DP\[1\]
+  40:	1f ce [ 	]*MOVE  DPC, @DP\[0\]\+\+
+  42:	5f ce [ 	]*MOVE  DPC, @DP\[1\]\+\+
+  44:	2f ce [ 	]*MOVE  DPC, @DP\[0\]\-\-
+  46:	6f ce [ 	]*MOVE  DPC, @DP\[1\]\-\-
+  48:	01 5e [ 	]*MOVE  GR, #01h
+  4a:	08 de [ 	]*MOVE  GR, AP
+  4c:	18 de [ 	]*MOVE  GR, APC
+  4e:	48 de [ 	]*MOVE  GR, PSF
+  50:	58 de [ 	]*MOVE  GR, IC
+  52:	68 de [ 	]*MOVE  GR, IMR
+  54:	88 de [ 	]*MOVE  GR, SC
+  56:	b8 de [ 	]*MOVE  GR, IIR
+  58:	e8 de [ 	]*MOVE  GR, CKCN
+  5a:	f8 de [ 	]*MOVE  GR, WDCN
+  5c:	09 de [ 	]*MOVE  GR, A\[0\]
+  5e:	f9 de [ 	]*MOVE  GR, A\[15\]
+  60:	0a de [ 	]*MOVE  GR, ACC
+  62:	1a de [ 	]*MOVE  GR, A\[AP\]
+  64:	0c de [ 	]*MOVE  GR, IP
+  66:	0d de [ 	]*MOVE  GR, @SP\-\-
+  68:	1d de [ 	]*MOVE  GR, SP
+  6a:	2d de [ 	]*MOVE  GR, IV
+  6c:	6d de [ 	]*MOVE  GR, LC\[0\]
+  6e:	7d de [ 	]*MOVE  GR, LC\[1\]
+  70:	1e de [ 	]*MOVE  GR, @BP\[OFFS\+\+\]
+  72:	2e de [ 	]*MOVE  GR, @BP\[OFFS\-\-\]
+  74:	3e de [ 	]*MOVE  GR, OFFS
+  76:	4e de [ 	]*MOVE  GR, DPC
+  78:	6e de [ 	]*MOVE  GR, GRL
+  7a:	7e de [ 	]*MOVE  GR, BP
+  7c:	8e de [ 	]*MOVE  GR, GRS
+  7e:	9e de [ 	]*MOVE  GR, GRH
+  80:	ae de [ 	]*MOVE  GR, GRXL
+  82:	be de [ 	]*MOVE  GR, FP
+  84:	0f de [ 	]*MOVE  GR, @DP\[0\]
+  86:	4f de [ 	]*MOVE  GR, @DP\[1\]
+  88:	1f de [ 	]*MOVE  GR, @DP\[0\]\+\+
+  8a:	5f de [ 	]*MOVE  GR, @DP\[1\]\+\+
+  8c:	2f de [ 	]*MOVE  GR, @DP\[0\]\-\-
+  8e:	6f de [ 	]*MOVE  GR, @DP\[1\]\-\-
+  90:	01 6e [ 	]*MOVE  GRL, #01h
+  92:	08 ee [ 	]*MOVE  GRL, AP
+  94:	18 ee [ 	]*MOVE  GRL, APC
+  96:	48 ee [ 	]*MOVE  GRL, PSF
+  98:	58 ee [ 	]*MOVE  GRL, IC
+  9a:	68 ee [ 	]*MOVE  GRL, IMR
+  9c:	88 ee [ 	]*MOVE  GRL, SC
+  9e:	b8 ee [ 	]*MOVE  GRL, IIR
+  a0:	e8 ee [ 	]*MOVE  GRL, CKCN
+  a2:	f8 ee [ 	]*MOVE  GRL, WDCN
+  a4:	09 ee [ 	]*MOVE  GRL, A\[0\]
+  a6:	f9 ee [ 	]*MOVE  GRL, A\[15\]
+  a8:	0a ee [ 	]*MOVE  GRL, ACC
+  aa:	1a ee [ 	]*MOVE  GRL, A\[AP\]
+  ac:	0c ee [ 	]*MOVE  GRL, IP
+  ae:	0d ee [ 	]*MOVE  GRL, @SP\-\-
+  b0:	1d ee [ 	]*MOVE  GRL, SP
+  b2:	2d ee [ 	]*MOVE  GRL, IV
+  b4:	6d ee [ 	]*MOVE  GRL, LC\[0\]
+  b6:	7d ee [ 	]*MOVE  GRL, LC\[1\]
+  b8:	1e ee [ 	]*MOVE  GRL, @BP\[OFFS\+\+\]
+  ba:	2e ee [ 	]*MOVE  GRL, @BP\[OFFS\-\-\]
+  bc:	3e ee [ 	]*MOVE  GRL, OFFS
+  be:	4e ee [ 	]*MOVE  GRL, DPC
+  c0:	5e ee [ 	]*MOVE  GRL, GR
+  c2:	7e ee [ 	]*MOVE  GRL, BP
+  c4:	8e ee [ 	]*MOVE  GRL, GRS
+  c6:	9e ee [ 	]*MOVE  GRL, GRH
+  c8:	ae ee [ 	]*MOVE  GRL, GRXL
+  ca:	be ee [ 	]*MOVE  GRL, FP
+  cc:	0f ee [ 	]*MOVE  GRL, @DP\[0\]
+  ce:	4f ee [ 	]*MOVE  GRL, @DP\[1\]
+  d0:	1f ee [ 	]*MOVE  GRL, @DP\[0\]\+\+
+  d2:	5f ee [ 	]*MOVE  GRL, @DP\[1\]\+\+
+  d4:	2f ee [ 	]*MOVE  GRL, @DP\[0\]\-\-
+  d6:	6f ee [ 	]*MOVE  GRL, @DP\[1\]\-\-
+  d8:	01 7e [ 	]*MOVE  BP, #01h
+  da:	08 fe [ 	]*MOVE  BP, AP
+  dc:	18 fe [ 	]*MOVE  BP, APC
+  de:	48 fe [ 	]*MOVE  BP, PSF
+  e0:	58 fe [ 	]*MOVE  BP, IC
+  e2:	68 fe [ 	]*MOVE  BP, IMR
+  e4:	88 fe [ 	]*MOVE  BP, SC
+  e6:	b8 fe [ 	]*MOVE  BP, IIR
+  e8:	e8 fe [ 	]*MOVE  BP, CKCN
+  ea:	f8 fe [ 	]*MOVE  BP, WDCN
+  ec:	09 fe [ 	]*MOVE  BP, A\[0\]
+  ee:	f9 fe [ 	]*MOVE  BP, A\[15\]
+  f0:	0a fe [ 	]*MOVE  BP, ACC
+  f2:	1a fe [ 	]*MOVE  BP, A\[AP\]
+  f4:	0c fe [ 	]*MOVE  BP, IP
+  f6:	0d fe [ 	]*MOVE  BP, @SP\-\-
+  f8:	1d fe [ 	]*MOVE  BP, SP
+  fa:	2d fe [ 	]*MOVE  BP, IV
+  fc:	6d fe [ 	]*MOVE  BP, LC\[0\]
+  fe:	7d fe [ 	]*MOVE  BP, LC\[1\]
+ 100:	1e fe [ 	]*MOVE  BP, @BP\[OFFS\+\+\]
+ 102:	2e fe [ 	]*MOVE  BP, @BP\[OFFS\-\-\]
+ 104:	3e fe [ 	]*MOVE  BP, OFFS
+ 106:	4e fe [ 	]*MOVE  BP, DPC
+ 108:	5e fe [ 	]*MOVE  BP, GR
+ 10a:	6e fe [ 	]*MOVE  BP, GRL
+ 10c:	8e fe [ 	]*MOVE  BP, GRS
+ 10e:	9e fe [ 	]*MOVE  BP, GRH
+ 110:	ae fe [ 	]*MOVE  BP, GRXL
+ 112:	be fe [ 	]*MOVE  BP, FP
+ 114:	0f fe [ 	]*MOVE  BP, @DP\[0\]
+ 116:	4f fe [ 	]*MOVE  BP, @DP\[1\]
+ 118:	1f fe [ 	]*MOVE  BP, @DP\[0\]\+\+
+ 11a:	5f fe [ 	]*MOVE  BP, @DP\[1\]\+\+
+ 11c:	2f fe [ 	]*MOVE  BP, @DP\[0\]\-\-
+ 11e:	6f fe [ 	]*MOVE  BP, @DP\[1\]\-\-
+ 120:	01 0f [ 	]*MOVE  @DP\[0\], #01h
+ 122:	08 8f [ 	]*MOVE  @DP\[0\], AP
+ 124:	18 8f [ 	]*MOVE  @DP\[0\], APC
+ 126:	48 8f [ 	]*MOVE  @DP\[0\], PSF
+ 128:	58 8f [ 	]*MOVE  @DP\[0\], IC
+ 12a:	68 8f [ 	]*MOVE  @DP\[0\], IMR
+ 12c:	88 8f [ 	]*MOVE  @DP\[0\], SC
+ 12e:	b8 8f [ 	]*MOVE  @DP\[0\], IIR
+ 130:	e8 8f [ 	]*MOVE  @DP\[0\], CKCN
+ 132:	f8 8f [ 	]*MOVE  @DP\[0\], WDCN
+ 134:	09 8f [ 	]*MOVE  @DP\[0\], A\[0\]
+ 136:	f9 8f [ 	]*MOVE  @DP\[0\], A\[15\]
+ 138:	0a 8f [ 	]*MOVE  @DP\[0\], ACC
+ 13a:	1a 8f [ 	]*MOVE  @DP\[0\], A\[AP\]
+ 13c:	0c 8f [ 	]*MOVE  @DP\[0\], IP
+ 13e:	0d 8f [ 	]*MOVE  @DP\[0\], @SP\-\-
+ 140:	1d 8f [ 	]*MOVE  @DP\[0\], SP
+ 142:	2d 8f [ 	]*MOVE  @DP\[0\], IV
+ 144:	6d 8f [ 	]*MOVE  @DP\[0\], LC\[0\]
+ 146:	7d 8f [ 	]*MOVE  @DP\[0\], LC\[1\]
+ 148:	1e 8f [ 	]*MOVE  @DP\[0\], @BP\[OFFS\+\+\]
+ 14a:	2e 8f [ 	]*MOVE  @DP\[0\], @BP\[OFFS\-\-\]
+ 14c:	3e 8f [ 	]*MOVE  @DP\[0\], OFFS
+ 14e:	4e 8f [ 	]*MOVE  @DP\[0\], DPC
+ 150:	5e 8f [ 	]*MOVE  @DP\[0\], GR
+ 152:	6e 8f [ 	]*MOVE  @DP\[0\], GRL
+ 154:	7e 8f [ 	]*MOVE  @DP\[0\], BP
+ 156:	8e 8f [ 	]*MOVE  @DP\[0\], GRS
+ 158:	9e 8f [ 	]*MOVE  @DP\[0\], GRH
+ 15a:	ae 8f [ 	]*MOVE  @DP\[0\], GRXL
+ 15c:	be 8f [ 	]*MOVE  @DP\[0\], FP
+ 15e:	01 1f [ 	]*MOVE  @\+\+DP\[0\], #01h
+ 160:	08 9f [ 	]*MOVE  @\+\+DP\[0\], AP
+ 162:	18 9f [ 	]*MOVE  @\+\+DP\[0\], APC
+ 164:	48 9f [ 	]*MOVE  @\+\+DP\[0\], PSF
+ 166:	58 9f [ 	]*MOVE  @\+\+DP\[0\], IC
+ 168:	68 9f [ 	]*MOVE  @\+\+DP\[0\], IMR
+ 16a:	88 9f [ 	]*MOVE  @\+\+DP\[0\], SC
+ 16c:	b8 9f [ 	]*MOVE  @\+\+DP\[0\], IIR
+ 16e:	e8 9f [ 	]*MOVE  @\+\+DP\[0\], CKCN
+ 170:	f8 9f [ 	]*MOVE  @\+\+DP\[0\], WDCN
+ 172:	09 9f [ 	]*MOVE  @\+\+DP\[0\], A\[0\]
+ 174:	f9 9f [ 	]*MOVE  @\+\+DP\[0\], A\[15\]
+ 176:	0a 9f [ 	]*MOVE  @\+\+DP\[0\], ACC
+ 178:	1a 9f [ 	]*MOVE  @\+\+DP\[0\], A\[AP\]
+ 17a:	0c 9f [ 	]*MOVE  @\+\+DP\[0\], IP
+ 17c:	0d 9f [ 	]*MOVE  @\+\+DP\[0\], @SP\-\-
+ 17e:	1d 9f [ 	]*MOVE  @\+\+DP\[0\], SP
+ 180:	2d 9f [ 	]*MOVE  @\+\+DP\[0\], IV
+ 182:	6d 9f [ 	]*MOVE  @\+\+DP\[0\], LC\[0\]
+ 184:	7d 9f [ 	]*MOVE  @\+\+DP\[0\], LC\[1\]
+ 186:	1e 9f [ 	]*MOVE  @\+\+DP\[0\], @BP\[OFFS\+\+\]
+ 188:	2e 9f [ 	]*MOVE  @\+\+DP\[0\], @BP\[OFFS\-\-\]
+ 18a:	3e 9f [ 	]*MOVE  @\+\+DP\[0\], OFFS
+ 18c:	4e 9f [ 	]*MOVE  @\+\+DP\[0\], DPC
+ 18e:	5e 9f [ 	]*MOVE  @\+\+DP\[0\], GR
+ 190:	6e 9f [ 	]*MOVE  @\+\+DP\[0\], GRL
+ 192:	7e 9f [ 	]*MOVE  @\+\+DP\[0\], BP
+ 194:	8e 9f [ 	]*MOVE  @\+\+DP\[0\], GRS
+ 196:	9e 9f [ 	]*MOVE  @\+\+DP\[0\], GRH
+ 198:	ae 9f [ 	]*MOVE  @\+\+DP\[0\], GRXL
+ 19a:	be 9f [ 	]*MOVE  @\+\+DP\[0\], FP
+ 19c:	01 2f [ 	]*MOVE  @\-\-DP\[0\], #01h
+ 19e:	08 af [ 	]*MOVE  @\-\-DP\[0\], AP
+ 1a0:	18 af [ 	]*MOVE  @\-\-DP\[0\], APC
+ 1a2:	48 af [ 	]*MOVE  @\-\-DP\[0\], PSF
+ 1a4:	58 af [ 	]*MOVE  @\-\-DP\[0\], IC
+ 1a6:	68 af [ 	]*MOVE  @\-\-DP\[0\], IMR
+ 1a8:	88 af [ 	]*MOVE  @\-\-DP\[0\], SC
+ 1aa:	b8 af [ 	]*MOVE  @\-\-DP\[0\], IIR
+ 1ac:	e8 af [ 	]*MOVE  @\-\-DP\[0\], CKCN
+ 1ae:	f8 af [ 	]*MOVE  @\-\-DP\[0\], WDCN
+ 1b0:	09 af [ 	]*MOVE  @\-\-DP\[0\], A\[0\]
+ 1b2:	f9 af [ 	]*MOVE  @\-\-DP\[0\], A\[15\]
+ 1b4:	0a af [ 	]*MOVE  @\-\-DP\[0\], ACC
+ 1b6:	1a af [ 	]*MOVE  @\-\-DP\[0\], A\[AP\]
+ 1b8:	0c af [ 	]*MOVE  @\-\-DP\[0\], IP
+ 1ba:	0d af [ 	]*MOVE  @\-\-DP\[0\], @SP\-\-
+ 1bc:	1d af [ 	]*MOVE  @\-\-DP\[0\], SP
+ 1be:	2d af [ 	]*MOVE  @\-\-DP\[0\], IV
+ 1c0:	6d af [ 	]*MOVE  @\-\-DP\[0\], LC\[0\]
+ 1c2:	7d af [ 	]*MOVE  @\-\-DP\[0\], LC\[1\]
+ 1c4:	1e af [ 	]*MOVE  @\-\-DP\[0\], @BP\[OFFS\+\+\]
+ 1c6:	2e af [ 	]*MOVE  @\-\-DP\[0\], @BP\[OFFS\-\-\]
+ 1c8:	3e af [ 	]*MOVE  @\-\-DP\[0\], OFFS
+ 1ca:	4e af [ 	]*MOVE  @\-\-DP\[0\], DPC
+ 1cc:	5e af [ 	]*MOVE  @\-\-DP\[0\], GR
+ 1ce:	6e af [ 	]*MOVE  @\-\-DP\[0\], GRL
+ 1d0:	7e af [ 	]*MOVE  @\-\-DP\[0\], BP
+ 1d2:	8e af [ 	]*MOVE  @\-\-DP\[0\], GRS
+ 1d4:	9e af [ 	]*MOVE  @\-\-DP\[0\], GRH
+ 1d6:	ae af [ 	]*MOVE  @\-\-DP\[0\], GRXL
+ 1d8:	be af [ 	]*MOVE  @\-\-DP\[0\], FP
+ 1da:	01 3f [ 	]*MOVE  DP\[0\], #01h
+ 1dc:	08 bf [ 	]*MOVE  DP\[0\], AP
+ 1de:	18 bf [ 	]*MOVE  DP\[0\], APC
+ 1e0:	48 bf [ 	]*MOVE  DP\[0\], PSF
+ 1e2:	58 bf [ 	]*MOVE  DP\[0\], IC
+ 1e4:	68 bf [ 	]*MOVE  DP\[0\], IMR
+ 1e6:	88 bf [ 	]*MOVE  DP\[0\], SC
+ 1e8:	b8 bf [ 	]*MOVE  DP\[0\], IIR
+ 1ea:	e8 bf [ 	]*MOVE  DP\[0\], CKCN
+ 1ec:	f8 bf [ 	]*MOVE  DP\[0\], WDCN
+ 1ee:	09 bf [ 	]*MOVE  DP\[0\], A\[0\]
+ 1f0:	f9 bf [ 	]*MOVE  DP\[0\], A\[15\]
+ 1f2:	0a bf [ 	]*MOVE  DP\[0\], ACC
+ 1f4:	1a bf [ 	]*MOVE  DP\[0\], A\[AP\]
+ 1f6:	0c bf [ 	]*MOVE  DP\[0\], IP
+ 1f8:	0d bf [ 	]*MOVE  DP\[0\], @SP\-\-
+ 1fa:	1d bf [ 	]*MOVE  DP\[0\], SP
+ 1fc:	2d bf [ 	]*MOVE  DP\[0\], IV
+ 1fe:	6d bf [ 	]*MOVE  DP\[0\], LC\[0\]
+ 200:	7d bf [ 	]*MOVE  DP\[0\], LC\[1\]
+ 202:	1e bf [ 	]*MOVE  DP\[0\], @BP\[OFFS\+\+\]
+ 204:	2e bf [ 	]*MOVE  DP\[0\], @BP\[OFFS\-\-\]
+ 206:	3e bf [ 	]*MOVE  DP\[0\], OFFS
+ 208:	4e bf [ 	]*MOVE  DP\[0\], DPC
+ 20a:	5e bf [ 	]*MOVE  DP\[0\], GR
+ 20c:	6e bf [ 	]*MOVE  DP\[0\], GRL
+ 20e:	7e bf [ 	]*MOVE  DP\[0\], BP
+ 210:	8e bf [ 	]*MOVE  DP\[0\], GRS
+ 212:	9e bf [ 	]*MOVE  DP\[0\], GRH
+ 214:	ae bf [ 	]*MOVE  DP\[0\], GRXL
+ 216:	be bf [ 	]*MOVE  DP\[0\], FP
+ 218:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 21a:	01 08 [ 	]*MOVE  AP, #01h
+ 21c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 21e:	08 88 [ 	]*MOVE  AP, AP
+ 220:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 222:	18 88 [ 	]*MOVE  AP, APC
+ 224:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 226:	48 88 [ 	]*MOVE  AP, PSF
+ 228:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 22a:	58 88 [ 	]*MOVE  AP, IC
+ 22c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 22e:	68 88 [ 	]*MOVE  AP, IMR
+ 230:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 232:	b8 88 [ 	]*MOVE  AP, IIR
+ 234:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 236:	e8 88 [ 	]*MOVE  AP, CKCN
+ 238:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 23a:	f8 88 [ 	]*MOVE  AP, WDCN
+ 23c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 23e:	09 88 [ 	]*MOVE  AP, A\[0\]
+ 240:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 242:	f9 88 [ 	]*MOVE  AP, A\[15\]
+ 244:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 246:	0a 88 [ 	]*MOVE  AP, ACC
+ 248:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 24a:	1a 88 [ 	]*MOVE  AP, A\[AP\]
+ 24c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 24e:	0c 88 [ 	]*MOVE  AP, IP
+ 250:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 252:	0d 88 [ 	]*MOVE  AP, @SP\-\-
+ 254:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 256:	1d 88 [ 	]*MOVE  AP, SP
+ 258:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 25a:	2d 88 [ 	]*MOVE  AP, IV
+ 25c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 25e:	6d 88 [ 	]*MOVE  AP, LC\[0\]
+ 260:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 262:	7d 88 [ 	]*MOVE  AP, LC\[1\]
+ 264:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 266:	1e 88 [ 	]*MOVE  AP, @BP\[OFFS\+\+\]
+ 268:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 26a:	2e 88 [ 	]*MOVE  AP, @BP\[OFFS\-\-\]
+ 26c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 26e:	3e 88 [ 	]*MOVE  AP, OFFS
+ 270:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 272:	4e 88 [ 	]*MOVE  AP, DPC
+ 274:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 276:	5e 88 [ 	]*MOVE  AP, GR
+ 278:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 27a:	6e 88 [ 	]*MOVE  AP, GRL
+ 27c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 27e:	7e 88 [ 	]*MOVE  AP, BP
+ 280:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 282:	8e 88 [ 	]*MOVE  AP, GRS
+ 284:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 286:	9e 88 [ 	]*MOVE  AP, GRH
+ 288:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 28a:	ae 88 [ 	]*MOVE  AP, GRXL
+ 28c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 28e:	be 88 [ 	]*MOVE  AP, FP
+ 290:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 292:	0f 88 [ 	]*MOVE  AP, @DP\[0\]
+ 294:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 296:	4f 88 [ 	]*MOVE  AP, @DP\[1\]
+ 298:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 29a:	1f 88 [ 	]*MOVE  AP, @DP\[0\]\+\+
+ 29c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 29e:	5f 88 [ 	]*MOVE  AP, @DP\[1\]\+\+
+ 2a0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2a2:	2f 88 [ 	]*MOVE  AP, @DP\[0\]\-\-
+ 2a4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2a6:	6f 88 [ 	]*MOVE  AP, @DP\[1\]\-\-
+ 2a8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2aa:	01 68 [ 	]*MOVE  IMR, #01h
+ 2ac:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ae:	08 e8 [ 	]*MOVE  IMR, AP
+ 2b0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2b2:	18 e8 [ 	]*MOVE  IMR, APC
+ 2b4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2b6:	48 e8 [ 	]*MOVE  IMR, PSF
+ 2b8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ba:	58 e8 [ 	]*MOVE  IMR, IC
+ 2bc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2be:	68 e8 [ 	]*MOVE  IMR, IMR
+ 2c0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2c2:	88 e8 [ 	]*MOVE  IMR, SC
+ 2c4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2c6:	b8 e8 [ 	]*MOVE  IMR, IIR
+ 2c8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ca:	f8 e8 [ 	]*MOVE  IMR, WDCN
+ 2cc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ce:	09 e8 [ 	]*MOVE  IMR, A\[0\]
+ 2d0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2d2:	f9 e8 [ 	]*MOVE  IMR, A\[15\]
+ 2d4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2d6:	0a e8 [ 	]*MOVE  IMR, ACC
+ 2d8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2da:	1a e8 [ 	]*MOVE  IMR, A\[AP\]
+ 2dc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2de:	0c e8 [ 	]*MOVE  IMR, IP
+ 2e0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2e2:	0d e8 [ 	]*MOVE  IMR, @SP\-\-
+ 2e4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2e6:	1d e8 [ 	]*MOVE  IMR, SP
+ 2e8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ea:	2d e8 [ 	]*MOVE  IMR, IV
+ 2ec:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ee:	6d e8 [ 	]*MOVE  IMR, LC\[0\]
+ 2f0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2f2:	7d e8 [ 	]*MOVE  IMR, LC\[1\]
+ 2f4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2f6:	1e e8 [ 	]*MOVE  IMR, @BP\[OFFS\+\+\]
+ 2f8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2fa:	2e e8 [ 	]*MOVE  IMR, @BP\[OFFS\-\-\]
+ 2fc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2fe:	3e e8 [ 	]*MOVE  IMR, OFFS
+ 300:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 302:	4e e8 [ 	]*MOVE  IMR, DPC
+ 304:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 306:	5e e8 [ 	]*MOVE  IMR, GR
+ 308:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 30a:	6e e8 [ 	]*MOVE  IMR, GRL
+ 30c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 30e:	7e e8 [ 	]*MOVE  IMR, BP
+ 310:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 312:	8e e8 [ 	]*MOVE  IMR, GRS
+ 314:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 316:	9e e8 [ 	]*MOVE  IMR, GRH
+ 318:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 31a:	ae e8 [ 	]*MOVE  IMR, GRXL
+ 31c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 31e:	be e8 [ 	]*MOVE  IMR, FP
+ 320:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 322:	0f e8 [ 	]*MOVE  IMR, @DP\[0\]
+ 324:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 326:	4f e8 [ 	]*MOVE  IMR, @DP\[1\]
+ 328:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 32a:	1f e8 [ 	]*MOVE  IMR, @DP\[0\]\+\+
+ 32c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 32e:	5f e8 [ 	]*MOVE  IMR, @DP\[1\]\+\+
+ 330:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 332:	2f e8 [ 	]*MOVE  IMR, @DP\[0\]\-\-
+ 334:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 336:	6f e8 [ 	]*MOVE  IMR, @DP\[1\]\-\-
+ 338:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 33a:	01 1e [ 	]*MOVE  @BP\[\+\+OFFS\], #01h
+ 33c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 33e:	08 9e [ 	]*MOVE  @BP\[\+\+OFFS\], AP
+ 340:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 342:	18 9e [ 	]*MOVE  @BP\[\+\+OFFS\], APC
+ 344:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 346:	48 9e [ 	]*MOVE  @BP\[\+\+OFFS\], PSF
+ 348:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 34a:	58 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IC
+ 34c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 34e:	68 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IMR
+ 350:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 352:	88 9e [ 	]*MOVE  @BP\[\+\+OFFS\], SC
+ 354:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 356:	b8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IIR
+ 358:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 35a:	e8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], CKCN
+ 35c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 35e:	f8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], WDCN
+ 360:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 362:	09 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[0\]
+ 364:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 366:	f9 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[15\]
+ 368:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 36a:	0a 9e [ 	]*MOVE  @BP\[\+\+OFFS\], ACC
+ 36c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 36e:	1a 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[AP\]
+ 370:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 372:	0c 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IP
+ 374:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 376:	0d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @SP\-\-
+ 378:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 37a:	1d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], SP
+ 37c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 37e:	2d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IV
+ 380:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 382:	6d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], LC\[0\]
+ 384:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 386:	7d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], LC\[1\]
+ 388:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 38a:	1e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @BP\[OFFS\+\+\]
+ 38c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 38e:	2e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @BP\[OFFS\-\-\]
+ 390:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 392:	3e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], OFFS
+ 394:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 396:	4e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], DPC
+ 398:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 39a:	5e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GR
+ 39c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 39e:	6e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRL
+ 3a0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3a2:	7e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], BP
+ 3a4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3a6:	8e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRS
+ 3a8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3aa:	ae 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRXL
+ 3ac:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3ae:	be 9e [ 	]*MOVE  @BP\[\+\+OFFS\], FP
+ 3b0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3b2:	0f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]
+ 3b4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3b6:	4f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]
+ 3b8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3ba:	1f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]\+\+
+ 3bc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3be:	5f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]\+\+
+ 3c0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3c2:	2f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]\-\-
+ 3c4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3c6:	6f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]\-\-
diff --git a/gas/testsuite/gas/maxq10/data3.s b/gas/testsuite/gas/maxq10/data3.s
new file mode 100644
index 0000000..c3cdbbb
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/data3.s
@@ -0,0 +1,379 @@
+;# data.s	
+;# checks all the data transfer instructions
+foo:
+	MOVE DPC, #01h
+	MOVE DPC, AP
+	MOVE DPC, APC
+	MOVE DPC, PSF
+	MOVE DPC, IC
+	MOVE DPC, IMR
+	MOVE DPC, SC
+	MOVE DPC, IIR
+	MOVE DPC, CKCN
+	MOVE DPC, WDCN
+	MOVE DPC, A[0]		;Just Check two boundary conditions
+	MOVE DPC, A[15]   
+	MOVE DPC, ACC
+	MOVE DPC, A[AP]
+	MOVE DPC, IP
+	MOVE DPC, @SP--
+	MOVE DPC, SP
+	MOVE DPC, IV
+	MOVE DPC, LC[0]
+	MOVE DPC, LC[1]
+	MOVE DPC, @BP[OFFS++]
+	MOVE DPC, @BP[OFFS--]
+	MOVE DPC, OFFS
+	MOVE DPC, GR
+	MOVE DPC, GRL
+	MOVE DPC, BP
+	MOVE DPC, GRS
+	MOVE DPC, GRH
+	MOVE DPC, GRXL
+	MOVE DPC, FP
+	MOVE DPC, @DP[0]	
+	MOVE DPC, @DP[1]	
+	MOVE DPC, @DP[0]++		
+	MOVE DPC, @DP[1]++
+	MOVE DPC, @DP[0]--
+	MOVE DPC, @DP[1]--
+	MOVE GR, #01h
+	MOVE GR, AP
+	MOVE GR, APC
+	MOVE GR, PSF
+	MOVE GR, IC
+	MOVE GR, IMR
+	MOVE GR, SC
+	MOVE GR, IIR
+	MOVE GR, CKCN
+	MOVE GR, WDCN
+	MOVE GR, A[0]		;Just Check two boundary conditions
+	MOVE GR, A[15]   
+	MOVE GR, ACC
+	MOVE GR, A[AP]
+	MOVE GR, IP
+	MOVE GR, @SP--
+	MOVE GR, SP
+	MOVE GR, IV
+	MOVE GR, LC[0]
+	MOVE GR, LC[1]
+	MOVE GR, @BP[OFFS++]
+	MOVE GR, @BP[OFFS--]
+	MOVE GR, OFFS
+	MOVE GR, DPC
+	MOVE GR, GRL
+	MOVE GR, BP
+	MOVE GR, GRS
+	MOVE GR, GRH
+	MOVE GR, GRXL
+	MOVE GR, FP
+	MOVE GR, @DP[0]	
+	MOVE GR, @DP[1]	
+	MOVE GR, @DP[0]++		
+	MOVE GR, @DP[1]++
+	MOVE GR, @DP[0]--
+	MOVE GR, @DP[1]--
+	MOVE GRL, #01h
+	MOVE GRL, AP
+	MOVE GRL, APC
+	MOVE GRL, PSF
+	MOVE GRL, IC
+	MOVE GRL, IMR
+	MOVE GRL, SC
+	MOVE GRL, IIR
+	MOVE GRL, CKCN
+	MOVE GRL, WDCN
+	MOVE GRL, A[0]		;Just Check two boundary conditions
+	MOVE GRL, A[15]   
+	MOVE GRL, ACC
+	MOVE GRL, A[AP]
+	MOVE GRL, IP
+	MOVE GRL, @SP--
+	MOVE GRL, SP
+	MOVE GRL, IV
+	MOVE GRL, LC[0]
+	MOVE GRL, LC[1]
+	MOVE GRL, @BP[OFFS++]
+	MOVE GRL, @BP[OFFS--]
+	MOVE GRL, OFFS
+	MOVE GRL, DPC
+	MOVE GRL, GR
+	MOVE GRL, BP
+	MOVE GRL, GRS
+	MOVE GRL, GRH
+	MOVE GRL, GRXL
+	MOVE GRL, FP
+	MOVE GRL, @DP[0]	
+	MOVE GRL, @DP[1]	
+	MOVE GRL, @DP[0]++		
+	MOVE GRL, @DP[1]++
+	MOVE GRL, @DP[0]--
+	MOVE GRL, @DP[1]--
+	MOVE BP, #01h
+	MOVE BP, AP
+	MOVE BP, APC
+	MOVE BP, PSF
+	MOVE BP, IC
+	MOVE BP, IMR
+	MOVE BP, SC
+	MOVE BP, IIR
+	MOVE BP, CKCN
+	MOVE BP, WDCN
+	MOVE BP, A[0]		;Just Check two boundary conditions
+	MOVE BP, A[15]   
+	MOVE BP, ACC
+	MOVE BP, A[AP]
+	MOVE BP, IP
+	MOVE BP, @SP--
+	MOVE BP, SP
+	MOVE BP, IV
+	MOVE BP, LC[0]
+	MOVE BP, LC[1]
+	MOVE BP, @BP[OFFS++]
+	MOVE BP, @BP[OFFS--]
+	MOVE BP, OFFS
+	MOVE BP, DPC
+	MOVE BP, GR
+	MOVE BP, GRL
+	MOVE BP, GRS
+	MOVE BP, GRH
+	MOVE BP, GRXL
+	MOVE BP, FP
+	MOVE BP, @DP[0]	
+	MOVE BP, @DP[1]	
+	MOVE BP, @DP[0]++		
+	MOVE BP, @DP[1]++
+	MOVE BP, @DP[0]--
+	MOVE BP, @DP[1]--
+	MOVE @DP[0], #01h
+	MOVE @DP[0], AP
+	MOVE @DP[0], APC
+	MOVE @DP[0], PSF
+	MOVE @DP[0], IC
+	MOVE @DP[0], IMR
+	MOVE @DP[0], SC
+	MOVE @DP[0], IIR
+	MOVE @DP[0], CKCN
+	MOVE @DP[0], WDCN
+	MOVE @DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @DP[0], A[15]   
+	MOVE @DP[0], ACC
+	MOVE @DP[0], A[AP]
+	MOVE @DP[0], IP
+	MOVE @DP[0], @SP--
+	MOVE @DP[0], SP
+	MOVE @DP[0], IV
+	MOVE @DP[0], LC[0]
+	MOVE @DP[0], LC[1]
+	MOVE @DP[0], @BP[OFFS++]
+	MOVE @DP[0], @BP[OFFS--]
+	MOVE @DP[0], OFFS
+	MOVE @DP[0], DPC
+	MOVE @DP[0], GR
+	MOVE @DP[0], GRL
+	MOVE @DP[0], BP
+	MOVE @DP[0], GRS
+	MOVE @DP[0], GRH
+	MOVE @DP[0], GRXL
+	MOVE @DP[0], FP
+	MOVE @++DP[0], #01h
+	MOVE @++DP[0], AP
+	MOVE @++DP[0], APC
+	MOVE @++DP[0], PSF
+	MOVE @++DP[0], IC
+	MOVE @++DP[0], IMR
+	MOVE @++DP[0], SC
+	MOVE @++DP[0], IIR
+	MOVE @++DP[0], CKCN
+	MOVE @++DP[0], WDCN
+	MOVE @++DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @++DP[0], A[15]   
+	MOVE @++DP[0], ACC
+	MOVE @++DP[0], A[AP]
+	MOVE @++DP[0], IP
+	MOVE @++DP[0], @SP--
+	MOVE @++DP[0], SP
+	MOVE @++DP[0], IV
+	MOVE @++DP[0], LC[0]
+	MOVE @++DP[0], LC[1]
+	MOVE @++DP[0], @BP[OFFS++]
+	MOVE @++DP[0], @BP[OFFS--]
+	MOVE @++DP[0], OFFS
+	MOVE @++DP[0], DPC
+	MOVE @++DP[0], GR
+	MOVE @++DP[0], GRL
+	MOVE @++DP[0], BP
+	MOVE @++DP[0], GRS
+	MOVE @++DP[0], GRH
+	MOVE @++DP[0], GRXL
+	MOVE @++DP[0], FP
+	MOVE @--DP[0], #01h
+	MOVE @--DP[0], AP
+	MOVE @--DP[0], APC
+	MOVE @--DP[0], PSF
+	MOVE @--DP[0], IC
+	MOVE @--DP[0], IMR
+	MOVE @--DP[0], SC
+	MOVE @--DP[0], IIR
+	MOVE @--DP[0], CKCN
+	MOVE @--DP[0], WDCN
+	MOVE @--DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @--DP[0], A[15]   
+	MOVE @--DP[0], ACC
+	MOVE @--DP[0], A[AP]
+	MOVE @--DP[0], IP
+	MOVE @--DP[0], @SP--
+	MOVE @--DP[0], SP
+	MOVE @--DP[0], IV
+	MOVE @--DP[0], LC[0]
+	MOVE @--DP[0], LC[1]
+	MOVE @--DP[0], @BP[OFFS++]
+	MOVE @--DP[0], @BP[OFFS--]
+	MOVE @--DP[0], OFFS
+	MOVE @--DP[0], DPC
+	MOVE @--DP[0], GR
+	MOVE @--DP[0], GRL
+	MOVE @--DP[0], BP
+	MOVE @--DP[0], GRS
+	MOVE @--DP[0], GRH
+	MOVE @--DP[0], GRXL
+	MOVE @--DP[0], FP
+	MOVE DP[0], #01h
+	MOVE DP[0], AP
+	MOVE DP[0], APC
+	MOVE DP[0], PSF
+	MOVE DP[0], IC
+	MOVE DP[0], IMR
+	MOVE DP[0], SC
+	MOVE DP[0], IIR
+	MOVE DP[0], CKCN
+	MOVE DP[0], WDCN
+	MOVE DP[0], A[0]		;Just Check two boundary conditions
+	MOVE DP[0], A[15]   
+	MOVE DP[0], ACC
+	MOVE DP[0], A[AP]
+	MOVE DP[0], IP
+	MOVE DP[0], @SP--
+	MOVE DP[0], SP
+	MOVE DP[0], IV
+	MOVE DP[0], LC[0]
+	MOVE DP[0], LC[1]
+	MOVE DP[0], @BP[OFFS++]
+	MOVE DP[0], @BP[OFFS--]
+	MOVE DP[0], OFFS
+	MOVE DP[0], DPC
+	MOVE DP[0], GR
+	MOVE DP[0], GRL
+	MOVE DP[0], BP
+	MOVE DP[0], GRS
+	MOVE DP[0], GRH
+	MOVE DP[0], GRXL
+	MOVE DP[0], FP
+	MOVE SC, #01h
+	MOVE SC, AP
+	MOVE SC, APC
+	MOVE SC, PSF
+	MOVE SC, IC
+	MOVE SC, IMR
+	MOVE SC, IIR
+	MOVE SC, CKCN
+	MOVE SC, WDCN
+	MOVE SC, A[0]		;Just Check two boundary conditions
+	MOVE SC, A[15]   
+	MOVE SC, ACC
+	MOVE SC, A[AP]
+	MOVE SC, IP
+	MOVE SC, @SP--
+	MOVE SC, SP
+	MOVE SC, IV
+	MOVE SC, LC[0]
+	MOVE SC, LC[1]
+	MOVE SC, @BP[OFFS++]
+	MOVE SC, @BP[OFFS--]
+	MOVE SC, OFFS
+	MOVE SC, DPC
+	MOVE SC, GR
+	MOVE SC, GRL
+	MOVE SC, BP
+	MOVE SC, GRS
+	MOVE SC, GRH
+	MOVE SC, GRXL
+	MOVE SC, FP
+	MOVE SC, @DP[0]	
+	MOVE SC, @DP[1]	
+	MOVE SC, @DP[0]++		
+	MOVE SC, @DP[1]++
+	MOVE SC, @DP[0]--
+	MOVE SC, @DP[1]--
+	MOVE CKCN, #01h
+	MOVE CKCN, AP
+	MOVE CKCN, APC
+	MOVE CKCN, PSF
+	MOVE CKCN, IC
+	MOVE CKCN, IMR
+	MOVE CKCN, SC
+	MOVE CKCN, IIR
+	MOVE CKCN, WDCN
+	MOVE CKCN, A[0]		;Just Check two boundary conditions
+	MOVE CKCN, A[15]   
+	MOVE CKCN, ACC
+	MOVE CKCN, A[AP]
+	MOVE CKCN, IP
+	MOVE CKCN, @SP--
+	MOVE CKCN, SP
+	MOVE CKCN, IV
+	MOVE CKCN, LC[0]
+	MOVE CKCN, LC[1]
+	MOVE CKCN, @BP[OFFS++]
+	MOVE CKCN, @BP[OFFS--]
+	MOVE CKCN, OFFS
+	MOVE CKCN, DPC
+	MOVE CKCN, GR
+	MOVE CKCN, GRL
+	MOVE CKCN, BP
+	MOVE CKCN, GRS
+	MOVE CKCN, GRH
+	MOVE CKCN, GRXL
+	MOVE CKCN, FP
+	MOVE CKCN, @DP[0]	
+	MOVE CKCN, @DP[1]	
+	MOVE CKCN, @DP[0]++		
+	MOVE CKCN, @DP[1]++
+	MOVE CKCN, @DP[0]--
+	MOVE CKCN, @DP[1]--
+	MOVE GRH, #01h
+	MOVE GRH, AP
+	MOVE GRH, APC
+	MOVE GRH, PSF
+	MOVE GRH, IC
+	MOVE GRH, IMR
+	MOVE GRH, SC
+	MOVE GRH, IIR
+	MOVE GRH, CKCN
+	MOVE GRH, WDCN
+	MOVE GRH, A[0]		;Just Check two boundary conditions
+	MOVE GRH, A[15]   
+	MOVE GRH, ACC
+	MOVE GRH, A[AP]
+	MOVE GRH, IP
+	MOVE GRH, @SP--
+	MOVE GRH, SP
+	MOVE GRH, IV
+	MOVE GRH, LC[0]
+	MOVE GRH, LC[1]
+	MOVE GRH, @BP[OFFS++]
+	MOVE GRH, @BP[OFFS--]
+	MOVE GRH, OFFS
+	MOVE GRH, DPC
+	MOVE GRH, GR
+	MOVE GRH, GRL
+	MOVE GRH, BP
+	MOVE GRH, GRS
+	MOVE GRH, GRXL
+	MOVE GRH, FP
+	MOVE GRH, @DP[0]	
+	MOVE GRH, @DP[1]	
+	MOVE GRH, @DP[0]++		
+	MOVE GRH, @DP[1]++
+	MOVE GRH, @DP[0]--
+	MOVE GRH, @DP[1]--
diff --git a/gas/testsuite/gas/maxq10/err.s b/gas/testsuite/gas/maxq10/err.s
new file mode 100644
index 0000000..916da73
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/err.s
@@ -0,0 +1,31 @@
+# err.s
+# some data pointer error conditions
+
+#NOT YET INCLUDED 
+
+
+
+	MOVE @++DP[0], @DP[0]++
+	MOVE @++DP[1], @DP[1]++
+	MOVE @BP[++Offs], @BP[Offs++]
+	MOVE @--DP[0], @DP[0]--
+	MOVE @--DP[1], @DP[1]--
+	MOVE @BP[--Offs], @BP[Offs--]	
+	MOVE @++DP[0], @DP[0]--
+	MOVE @++DP[1], @DP[1]--	
+	MOVE @BP[++Offs], @BP[Offs--]		
+	MOVE @--DP[0], @DP[0]++
+	MOVE @--DP[1], @DP[1]++
+	MOVE @BP[--Offs], @BP[Offs++]
+	MOVE @DP[0], @DP[0]++
+	MOVE @DP[1], @DP[1]++
+	MOVE @BP[Offs], @BP[Offs++]
+	MOVE @DP[0], @DP[0]--
+	MOVE @DP[1], @DP[1]--
+	MOVE @BP[Offs], @BP[Offs--]
+	MOVE DP[0], @DP[0]++
+	MOVE DP[0], @DP[0]--
+	MOVE DP[1], @DP[1]++
+	MOVE DP[1], @DP[1]--
+	MOVE Offs, @BP[Offs--]	
+	MOVE Offs, @BP[Offs++]
diff --git a/gas/testsuite/gas/maxq10/jump.d b/gas/testsuite/gas/maxq10/jump.d
new file mode 100644
index 0000000..2cc9c9b
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/jump.d
@@ -0,0 +1,117 @@
+#objdump: -dw
+#name: Jump operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <LableStart>:
+   0:	00 0c [ 	]*JUMP  #00h
+   2:	ff 2c [ 	]*JUMP C , #ffh
+   4:	09 ac [ 	]*JUMP C , A\[0\]
+   6:	19 ac [ 	]*JUMP C , A\[1\]
+   8:	fc 6c [ 	]*JUMP NC , #fch
+   a:	09 ec [ 	]*JUMP NC , A\[0\]
+   c:	19 ec [ 	]*JUMP NC , A\[1\]
+   e:	f9 4c [ 	]*JUMP S , #f9h
+  10:	09 cc [ 	]*JUMP S , A\[0\]
+  12:	19 cc [ 	]*JUMP S , A\[1\]
+  14:	f6 1c [ 	]*JUMP Z , #f6h
+  16:	09 9c [ 	]*JUMP Z , A\[0\]
+  18:	19 9c [ 	]*JUMP Z , A\[1\]
+  1a:	f3 5c [ 	]*JUMP NZ , #f3h
+  1c:	09 dc [ 	]*JUMP NZ , A\[0\]
+  1e:	19 dc [ 	]*JUMP NZ , A\[1\]
+  20:	f0 3c [ 	]*JUMP E , #f0h
+  22:	ef 7c [ 	]*JUMP NE , #efh
+  24:	01 7c [ 	]*JUMP NE , #01h
+
+0+026 <Lable1>:
+  26:	00 0c [ 	]*JUMP  #00h
+  28:	ff 2c [ 	]*JUMP C , #ffh
+  2a:	09 ac [ 	]*JUMP C , A\[0\]
+  2c:	19 ac [ 	]*JUMP C , A\[1\]
+  2e:	fc 6c [ 	]*JUMP NC , #fch
+  30:	09 ec [ 	]*JUMP NC , A\[0\]
+  32:	19 ec [ 	]*JUMP NC , A\[1\]
+  34:	f9 4c [ 	]*JUMP S , #f9h
+  36:	09 cc [ 	]*JUMP S , A\[0\]
+  38:	19 cc [ 	]*JUMP S , A\[1\]
+  3a:	f6 1c [ 	]*JUMP Z , #f6h
+  3c:	09 9c [ 	]*JUMP Z , A\[0\]
+  3e:	19 9c [ 	]*JUMP Z , A\[1\]
+  40:	f3 5c [ 	]*JUMP NZ , #f3h
+  42:	09 dc [ 	]*JUMP NZ , A\[0\]
+  44:	19 dc [ 	]*JUMP NZ , A\[1\]
+  46:	f0 3c [ 	]*JUMP E , #f0h
+  48:	ef 7c [ 	]*JUMP NE , #efh
+  4a:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  4c:	c6 0c [ 	]*JUMP  #c6h
+  4e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  50:	c6 2c [ 	]*JUMP C , #c6h
+  52:	09 ac [ 	]*JUMP C , A\[0\]
+  54:	19 ac [ 	]*JUMP C , A\[1\]
+  56:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  58:	c6 6c [ 	]*JUMP NC , #c6h
+  5a:	09 ec [ 	]*JUMP NC , A\[0\]
+  5c:	19 ec [ 	]*JUMP NC , A\[1\]
+  5e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  60:	c6 1c [ 	]*JUMP Z , #c6h
+  62:	09 9c [ 	]*JUMP Z , A\[0\]
+  64:	19 9c [ 	]*JUMP Z , A\[1\]
+  66:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  68:	c6 5c [ 	]*JUMP NZ , #c6h
+  6a:	09 dc [ 	]*JUMP NZ , A\[0\]
+  6c:	19 dc [ 	]*JUMP NZ , A\[1\]
+  6e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  70:	c6 4c [ 	]*JUMP S , #c6h
+  72:	09 cc [ 	]*JUMP S , A\[0\]
+  74:	19 cc [ 	]*JUMP S , A\[1\]
+  76:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  78:	c6 3c [ 	]*JUMP E , #c6h
+  7a:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  7c:	c6 7c [ 	]*JUMP NE , #c6h
+  7e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  80:	c6 0c [ 	]*JUMP  #c6h
+  82:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  84:	c6 2c [ 	]*JUMP C , #c6h
+  86:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  88:	09 ac [ 	]*JUMP C , A\[0\]
+  8a:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  8c:	19 ac [ 	]*JUMP C , A\[1\]
+  8e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  90:	c6 7c [ 	]*JUMP NE , #c6h
+  92:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  94:	c6 1c [ 	]*JUMP Z , #c6h
+  96:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  98:	09 9c [ 	]*JUMP Z , A\[0\]
+  9a:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  9c:	19 9c [ 	]*JUMP Z , A\[1\]
+  9e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  a0:	c6 5c [ 	]*JUMP NZ , #c6h
+  a2:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  a4:	09 dc [ 	]*JUMP NZ , A\[0\]
+  a6:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  a8:	19 dc [ 	]*JUMP NZ , A\[1\]
+  aa:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  ac:	c6 4c [ 	]*JUMP S , #c6h
+  ae:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  b0:	09 cc [ 	]*JUMP S , A\[0\]
+  b2:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  b4:	19 cc [ 	]*JUMP S , A\[1\]
+  b6:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  b8:	c6 6c [ 	]*JUMP NC , #c6h
+  ba:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  bc:	09 ec [ 	]*JUMP NC , A\[0\]
+  be:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  c0:	19 ec [ 	]*JUMP NC , A\[1\]
+  c2:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  c4:	c6 3c [ 	]*JUMP E , #c6h
+	...
+
+0+4c6 <LongJump>:
+ 4c6:	3a da [ 	]*NOP 
+ 4c8:	3a da [ 	]*NOP 
+ 4ca:	3a da [ 	]*NOP 
+ 4cc:	3a da [ 	]*NOP 
+ 4ce:	3a da [ 	]*NOP 
+
diff --git a/gas/testsuite/gas/maxq10/jump.s b/gas/testsuite/gas/maxq10/jump.s
new file mode 100644
index 0000000..3ce5838
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/jump.s
@@ -0,0 +1,86 @@
+;# jump.s 
+;# Program flow instructions using JUMP
+.text
+LableStart:	
+		JUMP LableStart
+		JUMP C, LableStart
+		JUMP C, A[0]
+		JUMP C, A[1]
+		JUMP NC, LableStart
+		JUMP NC, A[0]
+		JUMP NC, A[1]
+		JUMP S, LableStart
+		JUMP S, A[0]
+		JUMP S, A[1]	
+		JUMP Z, LableStart
+		JUMP Z, A[0]
+		JUMP Z, A[1]	
+		JUMP NZ, LableStart
+		JUMP NZ, A[0]
+		JUMP NZ, A[1]
+		JUMP E, LableStart
+		JUMP NE, LableStart
+		JUMP NE, Lable1
+
+Lable1:			
+		SJUMP Lable1		;Checking the SJUMP opcode
+		SJUMP C, Lable1
+		SJUMP C, A[0]
+		SJUMP C, A[1]
+		SJUMP NC, Lable1
+		SJUMP NC, A[0]
+		SJUMP NC, A[1]
+		SJUMP S, Lable1
+		SJUMP S, A[0]
+		SJUMP S, A[1]	
+		SJUMP Z, Lable1
+		SJUMP Z, A[0]
+		SJUMP Z, A[1]	
+		SJUMP NZ, Lable1
+		SJUMP NZ, A[0]
+		SJUMP NZ, A[1]	
+		SJUMP E, Lable1
+		SJUMP NE, Lable1
+		JUMP LongJump
+		JUMP C, LongJump
+		JUMP C, A[0]
+		JUMP C, A[1]
+		JUMP NC, LongJump
+		JUMP NC, A[0]
+		JUMP NC, A[1]
+		JUMP Z, LongJump
+		JUMP Z, A[0]
+		JUMP Z, A[1]
+		JUMP NZ, LongJump
+		JUMP NZ, A[0]
+		JUMP NZ, A[1]
+		JUMP S, LongJump
+		JUMP S, A[0]
+		JUMP S, A[1]	
+		JUMP E, LongJump
+		JUMP NE, LongJump
+		LJUMP LongJump		;test LJUMP also
+		LJUMP C, LongJump
+		LJUMP C, A[0]
+		LJUMP C, A[1]
+		LJUMP NE, LongJump
+		LJUMP Z, LongJump
+		LJUMP Z, A[0]
+		LJUMP Z, A[1]
+		LJUMP NZ, LongJump
+		LJUMP NZ, A[0]
+		LJUMP NZ, A[1]
+		LJUMP S, LongJump
+		LJUMP S, A[0]
+		LJUMP S, A[1]
+		LJUMP NC, LongJump
+		LJUMP NC, A[0]
+		LJUMP NC, A[1]	 
+		LJUMP E, LongJump
+		.fill 0x200, 2, 0 	
+LongJump: 
+		NOP
+		NOP
+		NOP
+		NOP
+		NOP
diff --git a/gas/testsuite/gas/maxq10/logical.d b/gas/testsuite/gas/maxq10/logical.d
new file mode 100644
index 0000000..8cad1bf
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/logical.d
@@ -0,0 +1,25 @@
+#objdump:-dw
+#name: Jump operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	00 08 [ 	]*MOVE  AP, #00h
+   2:	ff 1a [ 	]*AND  #ffh
+   4:	f0 2a [ 	]*OR  #f0h
+   6:	fe 3a [ 	]*XOR  #feh
+   8:	1a 8a [ 	]*CPL 
+   a:	9a 8a [ 	]*NEG 
+   c:	2a 8a [ 	]*SLA 
+   e:	3a 8a [ 	]*SLA2 
+  10:	6a 8a [ 	]*SLA4 
+  12:	4a 8a [ 	]*RL 
+  14:	5a 8a [ 	]*RLC 
+  16:	fa 8a [ 	]*SRA 
+  18:	ea 8a [ 	]*SRA2 
+  1a:	ba 8a [ 	]*SRA4 
+  1c:	aa 8a [ 	]*SR 
+  1e:	ca 8a [ 	]*RR 
+  20:	da 8a [ 	]*RRC 
+	...
diff --git a/gas/testsuite/gas/maxq10/logical.s b/gas/testsuite/gas/maxq10/logical.s
new file mode 100644
index 0000000..aa4202a
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/logical.s
@@ -0,0 +1,23 @@
+;# logical.s
+;# Verifies all the logical operation in the file
+
+.text	
+foo:
+	MOVE AP, #00h	;Set AC[0] as the active accumulator
+	AND #FFh	;AND AC[0] with 0xFF
+	OR #F0h
+	XOR #FEh
+	CPL
+	NEG
+	SLA
+	SLA2	
+	SLA4
+	RL	
+	RLC
+	SRA
+	SRA2
+	SRA4
+	SR
+	RR
+	RRC	
+
diff --git a/gas/testsuite/gas/maxq10/math.d b/gas/testsuite/gas/maxq10/math.d
new file mode 100644
index 0000000..34a70dd
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/math.d
@@ -0,0 +1,41 @@
+#objdump:-dw
+#name: Math operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	01 4a [ 	]*ADD  #01h
+   2:	02 4a [ 	]*ADD  #02h
+   4:	03 4a [ 	]*ADD  #03h
+   6:	04 4a [ 	]*ADD  #04h
+   8:	05 4a [ 	]*ADD  #05h
+   a:	09 ca [ 	]*ADD  A\[0\]
+   c:	19 ca [ 	]*ADD  A\[1\]
+   e:	29 ca [ 	]*ADD  A\[2\]
+  10:	39 ca [ 	]*ADD  A\[3\]
+  12:	49 ca [ 	]*ADD  A\[4\]
+  14:	31 6a [ 	]*ADDC  #31h
+  16:	32 6a [ 	]*ADDC  #32h
+  18:	33 6a [ 	]*ADDC  #33h
+  1a:	09 ea [ 	]*ADDC  A\[0\]
+  1c:	19 ea [ 	]*ADDC  A\[1\]
+  1e:	29 ea [ 	]*ADDC  A\[2\]
+  20:	39 ea [ 	]*ADDC  A\[3\]
+  22:	01 5a [ 	]*SUB  #01h
+  24:	02 5a [ 	]*SUB  #02h
+  26:	03 5a [ 	]*SUB  #03h
+  28:	04 5a [ 	]*SUB  #04h
+  2a:	05 5a [ 	]*SUB  #05h
+  2c:	09 da [ 	]*SUB  A\[0\]
+  2e:	19 da [ 	]*SUB  A\[1\]
+  30:	29 da [ 	]*SUB  A\[2\]
+  32:	39 da [ 	]*SUB  A\[3\]
+  34:	49 da [ 	]*SUB  A\[4\]
+  36:	31 7a [ 	]*SUBB  #31h
+  38:	32 7a [ 	]*SUBB  #32h
+  3a:	33 7a [ 	]*SUBB  #33h
+  3c:	09 fa [ 	]*SUBB  A\[0\]
+  3e:	19 fa [ 	]*SUBB  A\[1\]
+  40:	29 fa [ 	]*SUBB  A\[2\]
+  42:	39 fa [ 	]*SUBB  A\[3\]
diff --git a/gas/testsuite/gas/maxq10/math.s b/gas/testsuite/gas/maxq10/math.s
new file mode 100644
index 0000000..b3c1bd7
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/math.s
@@ -0,0 +1,39 @@
+;# math.s
+;# Implements all the math intuctions
+
+.text
+foo:	
+	ADD #01h	; add 01h to accumulator
+	ADD #02h
+	ADD #03h
+	ADD #04h
+	ADD #05h
+	ADD A[0]	; Add Active accumulator+A[0]
+	ADD A[1]
+	ADD A[2]
+	ADD A[3]
+	ADD A[4]
+	ADDC #31h
+	ADDC #32h
+	ADDC #33h
+	ADDC A[0]
+	ADDC A[1]
+	ADDC A[2]
+	ADDC A[3]
+	SUB #01h	; Substract 01h from accumulator
+	SUB #02h
+	SUB #03h
+	SUB #04h
+	SUB #05h
+	SUB A[0]	; Active accumulator-A[0]
+	SUB A[1]
+	SUB A[2]
+	SUB A[3]
+	SUB A[4]	
+	SUBB #31h
+	SUBB #32h
+	SUBB #33h
+	SUBB A[0]
+	SUBB A[1]
+	SUBB A[2]
+	SUBB A[3]
diff --git a/gas/testsuite/gas/maxq10/maxq10.exp b/gas/testsuite/gas/maxq10/maxq10.exp
new file mode 100644
index 0000000..d6ab4c4
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/maxq10.exp
@@ -0,0 +1,52 @@
+#
+# MAXQ10 tests
+#
+proc run_list_test { name opts } {
+    global srcdir subdir
+    set testname "maxq10 $name"
+    set file $srcdir/$subdir/$name
+    gas_run ${name}.s $opts ">&dump.out"
+    if { [regexp_diff "dump.out" "${file}.l"] } then {
+	fail $testname
+	verbose "output is [file_contents "dump.out"]" 2
+	return
+    }
+    pass $testname
+}
+
+proc gas_64_check { } {
+    global NM
+    global NMFLAGS
+    global srcdir
+
+    catch "exec $srcdir/lib/run $NM $NMFLAGS --help" nm_help
+    return [regexp "targets:.*maxq" $nm_help];
+}
+
+proc gas_32_check { } {
+    global NM
+    global NMFLAGS
+    global srcdir
+
+    catch "exec $srcdir/lib/run $NM $NMFLAGS --help" nm_help
+    return [regexp "targets:.*maxq" $nm_help];
+}
+
+if [expr ([istarget "maxq-*-*"] ||  [istarget "maxq-coff-*"]) && [gas_32_check]]  then {
+
+    global ASFLAGS
+    set old_ASFLAGS "$ASFLAGS"
+    set ASFLAGS "$ASFLAGS -MAXQ10"
+
+    run_dump_test "range"
+    run_dump_test "data3"
+    run_dump_test "data2"
+    run_dump_test "call"
+    run_dump_test "jump"
+    run_dump_test "logical"
+    run_dump_test "math"
+    run_dump_test "bits"
+
+    set ASFLAGS "$old_ASFLAGS"
+}
+
diff --git a/gas/testsuite/gas/maxq10/pmtest.d b/gas/testsuite/gas/maxq10/pmtest.d
new file mode 100644
index 0000000..d4d97a4
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/pmtest.d
@@ -0,0 +1,21 @@
+#objdump: -dw
+#name: MaC supoprt check
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <.text>:
+   0:	05 13 [ 	]*MOVE  13h, #05h
+   2:	e9 53 [ 	]*MOVE  53h, #e9h
+   4:	09 e3 [ 	]*MOVE  63h, A\[0\]
+   6:	12 14 [ 	]*MOVE  14h, #12h
+   8:	12 44 [ 	]*MOVE  44h, #12h
+   a:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+   c:	09 84 [ 	]*MOVE  04h, A\[0\]
+   e:	7b 15 [ 	]*MOVE  15h, #7bh
+  10:	13 25 [ 	]*MOVE  25h, #13h
+  12:	d9 e5 [ 	]*MOVE  65h, A\[13\]
+  14:	13 15 [ 	]*MOVE  15h, #13h
+  16:	13 a5 [ 	]*MOVE  25h, 13h
+  18:	12 13 [ 	]*MOVE  13h, #12h
+	...
diff --git a/gas/testsuite/gas/maxq10/pmtest.s b/gas/testsuite/gas/maxq10/pmtest.s
new file mode 100644
index 0000000..cce6f16
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/pmtest.s
@@ -0,0 +1,22 @@
+;# Peripheral(plugable) module test file 
+.text
+
+; Timer1 test module configured at mod. no. 3
+move T1CN, #05h
+move T1MD, #233
+move T1CL,A[0]
+; Timer2 module test plugged at mod. no. 4
+move T2CFG, #12h
+move T2V, #12h
+move T2C, A[0]
+
+; MAC module test plugged at 5
+move MCNT, #123
+move MA, #13h
+move MC0, A[13]
+
+;test the pm support 
+move 15h,#13h
+move 25h, 13h
+move 13h, #12h
+
diff --git a/gas/testsuite/gas/maxq10/range.d b/gas/testsuite/gas/maxq10/range.d
new file mode 100644
index 0000000..2ff72bb
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/range.d
@@ -0,0 +1,49 @@
+#objdump: -dw
+#name: limit checks for maxq10 immediate data
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <.text>:
+   0:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+   2:	ff 09 [ 	]*MOVE  A\[0\], #ffh
+   4:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+   6:	ff 08 [ 	]*MOVE  AP, #ffh
+   8:	01 09 [ 	]*MOVE  A\[0\], #01h
+   a:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+   c:	83 08 [ 	]*MOVE  AP, #83h
+   e:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  10:	82 08 [ 	]*MOVE  AP, #82h
+  12:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  14:	81 08 [ 	]*MOVE  AP, #81h
+  16:	7d 09 [ 	]*MOVE  A\[0\], #7dh
+  18:	7e 09 [ 	]*MOVE  A\[0\], #7eh
+  1a:	80 09 [ 	]*MOVE  A\[0\], #80h
+  1c:	fe 09 [ 	]*MOVE  A\[0\], #feh
+  1e:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  20:	ff 0d [ 	]*MOVE  @\+\+SP, #ffh
+  22:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  24:	82 0d [ 	]*MOVE  @\+\+SP, #82h
+  26:	fe 0d [ 	]*MOVE  @\+\+SP, #feh
+  28:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  2a:	81 0d [ 	]*MOVE  @\+\+SP, #81h
+  2c:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  2e:	80 0d [ 	]*MOVE  @\+\+SP, #80h
+  30:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  32:	ff 4a [ 	]*ADD  #ffh
+  34:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  36:	81 4a [ 	]*ADD  #81h
+  38:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  3a:	7f 4a [ 	]*ADD  #7fh
+  3c:	7f 4a [ 	]*ADD  #7fh
+  3e:	80 4a [ 	]*ADD  #80h
+  40:	81 4a [ 	]*ADD  #81h
+  42:	fe 4a [ 	]*ADD  #feh
+  44:	ff 4a [ 	]*ADD  #ffh
+  46:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  48:	02 4a [ 	]*ADD  #02h
+  4a:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  4c:	81 4a [ 	]*ADD  #81h
+  4e:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  50:	7f 4a [ 	]*ADD  #7fh
+
diff --git a/gas/testsuite/gas/maxq10/range.s b/gas/testsuite/gas/maxq10/range.s
new file mode 100644
index 0000000..f3cdc95
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/range.s
@@ -0,0 +1,30 @@
+;# checks the 8 bit ranges
+;# all negative values should contain a Prefix for MAXQ20
+;# immediate values with one operand for MAXQ10 skips PFX
+.text 
+	move A[0], #-1  
+	move Ap, #-1
+	move a[0], #1
+	move AP, #-125	; AP is an 8 bit register 
+	move AP, #-126
+	move AP, #-127
+	move A[0], #125		; A[0] is an 16 bit register - no pfx req. here
+	move A[0], #126
+	move A[0], #128
+	move A[0], #254	        ; ---------------
+	move @++SP, #-1		; check PFX generation for mem operands
+	move @++sp, #-126	; -
+	move @++sp, #254		; - no pFX here
+	move @++sp, #-127	; -
+	move @++sp, #-128	;--------------------------
+	Add #-1			;Check PFX gen. for single operand instructions
+	Add #-127
+	Add #-129
+	Add #127
+	Add #128
+	add #129
+	add #254
+	add #ffh
+	add #-254
+	add #-127
+	add #-129		; --------------------
diff --git a/gas/testsuite/gas/maxq20/bits.d b/gas/testsuite/gas/maxq20/bits.d
new file mode 100644
index 0000000..23abe79
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/bits.d
@@ -0,0 +1,95 @@
+#objdump: -dw
+#name: bit opp
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	0a ea [ 	]*MOVE C,Acc.0
+   2:	1a ea [ 	]*MOVE C,Acc.1
+   4:	2a ea [ 	]*MOVE C,Acc.2
+   6:	3a ea [ 	]*MOVE C,Acc.3
+   8:	4a ea [ 	]*MOVE C,Acc.4
+   a:	5a ea [ 	]*MOVE C,Acc.5
+   c:	6a ea [ 	]*MOVE C,Acc.6
+   e:	7a ea [ 	]*MOVE C,Acc.7
+  10:	8a ea [ 	]*MOVE C,Acc.8
+  12:	9a ea [ 	]*MOVE C,Acc.9
+  14:	aa ea [ 	]*MOVE C,Acc.10
+  16:	ba ea [ 	]*MOVE C,Acc.11
+  18:	ca ea [ 	]*MOVE C,Acc.12
+  1a:	da ea [ 	]*MOVE C,Acc.13
+  1c:	ea ea [ 	]*MOVE C,Acc.14
+  1e:	fa ea [ 	]*MOVE C,Acc.15
+  20:	0a da [ 	]*MOVE C,#0
+  22:	1a da [ 	]*MOVE C,#1
+  24:	0a fa [ 	]*MOVE Acc.0,C
+  26:	1a fa [ 	]*MOVE Acc.1,C
+  28:	2a fa [ 	]*MOVE Acc.2,C
+  2a:	3a fa [ 	]*MOVE Acc.3,C
+  2c:	4a fa [ 	]*MOVE Acc.4,C
+  2e:	5a fa [ 	]*MOVE Acc.5,C
+  30:	6a fa [ 	]*MOVE Acc.6,C
+  32:	7a fa [ 	]*MOVE Acc.7,C
+  34:	8a fa [ 	]*MOVE Acc.8,C
+  36:	9a fa [ 	]*MOVE Acc.9,C
+  38:	aa fa [ 	]*MOVE Acc.10,C
+  3a:	ba fa [ 	]*MOVE Acc.11,C
+  3c:	ca fa [ 	]*MOVE Acc.12,C
+  3e:	da fa [ 	]*MOVE Acc.13,C
+  40:	ea fa [ 	]*MOVE Acc.14,C
+  42:	fa fa [ 	]*MOVE Acc.15,C
+  44:	2a da [ 	]*CPL C
+  46:	0a 9a [ 	]*AND Acc.0
+  48:	1a 9a [ 	]*AND Acc.1
+  4a:	2a 9a [ 	]*AND Acc.2
+  4c:	3a 9a [ 	]*AND Acc.3
+  4e:	4a 9a [ 	]*AND Acc.4
+  50:	5a 9a [ 	]*AND Acc.5
+  52:	6a 9a [ 	]*AND Acc.6
+  54:	7a 9a [ 	]*AND Acc.7
+  56:	8a 9a [ 	]*AND Acc.8
+  58:	9a 9a [ 	]*AND Acc.9
+  5a:	aa 9a [ 	]*AND Acc.10
+  5c:	ba 9a [ 	]*AND Acc.11
+  5e:	ca 9a [ 	]*AND Acc.12
+  60:	da 9a [ 	]*AND Acc.13
+  62:	ea 9a [ 	]*AND Acc.14
+  64:	fa 9a [ 	]*AND Acc.15
+  66:	0a aa [ 	]*OR Acc.0
+  68:	1a aa [ 	]*OR Acc.1
+  6a:	2a aa [ 	]*OR Acc.2
+  6c:	3a aa [ 	]*OR Acc.3
+  6e:	4a aa [ 	]*OR Acc.4
+  70:	5a aa [ 	]*OR Acc.5
+  72:	6a aa [ 	]*OR Acc.6
+  74:	7a aa [ 	]*OR Acc.7
+  76:	8a aa [ 	]*OR Acc.8
+  78:	9a aa [ 	]*OR Acc.9
+  7a:	aa aa [ 	]*OR Acc.10
+  7c:	ba aa [ 	]*OR Acc.11
+  7e:	ca aa [ 	]*OR Acc.12
+  80:	da aa [ 	]*OR Acc.13
+  82:	ea aa [ 	]*OR Acc.14
+  84:	fa aa [ 	]*OR Acc.15
+  86:	0a ba [ 	]*XOR Acc.0
+  88:	1a ba [ 	]*XOR Acc.1
+  8a:	2a ba [ 	]*XOR Acc.2
+  8c:	3a ba [ 	]*XOR Acc.3
+  8e:	4a ba [ 	]*XOR Acc.4
+  90:	5a ba [ 	]*XOR Acc.5
+  92:	6a ba [ 	]*XOR Acc.6
+  94:	7a ba [ 	]*XOR Acc.7
+  96:	8a ba [ 	]*XOR Acc.8
+  98:	9a ba [ 	]*XOR Acc.9
+  9a:	aa ba [ 	]*XOR Acc.10
+  9c:	ba ba [ 	]*XOR Acc.11
+  9e:	ca ba [ 	]*XOR Acc.12
+  a0:	da ba [ 	]*XOR Acc.13
+  a2:	ea ba [ 	]*XOR Acc.14
+  a4:	fa ba [ 	]*XOR Acc.15
+  a6:	88 97 [ 	]*MOVE C , SC.1
+  a8:	68 87 [ 	]*MOVE C , IMR.0
+  aa:	58 87 [ 	]*MOVE C , IC.0
+  ac:	48 87 [ 	]*MOVE C , PSF.0
+	...
diff --git a/gas/testsuite/gas/maxq20/bits.s b/gas/testsuite/gas/maxq20/bits.s
new file mode 100644
index 0000000..de14aef
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/bits.s
@@ -0,0 +1,92 @@
+;# bits.s
+;# checks all the bit operations in MAXQ20
+
+.text
+foo:
+ MOVE C, ACC.0	
+ MOVE C, ACC.1
+ MOVE C, ACC.2
+ MOVE C, ACC.3
+ MOVE C, ACC.4
+ MOVE C, ACC.5
+ MOVE C, ACC.6
+ MOVE C, ACC.7		;8 bits on a MAXQ10 machine
+ MOVE C, ACC.8		
+ MOVE C, ACC.9
+ MOVE C, ACC.10
+ MOVE C, ACC.11
+ MOVE C, ACC.12
+ MOVE C, ACC.13
+ MOVE C, ACC.14
+ MOVE C, ACC.15 
+ MOVE C, #0
+ MOVE C, #1
+ MOVE ACC.0, C	
+ MOVE ACC.1, C 
+ MOVE ACC.2, C
+ MOVE ACC.3, C
+ MOVE ACC.4, C
+ MOVE ACC.5, C
+ MOVE ACC.6, C
+ MOVE ACC.7, C		;8 bits on a MAXQ10 machine
+ MOVE ACC.8, C		
+ MOVE ACC.9, C
+ MOVE ACC.10, C
+ MOVE ACC.11, C
+ MOVE ACC.12, C
+ MOVE ACC.13, C
+ MOVE ACC.14, C
+ MOVE ACC.15, C
+ CPL C
+ AND ACC.0	;AND with carry
+ AND ACC.1	
+ AND ACC.2	
+ AND ACC.3	
+ AND ACC.4	
+ AND ACC.5	
+ AND ACC.6	
+ AND ACC.7	
+ AND ACC.8	
+ AND ACC.9	
+ AND ACC.10	
+ AND ACC.11	
+ AND ACC.12	
+ AND ACC.13	
+ AND ACC.14	
+ AND ACC.15	
+ OR ACC.0	;OR with carry
+ OR ACC.1	
+ OR ACC.2	
+ OR ACC.3	
+ OR ACC.4	
+ OR ACC.5	
+ OR ACC.6	
+ OR ACC.7	
+ OR ACC.8	
+ OR ACC.9	
+ OR ACC.10	
+ OR ACC.11	
+ OR ACC.12	
+ OR ACC.13	
+ OR ACC.14	
+ OR  ACC.15	
+ XOR ACC.0	;XOR with carry
+ XOR ACC.1	
+ XOR ACC.2	
+ XOR ACC.3	
+ XOR ACC.4	
+ XOR ACC.5	
+ XOR ACC.6	
+ XOR ACC.7	
+ XOR ACC.8	
+ XOR ACC.9	
+ XOR ACC.10	
+ XOR ACC.11	 
+ XOR ACC.12	
+ XOR ACC.13	
+ XOR ACC.14	;Error condition when ACC.n and n>15
+ XOR ACC.15	
+ MOVE C, SC.1
+ MOVE C, IMR.0
+ MOVE C, IC.0
+ MOVE C, PSF.0		;move program status flag bit 0
diff --git a/gas/testsuite/gas/maxq20/call.d b/gas/testsuite/gas/maxq20/call.d
new file mode 100644
index 0000000..9789e5a
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/call.d
@@ -0,0 +1,42 @@
+#objdump: -dw
+#name: call operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	03 3d [ 	]*CALL  #03h
+   2:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+   4:	28 3d [ 	]*CALL  #28h
+
+0+006 <SmallCall>:
+   6:	0d 8c [ 	]*RET 
+   8:	0d ac [ 	]*RET C
+   a:	0d 9c [ 	]*RET Z
+   c:	0d dc [ 	]*RET NZ
+   e:	0d cc [ 	]*RET S
+  10:	8d 8c [ 	]*RETI 
+  12:	8d ac [ 	]*RETI C
+  14:	8d 9c [ 	]*RETI Z
+  16:	8d dc [ 	]*RETI NZ
+  18:	8d cc [ 	]*RETI S
+  1a:	10 7d [ 	]*MOVE  LC\[1\], #10h
+
+0+01c <LoopTop>:
+  1c:	00 3d [ 	]*CALL  #00h
+  1e:	ff 5d [ 	]*DJNZ LC\[1\], #ffh
+  20:	10 7d [ 	]*MOVE  LC\[1\], #10h
+
+0+022 <LoopTop1>:
+  22:	00 3d [ 	]*CALL  #00h
+	...
+ 424:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+ 426:	1c 5d [ 	]*DJNZ LC\[1\], #1ch
+
+0+428 <LongCall>:
+ 428:	8d 8c [ 	]*RETI 
+ 42a:	8d ac [ 	]*RETI C
+ 42c:	8d 9c [ 	]*RETI Z
+ 42e:	8d dc [ 	]*RETI NZ
+ 430:	8d cc [ 	]*RETI S
+	...
diff --git a/gas/testsuite/gas/maxq20/call.s b/gas/testsuite/gas/maxq20/call.s
new file mode 100644
index 0000000..0762726
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/call.s
@@ -0,0 +1,32 @@
+;# calls.s
+;# check program flow instruction involving CALL & RET
+.text
+foo:
+	Call SmallCall
+	Call LongCall
+SmallCall:
+	RET
+	RET C
+	RET Z
+	RET NZ
+	RET S	
+	RETI
+	RETI C
+	RETI Z
+	RETI NZ
+	RETI S
+	MOVE LC[1], #10h
+LoopTop:
+	Call LoopTop
+	DJNZ LC[1], LoopTop
+	MOVE LC[1], #10h
+LoopTop1:
+	Call LoopTop1
+	.fill 0x200, 2, 0 
+	DJNZ LC[1], LoopTop	
+LongCall:
+	RETI
+	RETI C
+	RETI Z
+	RETI NZ
+	RETI S
diff --git a/gas/testsuite/gas/maxq20/data1.d b/gas/testsuite/gas/maxq20/data1.d
new file mode 100644
index 0000000..e394f7a
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/data1.d
@@ -0,0 +1,119 @@
+#objdump:-dw
+#name: 1st  Move operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	8a 8a [ 	]*XCH 
+   2:	7a 8a [ 	]*XCHN 
+   4:	01 76 [ 	]*MOVE  NUL, #01h
+   6:	08 f6 [ 	]*MOVE  NUL, AP
+   8:	18 f6 [ 	]*MOVE  NUL, APC
+   a:	48 f6 [ 	]*MOVE  NUL, PSF
+   c:	58 f6 [ 	]*MOVE  NUL, IC
+   e:	68 f6 [ 	]*MOVE  NUL, IMR
+  10:	88 f6 [ 	]*MOVE  NUL, SC
+  12:	b8 f6 [ 	]*MOVE  NUL, IIR
+  14:	e8 f6 [ 	]*MOVE  NUL, CKCN
+  16:	f8 f6 [ 	]*MOVE  NUL, WDCN
+  18:	09 f6 [ 	]*MOVE  NUL, A\[0\]
+  1a:	f9 f6 [ 	]*MOVE  NUL, A\[15\]
+  1c:	0a f6 [ 	]*MOVE  NUL, ACC
+  1e:	1a f6 [ 	]*MOVE  NUL, A\[AP\]
+  20:	0c f6 [ 	]*MOVE  NUL, IP
+  22:	0d f6 [ 	]*POP  NUL
+  24:	1d f6 [ 	]*MOVE  NUL, SP
+  26:	2d f6 [ 	]*MOVE  NUL, IV
+  28:	6d f6 [ 	]*MOVE  NUL, LC\[0\]
+  2a:	7d f6 [ 	]*MOVE  NUL, LC\[1\]
+  2c:	1e f6 [ 	]*MOVE  NUL, @BP\[OFFS\+\+\]
+  2e:	2e f6 [ 	]*MOVE  NUL, @BP\[OFFS\-\-\]
+  30:	3e f6 [ 	]*MOVE  NUL, OFFS
+  32:	4e f6 [ 	]*MOVE  NUL, DPC
+  34:	5e f6 [ 	]*MOVE  NUL, GR
+  36:	6e f6 [ 	]*MOVE  NUL, GRL
+  38:	7e f6 [ 	]*MOVE  NUL, BP
+  3a:	8e f6 [ 	]*MOVE  NUL, GRS
+  3c:	9e f6 [ 	]*MOVE  NUL, GRH
+  3e:	ae f6 [ 	]*MOVE  NUL, GRXL
+  40:	be f6 [ 	]*MOVE  NUL, FP
+  42:	0f f6 [ 	]*MOVE  NUL, @DP\[0\]
+  44:	4f f6 [ 	]*MOVE  NUL, @DP\[1\]
+  46:	1f f6 [ 	]*MOVE  NUL, @DP\[0\]\+\+
+  48:	5f f6 [ 	]*MOVE  NUL, @DP\[1\]\+\+
+  4a:	2f f6 [ 	]*MOVE  NUL, @DP\[0\]\-\-
+  4c:	6f f6 [ 	]*MOVE  NUL, @DP\[1\]\-\-
+  4e:	01 08 [ 	]*MOVE  AP, #01h
+  50:	18 88 [ 	]*MOVE  AP, APC
+  52:	48 88 [ 	]*MOVE  AP, PSF
+  54:	58 88 [ 	]*MOVE  AP, IC
+  56:	68 88 [ 	]*MOVE  AP, IMR
+  58:	88 88 [ 	]*MOVE  AP, SC
+  5a:	b8 88 [ 	]*MOVE  AP, IIR
+  5c:	e8 88 [ 	]*MOVE  AP, CKCN
+  5e:	f8 88 [ 	]*MOVE  AP, WDCN
+  60:	09 88 [ 	]*MOVE  AP, A\[0\]
+  62:	f9 88 [ 	]*MOVE  AP, A\[15\]
+  64:	0a 88 [ 	]*MOVE  AP, ACC
+  66:	1a 88 [ 	]*MOVE  AP, A\[AP\]
+  68:	0c 88 [ 	]*MOVE  AP, IP
+  6a:	0d 88 [ 	]*MOVE  AP, @SP\-\-
+  6c:	1d 88 [ 	]*MOVE  AP, SP
+  6e:	2d 88 [ 	]*MOVE  AP, IV
+  70:	6d 88 [ 	]*MOVE  AP, LC\[0\]
+  72:	7d 88 [ 	]*MOVE  AP, LC\[1\]
+  74:	1e 88 [ 	]*MOVE  AP, @BP\[OFFS\+\+\]
+  76:	2e 88 [ 	]*MOVE  AP, @BP\[OFFS\-\-\]
+  78:	3e 88 [ 	]*MOVE  AP, OFFS
+  7a:	4e 88 [ 	]*MOVE  AP, DPC
+  7c:	5e 88 [ 	]*MOVE  AP, GR
+  7e:	6e 88 [ 	]*MOVE  AP, GRL
+  80:	7e 88 [ 	]*MOVE  AP, BP
+  82:	8e 88 [ 	]*MOVE  AP, GRS
+  84:	9e 88 [ 	]*MOVE  AP, GRH
+  86:	ae 88 [ 	]*MOVE  AP, GRXL
+  88:	be 88 [ 	]*MOVE  AP, FP
+  8a:	0f 88 [ 	]*MOVE  AP, @DP\[0\]
+  8c:	4f 88 [ 	]*MOVE  AP, @DP\[1\]
+  8e:	1f 88 [ 	]*MOVE  AP, @DP\[0\]\+\+
+  90:	5f 88 [ 	]*MOVE  AP, @DP\[1\]\+\+
+  92:	2f 88 [ 	]*MOVE  AP, @DP\[0\]\-\-
+  94:	6f 88 [ 	]*MOVE  AP, @DP\[1\]\-\-
+  96:	01 18 [ 	]*MOVE  APC, #01h
+  98:	08 98 [ 	]*MOVE  APC, AP
+  9a:	48 98 [ 	]*MOVE  APC, PSF
+  9c:	58 98 [ 	]*MOVE  APC, IC
+  9e:	68 98 [ 	]*MOVE  APC, IMR
+  a0:	88 98 [ 	]*MOVE  APC, SC
+  a2:	b8 98 [ 	]*MOVE  APC, IIR
+  a4:	e8 98 [ 	]*MOVE  APC, CKCN
+  a6:	f8 98 [ 	]*MOVE  APC, WDCN
+  a8:	09 98 [ 	]*MOVE  APC, A\[0\]
+  aa:	f9 98 [ 	]*MOVE  APC, A\[15\]
+  ac:	0a 98 [ 	]*MOVE  APC, ACC
+  ae:	1a 98 [ 	]*MOVE  APC, A\[AP\]
+  b0:	0c 98 [ 	]*MOVE  APC, IP
+  b2:	0d 98 [ 	]*MOVE  APC, @SP\-\-
+  b4:	1d 98 [ 	]*MOVE  APC, SP
+  b6:	2d 98 [ 	]*MOVE  APC, IV
+  b8:	6d 98 [ 	]*MOVE  APC, LC\[0\]
+  ba:	7d 98 [ 	]*MOVE  APC, LC\[1\]
+  bc:	1e 98 [ 	]*MOVE  APC, @BP\[OFFS\+\+\]
+  be:	2e 98 [ 	]*MOVE  APC, @BP\[OFFS\-\-\]
+  c0:	3e 98 [ 	]*MOVE  APC, OFFS
+  c2:	4e 98 [ 	]*MOVE  APC, DPC
+  c4:	5e 98 [ 	]*MOVE  APC, GR
+  c6:	6e 98 [ 	]*MOVE  APC, GRL
+  c8:	7e 98 [ 	]*MOVE  APC, BP
+  ca:	8e 98 [ 	]*MOVE  APC, GRS
+  cc:	9e 98 [ 	]*MOVE  APC, GRH
+  ce:	ae 98 [ 	]*MOVE  APC, GRXL
+  d0:	be 98 [ 	]*MOVE  APC, FP
+  d2:	0f 98 [ 	]*MOVE  APC, @DP\[0\]
+  d4:	4f 98 [ 	]*MOVE  APC, @DP\[1\]
+  d6:	1f 98 [ 	]*MOVE  APC, @DP\[0\]\+\+
+  d8:	5f 98 [ 	]*MOVE  APC, @DP\[1\]\+\+
+  da:	2f 98 [ 	]*MOVE  APC, @DP\[0\]\-\-
+  dc:	6f 98 [ 	]*MOVE  APC, @DP\[1\]\-\-
+	...
diff --git a/gas/testsuite/gas/maxq20/data1.s b/gas/testsuite/gas/maxq20/data1.s
new file mode 100644
index 0000000..a9b680e
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/data1.s
@@ -0,0 +1,114 @@
+;# data.s	
+;# checks all the data transfer instructions
+foo:
+	XCH	
+	XCHN
+	MOVE NUL, #01h
+	MOVE NUL, AP
+	MOVE NUL, APC
+	MOVE NUL, PSF
+	MOVE NUL, IC
+	MOVE NUL, IMR
+	MOVE NUL, SC
+	MOVE NUL, IIR
+	MOVE NUL, CKCN
+	MOVE NUL, WDCN
+	MOVE NUL, A[0]		;Just Check two boundary conditions
+	MOVE NUL, A[15]   
+	MOVE NUL, ACC
+	MOVE NUL, A[AP]
+	MOVE NUL, IP
+	MOVE NUL, @SP--
+	MOVE NUL, SP
+	MOVE NUL, IV
+	MOVE NUL, LC[0]
+	MOVE NUL, LC[1]
+	MOVE NUL, @BP[OFFS++]
+	MOVE NUL, @BP[OFFS--]
+	MOVE NUL, OFFS
+	MOVE NUL, DPC
+	MOVE NUL, GR
+	MOVE NUL, GRL
+	MOVE NUL, BP
+	MOVE NUL, GRS
+	MOVE NUL, GRH
+	MOVE NUL, GRXL
+	MOVE NUL, FP
+	MOVE NUL, @DP[0]	
+	MOVE NUL, @DP[1]	
+	MOVE NUL, @DP[0]++		
+	MOVE NUL, @DP[1]++
+	MOVE NUL, @DP[0]--
+	MOVE NUL, @DP[1]--
+	MOVE AP, #01h
+	MOVE AP, APC
+	MOVE AP, PSF
+	MOVE AP, IC
+	MOVE AP, IMR
+	MOVE AP, SC
+	MOVE AP, IIR
+	MOVE AP, CKCN
+	MOVE AP, WDCN
+	MOVE AP, A[0]		;Just Check two boundary conditions
+	MOVE AP, A[15]   
+	MOVE AP, ACC
+	MOVE AP, A[AP]
+	MOVE AP, IP
+	MOVE AP, @SP--
+	MOVE AP, SP
+	MOVE AP, IV
+	MOVE AP, LC[0]
+	MOVE AP, LC[1]
+	MOVE AP, @BP[OFFS++]
+	MOVE AP, @BP[OFFS--]
+	MOVE AP, OFFS
+	MOVE AP, DPC
+	MOVE AP, GR
+	MOVE AP, GRL
+	MOVE AP, BP
+	MOVE AP, GRS
+	MOVE AP, GRH
+	MOVE AP, GRXL
+	MOVE AP, FP
+	MOVE AP, @DP[0]	
+	MOVE AP, @DP[1]	
+	MOVE AP, @DP[0]++		
+	MOVE AP, @DP[1]++
+	MOVE AP, @DP[0]--
+	MOVE AP, @DP[1]--
+	MOVE APC, #01h
+	MOVE APC, AP
+	MOVE APC, PSF
+	MOVE APC, IC
+	MOVE APC, IMR
+	MOVE APC, SC
+	MOVE APC, IIR
+	MOVE APC, CKCN
+	MOVE APC, WDCN
+	MOVE APC, A[0]		;Just Check two boundary conditions
+	MOVE APC, A[15]   
+	MOVE APC, ACC
+	MOVE APC, A[AP]
+	MOVE APC, IP
+	MOVE APC, @SP--
+	MOVE APC, SP
+	MOVE APC, IV
+	MOVE APC, LC[0]
+	MOVE APC, LC[1]
+	MOVE APC, @BP[OFFS++]
+	MOVE APC, @BP[OFFS--]
+	MOVE APC, OFFS
+	MOVE APC, DPC
+	MOVE APC, GR
+	MOVE APC, GRL
+	MOVE APC, BP
+	MOVE APC, GRS
+	MOVE APC, GRH
+	MOVE APC, GRXL
+	MOVE APC, FP
+	MOVE APC, @DP[0]	
+	MOVE APC, @DP[1]	
+	MOVE APC, @DP[0]++		
+	MOVE APC, @DP[1]++
+	MOVE APC, @DP[0]--
+	MOVE APC, @DP[1]--
diff --git a/gas/testsuite/gas/maxq20/data2.d b/gas/testsuite/gas/maxq20/data2.d
new file mode 100644
index 0000000..d0fc205
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/data2.d
@@ -0,0 +1,459 @@
+#objdump: -dw
+#name: 2nd Move operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	01 48 [ 	]*MOVE  PSF, #01h
+   2:	08 c8 [ 	]*MOVE  PSF, AP
+   4:	18 c8 [ 	]*MOVE  PSF, APC
+   6:	58 c8 [ 	]*MOVE  PSF, IC
+   8:	68 c8 [ 	]*MOVE  PSF, IMR
+   a:	88 c8 [ 	]*MOVE  PSF, SC
+   c:	b8 c8 [ 	]*MOVE  PSF, IIR
+   e:	e8 c8 [ 	]*MOVE  PSF, CKCN
+  10:	f8 c8 [ 	]*MOVE  PSF, WDCN
+  12:	09 c8 [ 	]*MOVE  PSF, A\[0\]
+  14:	f9 c8 [ 	]*MOVE  PSF, A\[15\]
+  16:	0a c8 [ 	]*MOVE  PSF, ACC
+  18:	1a c8 [ 	]*MOVE  PSF, A\[AP\]
+  1a:	0c c8 [ 	]*MOVE  PSF, IP
+  1c:	0d c8 [ 	]*MOVE  PSF, @SP\-\-
+  1e:	1d c8 [ 	]*MOVE  PSF, SP
+  20:	2d c8 [ 	]*MOVE  PSF, IV
+  22:	6d c8 [ 	]*MOVE  PSF, LC\[0\]
+  24:	7d c8 [ 	]*MOVE  PSF, LC\[1\]
+  26:	1e c8 [ 	]*MOVE  PSF, @BP\[OFFS\+\+\]
+  28:	2e c8 [ 	]*MOVE  PSF, @BP\[OFFS\-\-\]
+  2a:	3e c8 [ 	]*MOVE  PSF, OFFS
+  2c:	4e c8 [ 	]*MOVE  PSF, DPC
+  2e:	5e c8 [ 	]*MOVE  PSF, GR
+  30:	6e c8 [ 	]*MOVE  PSF, GRL
+  32:	7e c8 [ 	]*MOVE  PSF, BP
+  34:	8e c8 [ 	]*MOVE  PSF, GRS
+  36:	9e c8 [ 	]*MOVE  PSF, GRH
+  38:	ae c8 [ 	]*MOVE  PSF, GRXL
+  3a:	be c8 [ 	]*MOVE  PSF, FP
+  3c:	0f c8 [ 	]*MOVE  PSF, @DP\[0\]
+  3e:	4f c8 [ 	]*MOVE  PSF, @DP\[1\]
+  40:	1f c8 [ 	]*MOVE  PSF, @DP\[0\]\+\+
+  42:	5f c8 [ 	]*MOVE  PSF, @DP\[1\]\+\+
+  44:	2f c8 [ 	]*MOVE  PSF, @DP\[0\]\-\-
+  46:	6f c8 [ 	]*MOVE  PSF, @DP\[1\]\-\-
+  48:	01 58 [ 	]*MOVE  IC, #01h
+  4a:	08 d8 [ 	]*MOVE  IC, AP
+  4c:	18 d8 [ 	]*MOVE  IC, APC
+  4e:	48 d8 [ 	]*MOVE  IC, PSF
+  50:	68 d8 [ 	]*MOVE  IC, IMR
+  52:	88 d8 [ 	]*MOVE  IC, SC
+  54:	b8 d8 [ 	]*MOVE  IC, IIR
+  56:	e8 d8 [ 	]*MOVE  IC, CKCN
+  58:	f8 d8 [ 	]*MOVE  IC, WDCN
+  5a:	09 d8 [ 	]*MOVE  IC, A\[0\]
+  5c:	f9 d8 [ 	]*MOVE  IC, A\[15\]
+  5e:	0a d8 [ 	]*MOVE  IC, ACC
+  60:	1a d8 [ 	]*MOVE  IC, A\[AP\]
+  62:	0c d8 [ 	]*MOVE  IC, IP
+  64:	0d d8 [ 	]*MOVE  IC, @SP\-\-
+  66:	1d d8 [ 	]*MOVE  IC, SP
+  68:	2d d8 [ 	]*MOVE  IC, IV
+  6a:	6d d8 [ 	]*MOVE  IC, LC\[0\]
+  6c:	7d d8 [ 	]*MOVE  IC, LC\[1\]
+  6e:	1e d8 [ 	]*MOVE  IC, @BP\[OFFS\+\+\]
+  70:	2e d8 [ 	]*MOVE  IC, @BP\[OFFS\-\-\]
+  72:	3e d8 [ 	]*MOVE  IC, OFFS
+  74:	4e d8 [ 	]*MOVE  IC, DPC
+  76:	5e d8 [ 	]*MOVE  IC, GR
+  78:	6e d8 [ 	]*MOVE  IC, GRL
+  7a:	7e d8 [ 	]*MOVE  IC, BP
+  7c:	8e d8 [ 	]*MOVE  IC, GRS
+  7e:	9e d8 [ 	]*MOVE  IC, GRH
+  80:	ae d8 [ 	]*MOVE  IC, GRXL
+  82:	be d8 [ 	]*MOVE  IC, FP
+  84:	0f d8 [ 	]*MOVE  IC, @DP\[0\]
+  86:	4f d8 [ 	]*MOVE  IC, @DP\[1\]
+  88:	1f d8 [ 	]*MOVE  IC, @DP\[0\]\+\+
+  8a:	5f d8 [ 	]*MOVE  IC, @DP\[1\]\+\+
+  8c:	2f d8 [ 	]*MOVE  IC, @DP\[0\]\-\-
+  8e:	6f d8 [ 	]*MOVE  IC, @DP\[1\]\-\-
+  90:	01 68 [ 	]*MOVE  IMR, #01h
+  92:	08 e8 [ 	]*MOVE  IMR, AP
+  94:	18 e8 [ 	]*MOVE  IMR, APC
+  96:	48 e8 [ 	]*MOVE  IMR, PSF
+  98:	58 e8 [ 	]*MOVE  IMR, IC
+  9a:	88 e8 [ 	]*MOVE  IMR, SC
+  9c:	b8 e8 [ 	]*MOVE  IMR, IIR
+  9e:	e8 e8 [ 	]*MOVE  IMR, CKCN
+  a0:	f8 e8 [ 	]*MOVE  IMR, WDCN
+  a2:	09 e8 [ 	]*MOVE  IMR, A\[0\]
+  a4:	f9 e8 [ 	]*MOVE  IMR, A\[15\]
+  a6:	0a e8 [ 	]*MOVE  IMR, ACC
+  a8:	1a e8 [ 	]*MOVE  IMR, A\[AP\]
+  aa:	0c e8 [ 	]*MOVE  IMR, IP
+  ac:	0d e8 [ 	]*MOVE  IMR, @SP\-\-
+  ae:	1d e8 [ 	]*MOVE  IMR, SP
+  b0:	2d e8 [ 	]*MOVE  IMR, IV
+  b2:	6d e8 [ 	]*MOVE  IMR, LC\[0\]
+  b4:	7d e8 [ 	]*MOVE  IMR, LC\[1\]
+  b6:	1e e8 [ 	]*MOVE  IMR, @BP\[OFFS\+\+\]
+  b8:	2e e8 [ 	]*MOVE  IMR, @BP\[OFFS\-\-\]
+  ba:	3e e8 [ 	]*MOVE  IMR, OFFS
+  bc:	4e e8 [ 	]*MOVE  IMR, DPC
+  be:	5e e8 [ 	]*MOVE  IMR, GR
+  c0:	6e e8 [ 	]*MOVE  IMR, GRL
+  c2:	7e e8 [ 	]*MOVE  IMR, BP
+  c4:	8e e8 [ 	]*MOVE  IMR, GRS
+  c6:	9e e8 [ 	]*MOVE  IMR, GRH
+  c8:	ae e8 [ 	]*MOVE  IMR, GRXL
+  ca:	be e8 [ 	]*MOVE  IMR, FP
+  cc:	0f e8 [ 	]*MOVE  IMR, @DP\[0\]
+  ce:	4f e8 [ 	]*MOVE  IMR, @DP\[1\]
+  d0:	1f e8 [ 	]*MOVE  IMR, @DP\[0\]\+\+
+  d2:	5f e8 [ 	]*MOVE  IMR, @DP\[1\]\+\+
+  d4:	2f e8 [ 	]*MOVE  IMR, @DP\[0\]\-\-
+  d6:	6f e8 [ 	]*MOVE  IMR, @DP\[1\]\-\-
+  d8:	01 09 [ 	]*MOVE  A\[0\], #01h
+  da:	08 89 [ 	]*MOVE  A\[0\], AP
+  dc:	18 89 [ 	]*MOVE  A\[0\], APC
+  de:	48 89 [ 	]*MOVE  A\[0\], PSF
+  e0:	58 89 [ 	]*MOVE  A\[0\], IC
+  e2:	68 89 [ 	]*MOVE  A\[0\], IMR
+  e4:	88 89 [ 	]*MOVE  A\[0\], SC
+  e6:	b8 89 [ 	]*MOVE  A\[0\], IIR
+  e8:	e8 89 [ 	]*MOVE  A\[0\], CKCN
+  ea:	f8 89 [ 	]*MOVE  A\[0\], WDCN
+  ec:	0a 89 [ 	]*MOVE  A\[0\], ACC
+  ee:	1a 89 [ 	]*MOVE  A\[0\], A\[AP\]
+  f0:	0c 89 [ 	]*MOVE  A\[0\], IP
+  f2:	0d 89 [ 	]*MOVE  A\[0\], @SP\-\-
+  f4:	1d 89 [ 	]*MOVE  A\[0\], SP
+  f6:	2d 89 [ 	]*MOVE  A\[0\], IV
+  f8:	6d 89 [ 	]*MOVE  A\[0\], LC\[0\]
+  fa:	7d 89 [ 	]*MOVE  A\[0\], LC\[1\]
+  fc:	1e 89 [ 	]*MOVE  A\[0\], @BP\[OFFS\+\+\]
+  fe:	2e 89 [ 	]*MOVE  A\[0\], @BP\[OFFS\-\-\]
+ 100:	3e 89 [ 	]*MOVE  A\[0\], OFFS
+ 102:	4e 89 [ 	]*MOVE  A\[0\], DPC
+ 104:	5e 89 [ 	]*MOVE  A\[0\], GR
+ 106:	6e 89 [ 	]*MOVE  A\[0\], GRL
+ 108:	7e 89 [ 	]*MOVE  A\[0\], BP
+ 10a:	8e 89 [ 	]*MOVE  A\[0\], GRS
+ 10c:	9e 89 [ 	]*MOVE  A\[0\], GRH
+ 10e:	ae 89 [ 	]*MOVE  A\[0\], GRXL
+ 110:	be 89 [ 	]*MOVE  A\[0\], FP
+ 112:	0f 89 [ 	]*MOVE  A\[0\], @DP\[0\]
+ 114:	4f 89 [ 	]*MOVE  A\[0\], @DP\[1\]
+ 116:	1f 89 [ 	]*MOVE  A\[0\], @DP\[0\]\+\+
+ 118:	5f 89 [ 	]*MOVE  A\[0\], @DP\[1\]\+\+
+ 11a:	2f 89 [ 	]*MOVE  A\[0\], @DP\[0\]\-\-
+ 11c:	6f 89 [ 	]*MOVE  A\[0\], @DP\[1\]\-\-
+ 11e:	01 0a [ 	]*MOVE  ACC, #01h
+ 120:	08 8a [ 	]*MOVE  ACC, AP
+ 122:	18 8a [ 	]*MOVE  ACC, APC
+ 124:	48 8a [ 	]*MOVE  ACC, PSF
+ 126:	58 8a [ 	]*MOVE  ACC, IC
+ 128:	68 8a [ 	]*MOVE  ACC, IMR
+ 12a:	88 8a [ 	]*MOVE  ACC, SC
+ 12c:	b8 8a [ 	]*MOVE  ACC, IIR
+ 12e:	e8 8a [ 	]*MOVE  ACC, CKCN
+ 130:	f8 8a [ 	]*MOVE  ACC, WDCN
+ 132:	09 8a [ 	]*MOVE  ACC, A\[0\]
+ 134:	f9 8a [ 	]*MOVE  ACC, A\[15\]
+ 136:	0c 8a [ 	]*MOVE  ACC, IP
+ 138:	0d 8a [ 	]*MOVE  ACC, @SP\-\-
+ 13a:	1d 8a [ 	]*MOVE  ACC, SP
+ 13c:	2d 8a [ 	]*MOVE  ACC, IV
+ 13e:	6d 8a [ 	]*MOVE  ACC, LC\[0\]
+ 140:	7d 8a [ 	]*MOVE  ACC, LC\[1\]
+ 142:	1e 8a [ 	]*MOVE  ACC, @BP\[OFFS\+\+\]
+ 144:	2e 8a [ 	]*MOVE  ACC, @BP\[OFFS\-\-\]
+ 146:	3e 8a [ 	]*MOVE  ACC, OFFS
+ 148:	4e 8a [ 	]*MOVE  ACC, DPC
+ 14a:	5e 8a [ 	]*MOVE  ACC, GR
+ 14c:	6e 8a [ 	]*MOVE  ACC, GRL
+ 14e:	7e 8a [ 	]*MOVE  ACC, BP
+ 150:	8e 8a [ 	]*MOVE  ACC, GRS
+ 152:	9e 8a [ 	]*MOVE  ACC, GRH
+ 154:	ae 8a [ 	]*MOVE  ACC, GRXL
+ 156:	be 8a [ 	]*MOVE  ACC, FP
+ 158:	0f 8a [ 	]*MOVE  ACC, @DP\[0\]
+ 15a:	4f 8a [ 	]*MOVE  ACC, @DP\[1\]
+ 15c:	1f 8a [ 	]*MOVE  ACC, @DP\[0\]\+\+
+ 15e:	5f 8a [ 	]*MOVE  ACC, @DP\[1\]\+\+
+ 160:	2f 8a [ 	]*MOVE  ACC, @DP\[0\]\-\-
+ 162:	6f 8a [ 	]*MOVE  ACC, @DP\[1\]\-\-
+ 164:	01 0d [ 	]*MOVE  @\+\+SP, #01h
+ 166:	08 8d [ 	]*MOVE  @\+\+SP, AP
+ 168:	18 8d [ 	]*MOVE  @\+\+SP, APC
+ 16a:	48 8d [ 	]*MOVE  @\+\+SP, PSF
+ 16c:	58 8d [ 	]*MOVE  @\+\+SP, IC
+ 16e:	68 8d [ 	]*MOVE  @\+\+SP, IMR
+ 170:	88 8d [ 	]*MOVE  @\+\+SP, SC
+ 172:	b8 8d [ 	]*MOVE  @\+\+SP, IIR
+ 174:	e8 8d [ 	]*MOVE  @\+\+SP, CKCN
+ 176:	f8 8d [ 	]*MOVE  @\+\+SP, WDCN
+ 178:	09 8d [ 	]*MOVE  @\+\+SP, A\[0\]
+ 17a:	f9 8d [ 	]*MOVE  @\+\+SP, A\[15\]
+ 17c:	0a 8d [ 	]*MOVE  @\+\+SP, ACC
+ 17e:	1a 8d [ 	]*MOVE  @\+\+SP, A\[AP\]
+ 180:	0c 8d [ 	]*MOVE  @\+\+SP, IP
+ 182:	1d 8d [ 	]*MOVE  @\+\+SP, SP
+ 184:	2d 8d [ 	]*MOVE  @\+\+SP, IV
+ 186:	6d 8d [ 	]*MOVE  @\+\+SP, LC\[0\]
+ 188:	7d 8d [ 	]*MOVE  @\+\+SP, LC\[1\]
+ 18a:	1e 8d [ 	]*MOVE  @\+\+SP, @BP\[OFFS\+\+\]
+ 18c:	2e 8d [ 	]*MOVE  @\+\+SP, @BP\[OFFS\-\-\]
+ 18e:	3e 8d [ 	]*MOVE  @\+\+SP, OFFS
+ 190:	4e 8d [ 	]*MOVE  @\+\+SP, DPC
+ 192:	5e 8d [ 	]*MOVE  @\+\+SP, GR
+ 194:	6e 8d [ 	]*MOVE  @\+\+SP, GRL
+ 196:	7e 8d [ 	]*MOVE  @\+\+SP, BP
+ 198:	8e 8d [ 	]*MOVE  @\+\+SP, GRS
+ 19a:	9e 8d [ 	]*MOVE  @\+\+SP, GRH
+ 19c:	ae 8d [ 	]*MOVE  @\+\+SP, GRXL
+ 19e:	be 8d [ 	]*MOVE  @\+\+SP, FP
+ 1a0:	0f 8d [ 	]*MOVE  @\+\+SP, @DP\[0\]
+ 1a2:	4f 8d [ 	]*MOVE  @\+\+SP, @DP\[1\]
+ 1a4:	1f 8d [ 	]*MOVE  @\+\+SP, @DP\[0\]\+\+
+ 1a6:	5f 8d [ 	]*MOVE  @\+\+SP, @DP\[1\]\+\+
+ 1a8:	2f 8d [ 	]*MOVE  @\+\+SP, @DP\[0\]\-\-
+ 1aa:	6f 8d [ 	]*MOVE  @\+\+SP, @DP\[1\]\-\-
+ 1ac:	01 1d [ 	]*MOVE  SP, #01h
+ 1ae:	08 9d [ 	]*MOVE  SP, AP
+ 1b0:	18 9d [ 	]*MOVE  SP, APC
+ 1b2:	48 9d [ 	]*MOVE  SP, PSF
+ 1b4:	58 9d [ 	]*MOVE  SP, IC
+ 1b6:	68 9d [ 	]*MOVE  SP, IMR
+ 1b8:	88 9d [ 	]*MOVE  SP, SC
+ 1ba:	b8 9d [ 	]*MOVE  SP, IIR
+ 1bc:	e8 9d [ 	]*MOVE  SP, CKCN
+ 1be:	f8 9d [ 	]*MOVE  SP, WDCN
+ 1c0:	09 9d [ 	]*MOVE  SP, A\[0\]
+ 1c2:	f9 9d [ 	]*MOVE  SP, A\[15\]
+ 1c4:	0a 9d [ 	]*MOVE  SP, ACC
+ 1c6:	1a 9d [ 	]*MOVE  SP, A\[AP\]
+ 1c8:	0c 9d [ 	]*MOVE  SP, IP
+ 1ca:	2d 9d [ 	]*MOVE  SP, IV
+ 1cc:	6d 9d [ 	]*MOVE  SP, LC\[0\]
+ 1ce:	7d 9d [ 	]*MOVE  SP, LC\[1\]
+ 1d0:	1e 9d [ 	]*MOVE  SP, @BP\[OFFS\+\+\]
+ 1d2:	2e 9d [ 	]*MOVE  SP, @BP\[OFFS\-\-\]
+ 1d4:	3e 9d [ 	]*MOVE  SP, OFFS
+ 1d6:	4e 9d [ 	]*MOVE  SP, DPC
+ 1d8:	5e 9d [ 	]*MOVE  SP, GR
+ 1da:	6e 9d [ 	]*MOVE  SP, GRL
+ 1dc:	7e 9d [ 	]*MOVE  SP, BP
+ 1de:	8e 9d [ 	]*MOVE  SP, GRS
+ 1e0:	9e 9d [ 	]*MOVE  SP, GRH
+ 1e2:	ae 9d [ 	]*MOVE  SP, GRXL
+ 1e4:	be 9d [ 	]*MOVE  SP, FP
+ 1e6:	0f 9d [ 	]*MOVE  SP, @DP\[0\]
+ 1e8:	4f 9d [ 	]*MOVE  SP, @DP\[1\]
+ 1ea:	1f 9d [ 	]*MOVE  SP, @DP\[0\]\+\+
+ 1ec:	5f 9d [ 	]*MOVE  SP, @DP\[1\]\+\+
+ 1ee:	2f 9d [ 	]*MOVE  SP, @DP\[0\]\-\-
+ 1f0:	6f 9d [ 	]*MOVE  SP, @DP\[1\]\-\-
+ 1f2:	01 2d [ 	]*MOVE  IV, #01h
+ 1f4:	08 ad [ 	]*MOVE  IV, AP
+ 1f6:	18 ad [ 	]*MOVE  IV, APC
+ 1f8:	48 ad [ 	]*MOVE  IV, PSF
+ 1fa:	58 ad [ 	]*MOVE  IV, IC
+ 1fc:	68 ad [ 	]*MOVE  IV, IMR
+ 1fe:	88 ad [ 	]*MOVE  IV, SC
+ 200:	b8 ad [ 	]*MOVE  IV, IIR
+ 202:	e8 ad [ 	]*MOVE  IV, CKCN
+ 204:	f8 ad [ 	]*MOVE  IV, WDCN
+ 206:	09 ad [ 	]*MOVE  IV, A\[0\]
+ 208:	f9 ad [ 	]*MOVE  IV, A\[15\]
+ 20a:	0a ad [ 	]*MOVE  IV, ACC
+ 20c:	1a ad [ 	]*MOVE  IV, A\[AP\]
+ 20e:	0c ad [ 	]*MOVE  IV, IP
+ 210:	0d ad [ 	]*MOVE  IV, @SP\-\-
+ 212:	1d ad [ 	]*MOVE  IV, SP
+ 214:	2d ad [ 	]*MOVE  IV, IV
+ 216:	6d ad [ 	]*MOVE  IV, LC\[0\]
+ 218:	7d ad [ 	]*MOVE  IV, LC\[1\]
+ 21a:	1e ad [ 	]*MOVE  IV, @BP\[OFFS\+\+\]
+ 21c:	2e ad [ 	]*MOVE  IV, @BP\[OFFS\-\-\]
+ 21e:	3e ad [ 	]*MOVE  IV, OFFS
+ 220:	4e ad [ 	]*MOVE  IV, DPC
+ 222:	5e ad [ 	]*MOVE  IV, GR
+ 224:	6e ad [ 	]*MOVE  IV, GRL
+ 226:	7e ad [ 	]*MOVE  IV, BP
+ 228:	8e ad [ 	]*MOVE  IV, GRS
+ 22a:	9e ad [ 	]*MOVE  IV, GRH
+ 22c:	ae ad [ 	]*MOVE  IV, GRXL
+ 22e:	be ad [ 	]*MOVE  IV, FP
+ 230:	0f ad [ 	]*MOVE  IV, @DP\[0\]
+ 232:	4f ad [ 	]*MOVE  IV, @DP\[1\]
+ 234:	1f ad [ 	]*MOVE  IV, @DP\[0\]\+\+
+ 236:	5f ad [ 	]*MOVE  IV, @DP\[1\]\+\+
+ 238:	2f ad [ 	]*MOVE  IV, @DP\[0\]\-\-
+ 23a:	6f ad [ 	]*MOVE  IV, @DP\[1\]\-\-
+ 23c:	01 6d [ 	]*MOVE  LC\[0\], #01h
+ 23e:	08 ed [ 	]*MOVE  LC\[0\], AP
+ 240:	18 ed [ 	]*MOVE  LC\[0\], APC
+ 242:	48 ed [ 	]*MOVE  LC\[0\], PSF
+ 244:	58 ed [ 	]*MOVE  LC\[0\], IC
+ 246:	68 ed [ 	]*MOVE  LC\[0\], IMR
+ 248:	88 ed [ 	]*MOVE  LC\[0\], SC
+ 24a:	b8 ed [ 	]*MOVE  LC\[0\], IIR
+ 24c:	e8 ed [ 	]*MOVE  LC\[0\], CKCN
+ 24e:	f8 ed [ 	]*MOVE  LC\[0\], WDCN
+ 250:	09 ed [ 	]*MOVE  LC\[0\], A\[0\]
+ 252:	f9 ed [ 	]*MOVE  LC\[0\], A\[15\]
+ 254:	0a ed [ 	]*MOVE  LC\[0\], ACC
+ 256:	1a ed [ 	]*MOVE  LC\[0\], A\[AP\]
+ 258:	0c ed [ 	]*MOVE  LC\[0\], IP
+ 25a:	0d ed [ 	]*MOVE  LC\[0\], @SP\-\-
+ 25c:	1d ed [ 	]*MOVE  LC\[0\], SP
+ 25e:	2d ed [ 	]*MOVE  LC\[0\], IV
+ 260:	1e ed [ 	]*MOVE  LC\[0\], @BP\[OFFS\+\+\]
+ 262:	2e ed [ 	]*MOVE  LC\[0\], @BP\[OFFS\-\-\]
+ 264:	3e ed [ 	]*MOVE  LC\[0\], OFFS
+ 266:	4e ed [ 	]*MOVE  LC\[0\], DPC
+ 268:	5e ed [ 	]*MOVE  LC\[0\], GR
+ 26a:	6e ed [ 	]*MOVE  LC\[0\], GRL
+ 26c:	7e ed [ 	]*MOVE  LC\[0\], BP
+ 26e:	8e ed [ 	]*MOVE  LC\[0\], GRS
+ 270:	9e ed [ 	]*MOVE  LC\[0\], GRH
+ 272:	ae ed [ 	]*MOVE  LC\[0\], GRXL
+ 274:	be ed [ 	]*MOVE  LC\[0\], FP
+ 276:	0f ed [ 	]*MOVE  LC\[0\], @DP\[0\]
+ 278:	4f ed [ 	]*MOVE  LC\[0\], @DP\[1\]
+ 27a:	1f ed [ 	]*MOVE  LC\[0\], @DP\[0\]\+\+
+ 27c:	5f ed [ 	]*MOVE  LC\[0\], @DP\[1\]\+\+
+ 27e:	2f ed [ 	]*MOVE  LC\[0\], @DP\[0\]\-\-
+ 280:	6f ed [ 	]*MOVE  LC\[0\], @DP\[1\]\-\-
+ 282:	01 0e [ 	]*MOVE  @BP\[OFFS\], #01h
+ 284:	08 8e [ 	]*MOVE  @BP\[OFFS\], AP
+ 286:	18 8e [ 	]*MOVE  @BP\[OFFS\], APC
+ 288:	48 8e [ 	]*MOVE  @BP\[OFFS\], PSF
+ 28a:	58 8e [ 	]*MOVE  @BP\[OFFS\], IC
+ 28c:	68 8e [ 	]*MOVE  @BP\[OFFS\], IMR
+ 28e:	88 8e [ 	]*MOVE  @BP\[OFFS\], SC
+ 290:	b8 8e [ 	]*MOVE  @BP\[OFFS\], IIR
+ 292:	e8 8e [ 	]*MOVE  @BP\[OFFS\], CKCN
+ 294:	f8 8e [ 	]*MOVE  @BP\[OFFS\], WDCN
+ 296:	09 8e [ 	]*MOVE  @BP\[OFFS\], A\[0\]
+ 298:	f9 8e [ 	]*MOVE  @BP\[OFFS\], A\[15\]
+ 29a:	0a 8e [ 	]*MOVE  @BP\[OFFS\], ACC
+ 29c:	1a 8e [ 	]*MOVE  @BP\[OFFS\], A\[AP\]
+ 29e:	0c 8e [ 	]*MOVE  @BP\[OFFS\], IP
+ 2a0:	0d 8e [ 	]*MOVE  @BP\[OFFS\], @SP\-\-
+ 2a2:	1d 8e [ 	]*MOVE  @BP\[OFFS\], SP
+ 2a4:	2d 8e [ 	]*MOVE  @BP\[OFFS\], IV
+ 2a6:	6d 8e [ 	]*MOVE  @BP\[OFFS\], LC\[0\]
+ 2a8:	7d 8e [ 	]*MOVE  @BP\[OFFS\], LC\[1\]
+ 2aa:	3e 8e [ 	]*MOVE  @BP\[OFFS\], OFFS
+ 2ac:	4e 8e [ 	]*MOVE  @BP\[OFFS\], DPC
+ 2ae:	5e 8e [ 	]*MOVE  @BP\[OFFS\], GR
+ 2b0:	6e 8e [ 	]*MOVE  @BP\[OFFS\], GRL
+ 2b2:	7e 8e [ 	]*MOVE  @BP\[OFFS\], BP
+ 2b4:	8e 8e [ 	]*MOVE  @BP\[OFFS\], GRS
+ 2b6:	9e 8e [ 	]*MOVE  @BP\[OFFS\], GRH
+ 2b8:	ae 8e [ 	]*MOVE  @BP\[OFFS\], GRXL
+ 2ba:	be 8e [ 	]*MOVE  @BP\[OFFS\], FP
+ 2bc:	0f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[0\]
+ 2be:	4f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[1\]
+ 2c0:	1f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[0\]\+\+
+ 2c2:	5f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[1\]\+\+
+ 2c4:	2f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[0\]\-\-
+ 2c6:	6f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[1\]\-\-
+ 2c8:	01 1e [ 	]*MOVE  @BP\[\+\+OFFS\], #01h
+ 2ca:	08 9e [ 	]*MOVE  @BP\[\+\+OFFS\], AP
+ 2cc:	18 9e [ 	]*MOVE  @BP\[\+\+OFFS\], APC
+ 2ce:	48 9e [ 	]*MOVE  @BP\[\+\+OFFS\], PSF
+ 2d0:	58 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IC
+ 2d2:	68 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IMR
+ 2d4:	88 9e [ 	]*MOVE  @BP\[\+\+OFFS\], SC
+ 2d6:	b8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IIR
+ 2d8:	e8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], CKCN
+ 2da:	f8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], WDCN
+ 2dc:	09 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[0\]
+ 2de:	f9 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[15\]
+ 2e0:	0a 9e [ 	]*MOVE  @BP\[\+\+OFFS\], ACC
+ 2e2:	1a 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[AP\]
+ 2e4:	0c 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IP
+ 2e6:	1d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], SP
+ 2e8:	2d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IV
+ 2ea:	6d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], LC\[0\]
+ 2ec:	7d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], LC\[1\]
+ 2ee:	3e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], OFFS
+ 2f0:	4e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], DPC
+ 2f2:	5e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GR
+ 2f4:	6e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRL
+ 2f6:	7e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], BP
+ 2f8:	8e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRS
+ 2fa:	9e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRH
+ 2fc:	ae 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRXL
+ 2fe:	be 9e [ 	]*MOVE  @BP\[\+\+OFFS\], FP
+ 300:	0f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]
+ 302:	4f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]
+ 304:	2f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]\-\-
+ 306:	6f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]\-\-
+ 308:	01 2e [ 	]*MOVE  @BP\[\-\-OFFS\], #01h
+ 30a:	08 ae [ 	]*MOVE  @BP\[\-\-OFFS\], AP
+ 30c:	18 ae [ 	]*MOVE  @BP\[\-\-OFFS\], APC
+ 30e:	48 ae [ 	]*MOVE  @BP\[\-\-OFFS\], PSF
+ 310:	58 ae [ 	]*MOVE  @BP\[\-\-OFFS\], IC
+ 312:	68 ae [ 	]*MOVE  @BP\[\-\-OFFS\], IMR
+ 314:	88 ae [ 	]*MOVE  @BP\[\-\-OFFS\], SC
+ 316:	b8 ae [ 	]*MOVE  @BP\[\-\-OFFS\], IIR
+ 318:	e8 ae [ 	]*MOVE  @BP\[\-\-OFFS\], CKCN
+ 31a:	f8 ae [ 	]*MOVE  @BP\[\-\-OFFS\], WDCN
+ 31c:	09 ae [ 	]*MOVE  @BP\[\-\-OFFS\], A\[0\]
+ 31e:	f9 ae [ 	]*MOVE  @BP\[\-\-OFFS\], A\[15\]
+ 320:	0a ae [ 	]*MOVE  @BP\[\-\-OFFS\], ACC
+ 322:	1a ae [ 	]*MOVE  @BP\[\-\-OFFS\], A\[AP\]
+ 324:	0c ae [ 	]*MOVE  @BP\[\-\-OFFS\], IP
+ 326:	1d ae [ 	]*MOVE  @BP\[\-\-OFFS\], SP
+ 328:	2d ae [ 	]*MOVE  @BP\[\-\-OFFS\], IV
+ 32a:	6d ae [ 	]*MOVE  @BP\[\-\-OFFS\], LC\[0\]
+ 32c:	7d ae [ 	]*MOVE  @BP\[\-\-OFFS\], LC\[1\]
+ 32e:	3e ae [ 	]*MOVE  @BP\[\-\-OFFS\], OFFS
+ 330:	4e ae [ 	]*MOVE  @BP\[\-\-OFFS\], DPC
+ 332:	5e ae [ 	]*MOVE  @BP\[\-\-OFFS\], GR
+ 334:	6e ae [ 	]*MOVE  @BP\[\-\-OFFS\], GRL
+ 336:	7e ae [ 	]*MOVE  @BP\[\-\-OFFS\], BP
+ 338:	8e ae [ 	]*MOVE  @BP\[\-\-OFFS\], GRS
+ 33a:	9e ae [ 	]*MOVE  @BP\[\-\-OFFS\], GRH
+ 33c:	ae ae [ 	]*MOVE  @BP\[\-\-OFFS\], GRXL
+ 33e:	be ae [ 	]*MOVE  @BP\[\-\-OFFS\], FP
+ 340:	0f ae [ 	]*MOVE  @BP\[\-\-OFFS\], @DP\[0\]
+ 342:	4f ae [ 	]*MOVE  @BP\[\-\-OFFS\], @DP\[1\]
+ 344:	01 3e [ 	]*MOVE  OFFS, #01h
+ 346:	08 be [ 	]*MOVE  OFFS, AP
+ 348:	18 be [ 	]*MOVE  OFFS, APC
+ 34a:	48 be [ 	]*MOVE  OFFS, PSF
+ 34c:	58 be [ 	]*MOVE  OFFS, IC
+ 34e:	68 be [ 	]*MOVE  OFFS, IMR
+ 350:	88 be [ 	]*MOVE  OFFS, SC
+ 352:	b8 be [ 	]*MOVE  OFFS, IIR
+ 354:	e8 be [ 	]*MOVE  OFFS, CKCN
+ 356:	f8 be [ 	]*MOVE  OFFS, WDCN
+ 358:	09 be [ 	]*MOVE  OFFS, A\[0\]
+ 35a:	f9 be [ 	]*MOVE  OFFS, A\[15\]
+ 35c:	0a be [ 	]*MOVE  OFFS, ACC
+ 35e:	1a be [ 	]*MOVE  OFFS, A\[AP\]
+ 360:	0c be [ 	]*MOVE  OFFS, IP
+ 362:	0d be [ 	]*MOVE  OFFS, @SP\-\-
+ 364:	1d be [ 	]*MOVE  OFFS, SP
+ 366:	2d be [ 	]*MOVE  OFFS, IV
+ 368:	6d be [ 	]*MOVE  OFFS, LC\[0\]
+ 36a:	7d be [ 	]*MOVE  OFFS, LC\[1\]
+ 36c:	4e be [ 	]*MOVE  OFFS, DPC
+ 36e:	5e be [ 	]*MOVE  OFFS, GR
+ 370:	6e be [ 	]*MOVE  OFFS, GRL
+ 372:	7e be [ 	]*MOVE  OFFS, BP
+ 374:	8e be [ 	]*MOVE  OFFS, GRS
+ 376:	9e be [ 	]*MOVE  OFFS, GRH
+ 378:	ae be [ 	]*MOVE  OFFS, GRXL
+ 37a:	be be [ 	]*MOVE  OFFS, FP
+ 37c:	0f be [ 	]*MOVE  OFFS, @DP\[0\]
+ 37e:	4f be [ 	]*MOVE  OFFS, @DP\[1\]
+ 380:	1f be [ 	]*MOVE  OFFS, @DP\[0\]\+\+
+ 382:	5f be [ 	]*MOVE  OFFS, @DP\[1\]\+\+
+ 384:	2f be [ 	]*MOVE  OFFS, @DP\[0\]\-\-
+ 386:	6f be [ 	]*MOVE  OFFS, @DP\[1\]\-\-
diff --git a/gas/testsuite/gas/maxq20/data2.s b/gas/testsuite/gas/maxq20/data2.s
new file mode 100644
index 0000000..94cc70b
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/data2.s
@@ -0,0 +1,455 @@
+;# data.s	
+;# checks all the data transfer instructions
+foo:
+	MOVE PSF, #01h
+	MOVE PSF, AP
+	MOVE PSF, APC
+	MOVE PSF, IC
+	MOVE PSF, IMR
+	MOVE PSF, SC
+	MOVE PSF, IIR
+	MOVE PSF, CKCN
+	MOVE PSF, WDCN
+	MOVE PSF, A[0]		;Just Check two boundary conditions
+	MOVE PSF, A[15]   
+	MOVE PSF, ACC
+	MOVE PSF, A[AP]
+	MOVE PSF, IP
+	MOVE PSF, @SP--
+	MOVE PSF, SP
+	MOVE PSF, IV
+	MOVE PSF, LC[0]
+	MOVE PSF, LC[1]
+	MOVE PSF, @BP[OFFS++]
+	MOVE PSF, @BP[OFFS--]
+	MOVE PSF, OFFS
+	MOVE PSF, DPC
+	MOVE PSF, GR
+	MOVE PSF, GRL
+	MOVE PSF, BP
+	MOVE PSF, GRS
+	MOVE PSF, GRH
+	MOVE PSF, GRXL
+	MOVE PSF, FP
+	MOVE PSF, @DP[0]	
+	MOVE PSF, @DP[1]	
+	MOVE PSF, @DP[0]++		
+	MOVE PSF, @DP[1]++
+	MOVE PSF, @DP[0]--
+	MOVE PSF, @DP[1]--
+	MOVE IC, #01h
+	MOVE IC, AP
+	MOVE IC, APC
+	MOVE IC, PSF
+	MOVE IC, IMR
+	MOVE IC, SC
+	MOVE IC, IIR
+	MOVE IC, CKCN
+	MOVE IC, WDCN
+	MOVE IC, A[0]		;Just Check two boundary conditions
+	MOVE IC, A[15]   
+	MOVE IC, ACC
+	MOVE IC, A[AP]
+	MOVE IC, IP
+	MOVE IC, @SP--
+	MOVE IC, SP
+	MOVE IC, IV
+	MOVE IC, LC[0]
+	MOVE IC, LC[1]
+	MOVE IC, @BP[OFFS++]
+	MOVE IC, @BP[OFFS--]
+	MOVE IC, OFFS
+	MOVE IC, DPC
+	MOVE IC, GR
+	MOVE IC, GRL
+	MOVE IC, BP
+	MOVE IC, GRS
+	MOVE IC, GRH
+	MOVE IC, GRXL
+	MOVE IC, FP
+	MOVE IC, @DP[0]	
+	MOVE IC, @DP[1]	
+	MOVE IC, @DP[0]++		
+	MOVE IC, @DP[1]++
+	MOVE IC, @DP[0]--
+	MOVE IC, @DP[1]--
+	MOVE IMR, #01h
+	MOVE IMR, AP
+	MOVE IMR, APC
+	MOVE IMR, PSF
+	MOVE IMR, IC
+	MOVE IMR, SC
+	MOVE IMR, IIR
+	MOVE IMR, CKCN
+	MOVE IMR, WDCN
+	MOVE IMR, A[0]		;Just Check two boundary conditions
+	MOVE IMR, A[15]   
+	MOVE IMR, ACC
+	MOVE IMR, A[AP]
+	MOVE IMR, IP
+	MOVE IMR, @SP--
+	MOVE IMR, SP
+	MOVE IMR, IV
+	MOVE IMR, LC[0]
+	MOVE IMR, LC[1]
+	MOVE IMR, @BP[OFFS++]
+	MOVE IMR, @BP[OFFS--]
+	MOVE IMR, OFFS
+	MOVE IMR, DPC
+	MOVE IMR, GR
+	MOVE IMR, GRL
+	MOVE IMR, BP
+	MOVE IMR, GRS
+	MOVE IMR, GRH
+	MOVE IMR, GRXL
+	MOVE IMR, FP
+	MOVE IMR, @DP[0]	
+	MOVE IMR, @DP[1]	
+	MOVE IMR, @DP[0]++		
+	MOVE IMR, @DP[1]++
+	MOVE IMR, @DP[0]--
+	MOVE IMR, @DP[1]--
+	MOVE A[0], #01h
+	MOVE A[0], AP
+	MOVE A[0], APC
+	MOVE A[0], PSF
+	MOVE A[0], IC
+	MOVE A[0], IMR
+	MOVE A[0], SC
+	MOVE A[0], IIR
+	MOVE A[0], CKCN
+	MOVE A[0], WDCN
+	MOVE A[0], ACC
+	MOVE A[0], A[AP]
+	MOVE A[0], IP
+	MOVE A[0], @SP--
+	MOVE A[0], SP
+	MOVE A[0], IV
+	MOVE A[0], LC[0]
+	MOVE A[0], LC[1]
+	MOVE A[0], @BP[OFFS++]
+	MOVE A[0], @BP[OFFS--]
+	MOVE A[0], OFFS
+	MOVE A[0], DPC
+	MOVE A[0], GR
+	MOVE A[0], GRL
+	MOVE A[0], BP
+	MOVE A[0], GRS
+	MOVE A[0], GRH
+	MOVE A[0], GRXL
+	MOVE A[0], FP
+	MOVE A[0], @DP[0]	
+	MOVE A[0], @DP[1]	
+	MOVE A[0], @DP[0]++		
+	MOVE A[0], @DP[1]++
+	MOVE A[0], @DP[0]--
+	MOVE A[0], @DP[1]--
+	MOVE ACC, #01h
+	MOVE ACC, AP
+	MOVE ACC, APC
+	MOVE ACC, PSF
+	MOVE ACC, IC
+	MOVE ACC, IMR
+	MOVE ACC, SC
+	MOVE ACC, IIR
+	MOVE ACC, CKCN
+	MOVE ACC, WDCN
+	MOVE ACC, A[0]		;Just Check two boundary conditions
+	MOVE ACC, A[15]   
+	MOVE ACC, IP
+	MOVE ACC, @SP--
+	MOVE ACC, SP
+	MOVE ACC, IV
+	MOVE ACC, LC[0]
+	MOVE ACC, LC[1]
+	MOVE ACC, @BP[OFFS++]
+	MOVE ACC, @BP[OFFS--]
+	MOVE ACC, OFFS
+	MOVE ACC, DPC
+	MOVE ACC, GR
+	MOVE ACC, GRL
+	MOVE ACC, BP
+	MOVE ACC, GRS
+	MOVE ACC, GRH
+	MOVE ACC, GRXL
+	MOVE ACC, FP
+	MOVE ACC, @DP[0]	
+	MOVE ACC, @DP[1]	
+	MOVE ACC, @DP[0]++		
+	MOVE ACC, @DP[1]++
+	MOVE ACC, @DP[0]--
+	MOVE ACC, @DP[1]--
+	MOVE @++SP, #01h
+	MOVE @++SP, AP
+	MOVE @++SP, APC
+	MOVE @++SP, PSF
+	MOVE @++SP, IC
+	MOVE @++SP, IMR
+	MOVE @++SP, SC
+	MOVE @++SP, IIR
+	MOVE @++SP, CKCN
+	MOVE @++SP, WDCN
+	MOVE @++SP, A[0]		;Just Check two boundary conditions
+	MOVE @++SP, A[15]   
+	MOVE @++SP, ACC
+	MOVE @++SP, A[AP]
+	MOVE @++SP, IP
+	MOVE @++SP, SP
+	MOVE @++SP, IV
+	MOVE @++SP, LC[0]
+	MOVE @++SP, LC[1]
+	MOVE @++SP, @BP[OFFS++]
+	MOVE @++SP, @BP[OFFS--]
+	MOVE @++SP, OFFS
+	MOVE @++SP, DPC
+	MOVE @++SP, GR
+	MOVE @++SP, GRL
+	MOVE @++SP, BP
+	MOVE @++SP, GRS
+	MOVE @++SP, GRH
+	MOVE @++SP, GRXL
+	MOVE @++SP, FP
+	MOVE @++SP, @DP[0]	
+	MOVE @++SP, @DP[1]	
+	MOVE @++SP, @DP[0]++		
+	MOVE @++SP, @DP[1]++
+	MOVE @++SP, @DP[0]--
+	MOVE @++SP, @DP[1]--
+	MOVE SP, #01h
+	MOVE SP, AP
+	MOVE SP, APC
+	MOVE SP, PSF
+	MOVE SP, IC
+	MOVE SP, IMR
+	MOVE SP, SC
+	MOVE SP, IIR
+	MOVE SP, CKCN
+	MOVE SP, WDCN
+	MOVE SP, A[0]		;Just Check two boundary conditions
+	MOVE SP, A[15]   
+	MOVE SP, ACC
+	MOVE SP, A[AP]
+	MOVE SP, IP
+	MOVE SP, IV
+	MOVE SP, LC[0]
+	MOVE SP, LC[1]
+	MOVE SP, @BP[OFFS++]
+	MOVE SP, @BP[OFFS--]
+	MOVE SP, OFFS
+	MOVE SP, DPC
+	MOVE SP, GR
+	MOVE SP, GRL
+	MOVE SP, BP
+	MOVE SP, GRS
+	MOVE SP, GRH
+	MOVE SP, GRXL
+	MOVE SP, FP
+	MOVE SP, @DP[0]	
+	MOVE SP, @DP[1]	
+	MOVE SP, @DP[0]++		
+	MOVE SP, @DP[1]++
+	MOVE SP, @DP[0]--
+	MOVE SP, @DP[1]--
+	MOVE IV, #01h
+	MOVE IV, AP
+	MOVE IV, APC
+	MOVE IV, PSF
+	MOVE IV, IC
+	MOVE IV, IMR
+	MOVE IV, SC
+	MOVE IV, IIR
+	MOVE IV, CKCN
+	MOVE IV, WDCN
+	MOVE IV, A[0]		;Just Check two boundary conditions
+	MOVE IV, A[15]   
+	MOVE IV, ACC
+	MOVE IV, A[AP]
+	MOVE IV, IP
+	MOVE IV, @SP--
+	MOVE IV, SP
+	MOVE IV, IV
+	MOVE IV, LC[0]
+	MOVE IV, LC[1]
+	MOVE IV, @BP[OFFS++]
+	MOVE IV, @BP[OFFS--]
+	MOVE IV, OFFS
+	MOVE IV, DPC
+	MOVE IV, GR
+	MOVE IV, GRL
+	MOVE IV, BP
+	MOVE IV, GRS
+	MOVE IV, GRH
+	MOVE IV, GRXL
+	MOVE IV, FP
+	MOVE IV, @DP[0]	
+	MOVE IV, @DP[1]	
+	MOVE IV, @DP[0]++		
+	MOVE IV, @DP[1]++
+	MOVE IV, @DP[0]--
+	MOVE IV, @DP[1]--
+	MOVE LC[0], #01h
+	MOVE LC[0], AP
+	MOVE LC[0], APC
+	MOVE LC[0], PSF
+	MOVE LC[0], IC
+	MOVE LC[0], IMR
+	MOVE LC[0], SC
+	MOVE LC[0], IIR
+	MOVE LC[0], CKCN
+	MOVE LC[0], WDCN
+	MOVE LC[0], A[0]		;Just Check two boundary conditions
+	MOVE LC[0], A[15]   
+	MOVE LC[0], ACC
+	MOVE LC[0], A[AP]
+	MOVE LC[0], IP
+	MOVE LC[0], @SP--
+	MOVE LC[0], SP
+	MOVE LC[0], IV
+	MOVE LC[0], @BP[OFFS++]
+	MOVE LC[0], @BP[OFFS--]
+	MOVE LC[0], OFFS
+	MOVE LC[0], DPC
+	MOVE LC[0], GR
+	MOVE LC[0], GRL
+	MOVE LC[0], BP
+	MOVE LC[0], GRS
+	MOVE LC[0], GRH
+	MOVE LC[0], GRXL
+	MOVE LC[0], FP
+	MOVE LC[0], @DP[0]	
+	MOVE LC[0], @DP[1]	
+	MOVE LC[0], @DP[0]++		
+	MOVE LC[0], @DP[1]++
+	MOVE LC[0], @DP[0]--
+	MOVE LC[0], @DP[1]--
+	MOVE @BP[OFFS], #01h
+	MOVE @BP[OFFS], AP
+	MOVE @BP[OFFS], APC
+	MOVE @BP[OFFS], PSF
+	MOVE @BP[OFFS], IC
+	MOVE @BP[OFFS], IMR
+	MOVE @BP[OFFS], SC
+	MOVE @BP[OFFS], IIR
+	MOVE @BP[OFFS], CKCN
+	MOVE @BP[OFFS], WDCN
+	MOVE @BP[OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[OFFS], A[15]   
+	MOVE @BP[OFFS], ACC
+	MOVE @BP[OFFS], A[AP]
+	MOVE @BP[OFFS], IP
+	MOVE @BP[OFFS], @SP--
+	MOVE @BP[OFFS], SP
+	MOVE @BP[OFFS], IV
+	MOVE @BP[OFFS], LC[0]
+	MOVE @BP[OFFS], LC[1]
+	MOVE @BP[OFFS], OFFS
+	MOVE @BP[OFFS], DPC
+	MOVE @BP[OFFS], GR
+	MOVE @BP[OFFS], GRL
+	MOVE @BP[OFFS], BP
+	MOVE @BP[OFFS], GRS
+	MOVE @BP[OFFS], GRH
+	MOVE @BP[OFFS], GRXL
+	MOVE @BP[OFFS], FP
+	MOVE @BP[OFFS], @DP[0]	
+	MOVE @BP[OFFS], @DP[1]	
+	MOVE @BP[OFFS], @DP[0]++		
+	MOVE @BP[OFFS], @DP[1]++
+	MOVE @BP[OFFS], @DP[0]--
+	MOVE @BP[OFFS], @DP[1]--
+	MOVE @BP[++OFFS], #01h
+	MOVE @BP[++OFFS], AP
+	MOVE @BP[++OFFS], APC
+	MOVE @BP[++OFFS], PSF
+	MOVE @BP[++OFFS], IC
+	MOVE @BP[++OFFS], IMR
+	MOVE @BP[++OFFS], SC
+	MOVE @BP[++OFFS], IIR
+	MOVE @BP[++OFFS], CKCN
+	MOVE @BP[++OFFS], WDCN
+	MOVE @BP[++OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[++OFFS], A[15]   
+	MOVE @BP[++OFFS], ACC
+	MOVE @BP[++OFFS], A[AP]
+	MOVE @BP[++OFFS], IP
+	MOVE @BP[++OFFS], SP
+	MOVE @BP[++OFFS], IV
+	MOVE @BP[++OFFS], LC[0]
+	MOVE @BP[++OFFS], LC[1]
+	MOVE @BP[++OFFS], OFFS
+	MOVE @BP[++OFFS], DPC
+	MOVE @BP[++OFFS], GR
+	MOVE @BP[++OFFS], GRL
+	MOVE @BP[++OFFS], BP
+	MOVE @BP[++OFFS], GRS
+	MOVE @BP[++OFFS], GRH
+	MOVE @BP[++OFFS], GRXL
+	MOVE @BP[++OFFS], FP
+	MOVE @BP[++OFFS], @DP[0]	
+	MOVE @BP[++OFFS], @DP[1]	
+	MOVE @BP[++OFFS], @DP[0]--
+	MOVE @BP[++OFFS], @DP[1]--
+	MOVE @BP[--OFFS], #01h
+	MOVE @BP[--OFFS], AP
+	MOVE @BP[--OFFS], APC
+	MOVE @BP[--OFFS], PSF
+	MOVE @BP[--OFFS], IC
+	MOVE @BP[--OFFS], IMR
+	MOVE @BP[--OFFS], SC
+	MOVE @BP[--OFFS], IIR
+	MOVE @BP[--OFFS], CKCN
+	MOVE @BP[--OFFS], WDCN
+	MOVE @BP[--OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[--OFFS], A[15]   
+	MOVE @BP[--OFFS], ACC
+	MOVE @BP[--OFFS], A[AP]
+	MOVE @BP[--OFFS], IP
+	MOVE @BP[--OFFS], SP
+	MOVE @BP[--OFFS], IV
+	MOVE @BP[--OFFS], LC[0]
+	MOVE @BP[--OFFS], LC[1]
+	MOVE @BP[--OFFS], OFFS
+	MOVE @BP[--OFFS], DPC
+	MOVE @BP[--OFFS], GR
+	MOVE @BP[--OFFS], GRL
+	MOVE @BP[--OFFS], BP
+	MOVE @BP[--OFFS], GRS
+	MOVE @BP[--OFFS], GRH
+	MOVE @BP[--OFFS], GRXL
+	MOVE @BP[--OFFS], FP
+	MOVE @BP[--OFFS], @DP[0]	
+	MOVE @BP[--OFFS], @DP[1]	
+	MOVE OFFS, #01h
+	MOVE OFFS, AP
+	MOVE OFFS, APC
+	MOVE OFFS, PSF
+	MOVE OFFS, IC
+	MOVE OFFS, IMR
+	MOVE OFFS, SC
+	MOVE OFFS, IIR
+	MOVE OFFS, CKCN
+	MOVE OFFS, WDCN
+	MOVE OFFS, A[0]		;Just Check two boundary conditions
+	MOVE OFFS, A[15]   
+	MOVE OFFS, ACC
+	MOVE OFFS, A[AP]
+	MOVE OFFS, IP
+	MOVE OFFS, @SP--
+	MOVE OFFS, SP
+	MOVE OFFS, IV
+	MOVE OFFS, LC[0]
+	MOVE OFFS, LC[1]
+	MOVE OFFS, DPC
+	MOVE OFFS, GR
+	MOVE OFFS, GRL
+	MOVE OFFS, BP
+	MOVE OFFS, GRS
+	MOVE OFFS, GRH
+	MOVE OFFS, GRXL
+	MOVE OFFS, FP
+	MOVE OFFS, @DP[0]	
+	MOVE OFFS, @DP[1]	
+	MOVE OFFS, @DP[0]++		
+	MOVE OFFS, @DP[1]++
+	MOVE OFFS, @DP[0]--
+	MOVE OFFS, @DP[1]--
diff --git a/gas/testsuite/gas/maxq20/data3.d b/gas/testsuite/gas/maxq20/data3.d
new file mode 100644
index 0000000..517abb6
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/data3.d
@@ -0,0 +1,491 @@
+#objdump: -dw
+#name: 3rd Move operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	01 4e [ 	]*MOVE  DPC, #01h
+   2:	08 ce [ 	]*MOVE  DPC, AP
+   4:	18 ce [ 	]*MOVE  DPC, APC
+   6:	48 ce [ 	]*MOVE  DPC, PSF
+   8:	58 ce [ 	]*MOVE  DPC, IC
+   a:	68 ce [ 	]*MOVE  DPC, IMR
+   c:	88 ce [ 	]*MOVE  DPC, SC
+   e:	b8 ce [ 	]*MOVE  DPC, IIR
+  10:	e8 ce [ 	]*MOVE  DPC, CKCN
+  12:	f8 ce [ 	]*MOVE  DPC, WDCN
+  14:	09 ce [ 	]*MOVE  DPC, A\[0\]
+  16:	f9 ce [ 	]*MOVE  DPC, A\[15\]
+  18:	0a ce [ 	]*MOVE  DPC, ACC
+  1a:	1a ce [ 	]*MOVE  DPC, A\[AP\]
+  1c:	0c ce [ 	]*MOVE  DPC, IP
+  1e:	0d ce [ 	]*MOVE  DPC, @SP\-\-
+  20:	1d ce [ 	]*MOVE  DPC, SP
+  22:	2d ce [ 	]*MOVE  DPC, IV
+  24:	6d ce [ 	]*MOVE  DPC, LC\[0\]
+  26:	7d ce [ 	]*MOVE  DPC, LC\[1\]
+  28:	1e ce [ 	]*MOVE  DPC, @BP\[OFFS\+\+\]
+  2a:	2e ce [ 	]*MOVE  DPC, @BP\[OFFS\-\-\]
+  2c:	3e ce [ 	]*MOVE  DPC, OFFS
+  2e:	5e ce [ 	]*MOVE  DPC, GR
+  30:	6e ce [ 	]*MOVE  DPC, GRL
+  32:	7e ce [ 	]*MOVE  DPC, BP
+  34:	8e ce [ 	]*MOVE  DPC, GRS
+  36:	9e ce [ 	]*MOVE  DPC, GRH
+  38:	ae ce [ 	]*MOVE  DPC, GRXL
+  3a:	be ce [ 	]*MOVE  DPC, FP
+  3c:	0f ce [ 	]*MOVE  DPC, @DP\[0\]
+  3e:	4f ce [ 	]*MOVE  DPC, @DP\[1\]
+  40:	1f ce [ 	]*MOVE  DPC, @DP\[0\]\+\+
+  42:	5f ce [ 	]*MOVE  DPC, @DP\[1\]\+\+
+  44:	2f ce [ 	]*MOVE  DPC, @DP\[0\]\-\-
+  46:	6f ce [ 	]*MOVE  DPC, @DP\[1\]\-\-
+  48:	01 5e [ 	]*MOVE  GR, #01h
+  4a:	08 de [ 	]*MOVE  GR, AP
+  4c:	18 de [ 	]*MOVE  GR, APC
+  4e:	48 de [ 	]*MOVE  GR, PSF
+  50:	58 de [ 	]*MOVE  GR, IC
+  52:	68 de [ 	]*MOVE  GR, IMR
+  54:	88 de [ 	]*MOVE  GR, SC
+  56:	b8 de [ 	]*MOVE  GR, IIR
+  58:	e8 de [ 	]*MOVE  GR, CKCN
+  5a:	f8 de [ 	]*MOVE  GR, WDCN
+  5c:	09 de [ 	]*MOVE  GR, A\[0\]
+  5e:	f9 de [ 	]*MOVE  GR, A\[15\]
+  60:	0a de [ 	]*MOVE  GR, ACC
+  62:	1a de [ 	]*MOVE  GR, A\[AP\]
+  64:	0c de [ 	]*MOVE  GR, IP
+  66:	0d de [ 	]*MOVE  GR, @SP\-\-
+  68:	1d de [ 	]*MOVE  GR, SP
+  6a:	2d de [ 	]*MOVE  GR, IV
+  6c:	6d de [ 	]*MOVE  GR, LC\[0\]
+  6e:	7d de [ 	]*MOVE  GR, LC\[1\]
+  70:	1e de [ 	]*MOVE  GR, @BP\[OFFS\+\+\]
+  72:	2e de [ 	]*MOVE  GR, @BP\[OFFS\-\-\]
+  74:	3e de [ 	]*MOVE  GR, OFFS
+  76:	4e de [ 	]*MOVE  GR, DPC
+  78:	6e de [ 	]*MOVE  GR, GRL
+  7a:	7e de [ 	]*MOVE  GR, BP
+  7c:	8e de [ 	]*MOVE  GR, GRS
+  7e:	9e de [ 	]*MOVE  GR, GRH
+  80:	ae de [ 	]*MOVE  GR, GRXL
+  82:	be de [ 	]*MOVE  GR, FP
+  84:	0f de [ 	]*MOVE  GR, @DP\[0\]
+  86:	4f de [ 	]*MOVE  GR, @DP\[1\]
+  88:	1f de [ 	]*MOVE  GR, @DP\[0\]\+\+
+  8a:	5f de [ 	]*MOVE  GR, @DP\[1\]\+\+
+  8c:	2f de [ 	]*MOVE  GR, @DP\[0\]\-\-
+  8e:	6f de [ 	]*MOVE  GR, @DP\[1\]\-\-
+  90:	01 6e [ 	]*MOVE  GRL, #01h
+  92:	08 ee [ 	]*MOVE  GRL, AP
+  94:	18 ee [ 	]*MOVE  GRL, APC
+  96:	48 ee [ 	]*MOVE  GRL, PSF
+  98:	58 ee [ 	]*MOVE  GRL, IC
+  9a:	68 ee [ 	]*MOVE  GRL, IMR
+  9c:	88 ee [ 	]*MOVE  GRL, SC
+  9e:	b8 ee [ 	]*MOVE  GRL, IIR
+  a0:	e8 ee [ 	]*MOVE  GRL, CKCN
+  a2:	f8 ee [ 	]*MOVE  GRL, WDCN
+  a4:	09 ee [ 	]*MOVE  GRL, A\[0\]
+  a6:	f9 ee [ 	]*MOVE  GRL, A\[15\]
+  a8:	0a ee [ 	]*MOVE  GRL, ACC
+  aa:	1a ee [ 	]*MOVE  GRL, A\[AP\]
+  ac:	0c ee [ 	]*MOVE  GRL, IP
+  ae:	0d ee [ 	]*MOVE  GRL, @SP\-\-
+  b0:	1d ee [ 	]*MOVE  GRL, SP
+  b2:	2d ee [ 	]*MOVE  GRL, IV
+  b4:	6d ee [ 	]*MOVE  GRL, LC\[0\]
+  b6:	7d ee [ 	]*MOVE  GRL, LC\[1\]
+  b8:	1e ee [ 	]*MOVE  GRL, @BP\[OFFS\+\+\]
+  ba:	2e ee [ 	]*MOVE  GRL, @BP\[OFFS\-\-\]
+  bc:	3e ee [ 	]*MOVE  GRL, OFFS
+  be:	4e ee [ 	]*MOVE  GRL, DPC
+  c0:	5e ee [ 	]*MOVE  GRL, GR
+  c2:	7e ee [ 	]*MOVE  GRL, BP
+  c4:	8e ee [ 	]*MOVE  GRL, GRS
+  c6:	9e ee [ 	]*MOVE  GRL, GRH
+  c8:	ae ee [ 	]*MOVE  GRL, GRXL
+  ca:	be ee [ 	]*MOVE  GRL, FP
+  cc:	0f ee [ 	]*MOVE  GRL, @DP\[0\]
+  ce:	4f ee [ 	]*MOVE  GRL, @DP\[1\]
+  d0:	1f ee [ 	]*MOVE  GRL, @DP\[0\]\+\+
+  d2:	5f ee [ 	]*MOVE  GRL, @DP\[1\]\+\+
+  d4:	2f ee [ 	]*MOVE  GRL, @DP\[0\]\-\-
+  d6:	6f ee [ 	]*MOVE  GRL, @DP\[1\]\-\-
+  d8:	01 7e [ 	]*MOVE  BP, #01h
+  da:	08 fe [ 	]*MOVE  BP, AP
+  dc:	18 fe [ 	]*MOVE  BP, APC
+  de:	48 fe [ 	]*MOVE  BP, PSF
+  e0:	58 fe [ 	]*MOVE  BP, IC
+  e2:	68 fe [ 	]*MOVE  BP, IMR
+  e4:	88 fe [ 	]*MOVE  BP, SC
+  e6:	b8 fe [ 	]*MOVE  BP, IIR
+  e8:	e8 fe [ 	]*MOVE  BP, CKCN
+  ea:	f8 fe [ 	]*MOVE  BP, WDCN
+  ec:	09 fe [ 	]*MOVE  BP, A\[0\]
+  ee:	f9 fe [ 	]*MOVE  BP, A\[15\]
+  f0:	0a fe [ 	]*MOVE  BP, ACC
+  f2:	1a fe [ 	]*MOVE  BP, A\[AP\]
+  f4:	0c fe [ 	]*MOVE  BP, IP
+  f6:	0d fe [ 	]*MOVE  BP, @SP\-\-
+  f8:	1d fe [ 	]*MOVE  BP, SP
+  fa:	2d fe [ 	]*MOVE  BP, IV
+  fc:	6d fe [ 	]*MOVE  BP, LC\[0\]
+  fe:	7d fe [ 	]*MOVE  BP, LC\[1\]
+ 100:	1e fe [ 	]*MOVE  BP, @BP\[OFFS\+\+\]
+ 102:	2e fe [ 	]*MOVE  BP, @BP\[OFFS\-\-\]
+ 104:	3e fe [ 	]*MOVE  BP, OFFS
+ 106:	4e fe [ 	]*MOVE  BP, DPC
+ 108:	5e fe [ 	]*MOVE  BP, GR
+ 10a:	6e fe [ 	]*MOVE  BP, GRL
+ 10c:	8e fe [ 	]*MOVE  BP, GRS
+ 10e:	9e fe [ 	]*MOVE  BP, GRH
+ 110:	ae fe [ 	]*MOVE  BP, GRXL
+ 112:	be fe [ 	]*MOVE  BP, FP
+ 114:	0f fe [ 	]*MOVE  BP, @DP\[0\]
+ 116:	4f fe [ 	]*MOVE  BP, @DP\[1\]
+ 118:	1f fe [ 	]*MOVE  BP, @DP\[0\]\+\+
+ 11a:	5f fe [ 	]*MOVE  BP, @DP\[1\]\+\+
+ 11c:	2f fe [ 	]*MOVE  BP, @DP\[0\]\-\-
+ 11e:	6f fe [ 	]*MOVE  BP, @DP\[1\]\-\-
+ 120:	01 0f [ 	]*MOVE  @DP\[0\], #01h
+ 122:	08 8f [ 	]*MOVE  @DP\[0\], AP
+ 124:	18 8f [ 	]*MOVE  @DP\[0\], APC
+ 126:	48 8f [ 	]*MOVE  @DP\[0\], PSF
+ 128:	58 8f [ 	]*MOVE  @DP\[0\], IC
+ 12a:	68 8f [ 	]*MOVE  @DP\[0\], IMR
+ 12c:	88 8f [ 	]*MOVE  @DP\[0\], SC
+ 12e:	b8 8f [ 	]*MOVE  @DP\[0\], IIR
+ 130:	e8 8f [ 	]*MOVE  @DP\[0\], CKCN
+ 132:	f8 8f [ 	]*MOVE  @DP\[0\], WDCN
+ 134:	09 8f [ 	]*MOVE  @DP\[0\], A\[0\]
+ 136:	f9 8f [ 	]*MOVE  @DP\[0\], A\[15\]
+ 138:	0a 8f [ 	]*MOVE  @DP\[0\], ACC
+ 13a:	1a 8f [ 	]*MOVE  @DP\[0\], A\[AP\]
+ 13c:	0c 8f [ 	]*MOVE  @DP\[0\], IP
+ 13e:	0d 8f [ 	]*MOVE  @DP\[0\], @SP\-\-
+ 140:	1d 8f [ 	]*MOVE  @DP\[0\], SP
+ 142:	2d 8f [ 	]*MOVE  @DP\[0\], IV
+ 144:	6d 8f [ 	]*MOVE  @DP\[0\], LC\[0\]
+ 146:	7d 8f [ 	]*MOVE  @DP\[0\], LC\[1\]
+ 148:	1e 8f [ 	]*MOVE  @DP\[0\], @BP\[OFFS\+\+\]
+ 14a:	2e 8f [ 	]*MOVE  @DP\[0\], @BP\[OFFS\-\-\]
+ 14c:	3e 8f [ 	]*MOVE  @DP\[0\], OFFS
+ 14e:	4e 8f [ 	]*MOVE  @DP\[0\], DPC
+ 150:	5e 8f [ 	]*MOVE  @DP\[0\], GR
+ 152:	6e 8f [ 	]*MOVE  @DP\[0\], GRL
+ 154:	7e 8f [ 	]*MOVE  @DP\[0\], BP
+ 156:	8e 8f [ 	]*MOVE  @DP\[0\], GRS
+ 158:	9e 8f [ 	]*MOVE  @DP\[0\], GRH
+ 15a:	ae 8f [ 	]*MOVE  @DP\[0\], GRXL
+ 15c:	be 8f [ 	]*MOVE  @DP\[0\], FP
+ 15e:	01 1f [ 	]*MOVE  @\+\+DP\[0\], #01h
+ 160:	08 9f [ 	]*MOVE  @\+\+DP\[0\], AP
+ 162:	18 9f [ 	]*MOVE  @\+\+DP\[0\], APC
+ 164:	48 9f [ 	]*MOVE  @\+\+DP\[0\], PSF
+ 166:	58 9f [ 	]*MOVE  @\+\+DP\[0\], IC
+ 168:	68 9f [ 	]*MOVE  @\+\+DP\[0\], IMR
+ 16a:	88 9f [ 	]*MOVE  @\+\+DP\[0\], SC
+ 16c:	b8 9f [ 	]*MOVE  @\+\+DP\[0\], IIR
+ 16e:	e8 9f [ 	]*MOVE  @\+\+DP\[0\], CKCN
+ 170:	f8 9f [ 	]*MOVE  @\+\+DP\[0\], WDCN
+ 172:	09 9f [ 	]*MOVE  @\+\+DP\[0\], A\[0\]
+ 174:	f9 9f [ 	]*MOVE  @\+\+DP\[0\], A\[15\]
+ 176:	0a 9f [ 	]*MOVE  @\+\+DP\[0\], ACC
+ 178:	1a 9f [ 	]*MOVE  @\+\+DP\[0\], A\[AP\]
+ 17a:	0c 9f [ 	]*MOVE  @\+\+DP\[0\], IP
+ 17c:	0d 9f [ 	]*MOVE  @\+\+DP\[0\], @SP\-\-
+ 17e:	1d 9f [ 	]*MOVE  @\+\+DP\[0\], SP
+ 180:	2d 9f [ 	]*MOVE  @\+\+DP\[0\], IV
+ 182:	6d 9f [ 	]*MOVE  @\+\+DP\[0\], LC\[0\]
+ 184:	7d 9f [ 	]*MOVE  @\+\+DP\[0\], LC\[1\]
+ 186:	1e 9f [ 	]*MOVE  @\+\+DP\[0\], @BP\[OFFS\+\+\]
+ 188:	2e 9f [ 	]*MOVE  @\+\+DP\[0\], @BP\[OFFS\-\-\]
+ 18a:	3e 9f [ 	]*MOVE  @\+\+DP\[0\], OFFS
+ 18c:	4e 9f [ 	]*MOVE  @\+\+DP\[0\], DPC
+ 18e:	5e 9f [ 	]*MOVE  @\+\+DP\[0\], GR
+ 190:	6e 9f [ 	]*MOVE  @\+\+DP\[0\], GRL
+ 192:	7e 9f [ 	]*MOVE  @\+\+DP\[0\], BP
+ 194:	8e 9f [ 	]*MOVE  @\+\+DP\[0\], GRS
+ 196:	9e 9f [ 	]*MOVE  @\+\+DP\[0\], GRH
+ 198:	ae 9f [ 	]*MOVE  @\+\+DP\[0\], GRXL
+ 19a:	be 9f [ 	]*MOVE  @\+\+DP\[0\], FP
+ 19c:	01 2f [ 	]*MOVE  @\-\-DP\[0\], #01h
+ 19e:	08 af [ 	]*MOVE  @\-\-DP\[0\], AP
+ 1a0:	18 af [ 	]*MOVE  @\-\-DP\[0\], APC
+ 1a2:	48 af [ 	]*MOVE  @\-\-DP\[0\], PSF
+ 1a4:	58 af [ 	]*MOVE  @\-\-DP\[0\], IC
+ 1a6:	68 af [ 	]*MOVE  @\-\-DP\[0\], IMR
+ 1a8:	88 af [ 	]*MOVE  @\-\-DP\[0\], SC
+ 1aa:	b8 af [ 	]*MOVE  @\-\-DP\[0\], IIR
+ 1ac:	e8 af [ 	]*MOVE  @\-\-DP\[0\], CKCN
+ 1ae:	f8 af [ 	]*MOVE  @\-\-DP\[0\], WDCN
+ 1b0:	09 af [ 	]*MOVE  @\-\-DP\[0\], A\[0\]
+ 1b2:	f9 af [ 	]*MOVE  @\-\-DP\[0\], A\[15\]
+ 1b4:	0a af [ 	]*MOVE  @\-\-DP\[0\], ACC
+ 1b6:	1a af [ 	]*MOVE  @\-\-DP\[0\], A\[AP\]
+ 1b8:	0c af [ 	]*MOVE  @\-\-DP\[0\], IP
+ 1ba:	0d af [ 	]*MOVE  @\-\-DP\[0\], @SP\-\-
+ 1bc:	1d af [ 	]*MOVE  @\-\-DP\[0\], SP
+ 1be:	2d af [ 	]*MOVE  @\-\-DP\[0\], IV
+ 1c0:	6d af [ 	]*MOVE  @\-\-DP\[0\], LC\[0\]
+ 1c2:	7d af [ 	]*MOVE  @\-\-DP\[0\], LC\[1\]
+ 1c4:	1e af [ 	]*MOVE  @\-\-DP\[0\], @BP\[OFFS\+\+\]
+ 1c6:	2e af [ 	]*MOVE  @\-\-DP\[0\], @BP\[OFFS\-\-\]
+ 1c8:	3e af [ 	]*MOVE  @\-\-DP\[0\], OFFS
+ 1ca:	4e af [ 	]*MOVE  @\-\-DP\[0\], DPC
+ 1cc:	5e af [ 	]*MOVE  @\-\-DP\[0\], GR
+ 1ce:	6e af [ 	]*MOVE  @\-\-DP\[0\], GRL
+ 1d0:	7e af [ 	]*MOVE  @\-\-DP\[0\], BP
+ 1d2:	8e af [ 	]*MOVE  @\-\-DP\[0\], GRS
+ 1d4:	9e af [ 	]*MOVE  @\-\-DP\[0\], GRH
+ 1d6:	ae af [ 	]*MOVE  @\-\-DP\[0\], GRXL
+ 1d8:	be af [ 	]*MOVE  @\-\-DP\[0\], FP
+ 1da:	01 3f [ 	]*MOVE  DP\[0\], #01h
+ 1dc:	08 bf [ 	]*MOVE  DP\[0\], AP
+ 1de:	18 bf [ 	]*MOVE  DP\[0\], APC
+ 1e0:	48 bf [ 	]*MOVE  DP\[0\], PSF
+ 1e2:	58 bf [ 	]*MOVE  DP\[0\], IC
+ 1e4:	68 bf [ 	]*MOVE  DP\[0\], IMR
+ 1e6:	88 bf [ 	]*MOVE  DP\[0\], SC
+ 1e8:	b8 bf [ 	]*MOVE  DP\[0\], IIR
+ 1ea:	e8 bf [ 	]*MOVE  DP\[0\], CKCN
+ 1ec:	f8 bf [ 	]*MOVE  DP\[0\], WDCN
+ 1ee:	09 bf [ 	]*MOVE  DP\[0\], A\[0\]
+ 1f0:	f9 bf [ 	]*MOVE  DP\[0\], A\[15\]
+ 1f2:	0a bf [ 	]*MOVE  DP\[0\], ACC
+ 1f4:	1a bf [ 	]*MOVE  DP\[0\], A\[AP\]
+ 1f6:	0c bf [ 	]*MOVE  DP\[0\], IP
+ 1f8:	0d bf [ 	]*MOVE  DP\[0\], @SP\-\-
+ 1fa:	1d bf [ 	]*MOVE  DP\[0\], SP
+ 1fc:	2d bf [ 	]*MOVE  DP\[0\], IV
+ 1fe:	6d bf [ 	]*MOVE  DP\[0\], LC\[0\]
+ 200:	7d bf [ 	]*MOVE  DP\[0\], LC\[1\]
+ 202:	1e bf [ 	]*MOVE  DP\[0\], @BP\[OFFS\+\+\]
+ 204:	2e bf [ 	]*MOVE  DP\[0\], @BP\[OFFS\-\-\]
+ 206:	3e bf [ 	]*MOVE  DP\[0\], OFFS
+ 208:	4e bf [ 	]*MOVE  DP\[0\], DPC
+ 20a:	5e bf [ 	]*MOVE  DP\[0\], GR
+ 20c:	6e bf [ 	]*MOVE  DP\[0\], GRL
+ 20e:	7e bf [ 	]*MOVE  DP\[0\], BP
+ 210:	8e bf [ 	]*MOVE  DP\[0\], GRS
+ 212:	9e bf [ 	]*MOVE  DP\[0\], GRH
+ 214:	ae bf [ 	]*MOVE  DP\[0\], GRXL
+ 216:	be bf [ 	]*MOVE  DP\[0\], FP
+ 218:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 21a:	01 08 [ 	]*MOVE  AP, #01h
+ 21c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 21e:	08 88 [ 	]*MOVE  AP, AP
+ 220:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 222:	18 88 [ 	]*MOVE  AP, APC
+ 224:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 226:	48 88 [ 	]*MOVE  AP, PSF
+ 228:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 22a:	58 88 [ 	]*MOVE  AP, IC
+ 22c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 22e:	68 88 [ 	]*MOVE  AP, IMR
+ 230:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 232:	b8 88 [ 	]*MOVE  AP, IIR
+ 234:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 236:	e8 88 [ 	]*MOVE  AP, CKCN
+ 238:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 23a:	f8 88 [ 	]*MOVE  AP, WDCN
+ 23c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 23e:	09 88 [ 	]*MOVE  AP, A\[0\]
+ 240:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 242:	f9 88 [ 	]*MOVE  AP, A\[15\]
+ 244:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 246:	0a 88 [ 	]*MOVE  AP, ACC
+ 248:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 24a:	1a 88 [ 	]*MOVE  AP, A\[AP\]
+ 24c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 24e:	0c 88 [ 	]*MOVE  AP, IP
+ 250:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 252:	0d 88 [ 	]*MOVE  AP, @SP\-\-
+ 254:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 256:	1d 88 [ 	]*MOVE  AP, SP
+ 258:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 25a:	2d 88 [ 	]*MOVE  AP, IV
+ 25c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 25e:	6d 88 [ 	]*MOVE  AP, LC\[0\]
+ 260:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 262:	7d 88 [ 	]*MOVE  AP, LC\[1\]
+ 264:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 266:	1e 88 [ 	]*MOVE  AP, @BP\[OFFS\+\+\]
+ 268:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 26a:	2e 88 [ 	]*MOVE  AP, @BP\[OFFS\-\-\]
+ 26c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 26e:	3e 88 [ 	]*MOVE  AP, OFFS
+ 270:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 272:	4e 88 [ 	]*MOVE  AP, DPC
+ 274:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 276:	5e 88 [ 	]*MOVE  AP, GR
+ 278:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 27a:	6e 88 [ 	]*MOVE  AP, GRL
+ 27c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 27e:	7e 88 [ 	]*MOVE  AP, BP
+ 280:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 282:	8e 88 [ 	]*MOVE  AP, GRS
+ 284:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 286:	9e 88 [ 	]*MOVE  AP, GRH
+ 288:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 28a:	ae 88 [ 	]*MOVE  AP, GRXL
+ 28c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 28e:	be 88 [ 	]*MOVE  AP, FP
+ 290:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 292:	0f 88 [ 	]*MOVE  AP, @DP\[0\]
+ 294:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 296:	4f 88 [ 	]*MOVE  AP, @DP\[1\]
+ 298:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 29a:	1f 88 [ 	]*MOVE  AP, @DP\[0\]\+\+
+ 29c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 29e:	5f 88 [ 	]*MOVE  AP, @DP\[1\]\+\+
+ 2a0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2a2:	2f 88 [ 	]*MOVE  AP, @DP\[0\]\-\-
+ 2a4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2a6:	6f 88 [ 	]*MOVE  AP, @DP\[1\]\-\-
+ 2a8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2aa:	01 68 [ 	]*MOVE  IMR, #01h
+ 2ac:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ae:	08 e8 [ 	]*MOVE  IMR, AP
+ 2b0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2b2:	18 e8 [ 	]*MOVE  IMR, APC
+ 2b4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2b6:	48 e8 [ 	]*MOVE  IMR, PSF
+ 2b8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ba:	58 e8 [ 	]*MOVE  IMR, IC
+ 2bc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2be:	68 e8 [ 	]*MOVE  IMR, IMR
+ 2c0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2c2:	88 e8 [ 	]*MOVE  IMR, SC
+ 2c4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2c6:	b8 e8 [ 	]*MOVE  IMR, IIR
+ 2c8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ca:	f8 e8 [ 	]*MOVE  IMR, WDCN
+ 2cc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ce:	09 e8 [ 	]*MOVE  IMR, A\[0\]
+ 2d0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2d2:	f9 e8 [ 	]*MOVE  IMR, A\[15\]
+ 2d4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2d6:	0a e8 [ 	]*MOVE  IMR, ACC
+ 2d8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2da:	1a e8 [ 	]*MOVE  IMR, A\[AP\]
+ 2dc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2de:	0c e8 [ 	]*MOVE  IMR, IP
+ 2e0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2e2:	0d e8 [ 	]*MOVE  IMR, @SP\-\-
+ 2e4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2e6:	1d e8 [ 	]*MOVE  IMR, SP
+ 2e8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ea:	2d e8 [ 	]*MOVE  IMR, IV
+ 2ec:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ee:	6d e8 [ 	]*MOVE  IMR, LC\[0\]
+ 2f0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2f2:	7d e8 [ 	]*MOVE  IMR, LC\[1\]
+ 2f4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2f6:	1e e8 [ 	]*MOVE  IMR, @BP\[OFFS\+\+\]
+ 2f8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2fa:	2e e8 [ 	]*MOVE  IMR, @BP\[OFFS\-\-\]
+ 2fc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2fe:	3e e8 [ 	]*MOVE  IMR, OFFS
+ 300:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 302:	4e e8 [ 	]*MOVE  IMR, DPC
+ 304:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 306:	5e e8 [ 	]*MOVE  IMR, GR
+ 308:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 30a:	6e e8 [ 	]*MOVE  IMR, GRL
+ 30c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 30e:	7e e8 [ 	]*MOVE  IMR, BP
+ 310:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 312:	8e e8 [ 	]*MOVE  IMR, GRS
+ 314:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 316:	9e e8 [ 	]*MOVE  IMR, GRH
+ 318:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 31a:	ae e8 [ 	]*MOVE  IMR, GRXL
+ 31c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 31e:	be e8 [ 	]*MOVE  IMR, FP
+ 320:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 322:	0f e8 [ 	]*MOVE  IMR, @DP\[0\]
+ 324:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 326:	4f e8 [ 	]*MOVE  IMR, @DP\[1\]
+ 328:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 32a:	1f e8 [ 	]*MOVE  IMR, @DP\[0\]\+\+
+ 32c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 32e:	5f e8 [ 	]*MOVE  IMR, @DP\[1\]\+\+
+ 330:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 332:	2f e8 [ 	]*MOVE  IMR, @DP\[0\]\-\-
+ 334:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 336:	6f e8 [ 	]*MOVE  IMR, @DP\[1\]\-\-
+ 338:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 33a:	01 1e [ 	]*MOVE  @BP\[\+\+OFFS\], #01h
+ 33c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 33e:	08 9e [ 	]*MOVE  @BP\[\+\+OFFS\], AP
+ 340:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 342:	18 9e [ 	]*MOVE  @BP\[\+\+OFFS\], APC
+ 344:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 346:	48 9e [ 	]*MOVE  @BP\[\+\+OFFS\], PSF
+ 348:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 34a:	58 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IC
+ 34c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 34e:	68 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IMR
+ 350:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 352:	88 9e [ 	]*MOVE  @BP\[\+\+OFFS\], SC
+ 354:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 356:	b8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IIR
+ 358:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 35a:	e8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], CKCN
+ 35c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 35e:	f8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], WDCN
+ 360:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 362:	09 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[0\]
+ 364:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 366:	f9 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[15\]
+ 368:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 36a:	0a 9e [ 	]*MOVE  @BP\[\+\+OFFS\], ACC
+ 36c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 36e:	1a 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[AP\]
+ 370:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 372:	0c 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IP
+ 374:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 376:	0d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @SP\-\-
+ 378:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 37a:	1d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], SP
+ 37c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 37e:	2d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IV
+ 380:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 382:	6d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], LC\[0\]
+ 384:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 386:	7d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], LC\[1\]
+ 388:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 38a:	1e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @BP\[OFFS\+\+\]
+ 38c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 38e:	2e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @BP\[OFFS\-\-\]
+ 390:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 392:	3e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], OFFS
+ 394:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 396:	4e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], DPC
+ 398:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 39a:	5e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GR
+ 39c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 39e:	6e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRL
+ 3a0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3a2:	7e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], BP
+ 3a4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3a6:	8e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRS
+ 3a8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3aa:	ae 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRXL
+ 3ac:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3ae:	be 9e [ 	]*MOVE  @BP\[\+\+OFFS\], FP
+ 3b0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3b2:	0f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]
+ 3b4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3b6:	4f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]
+ 3b8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3ba:	1f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]\+\+
+ 3bc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3be:	5f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]\+\+
+ 3c0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3c2:	2f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]\-\-
+ 3c4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3c6:	6f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]\-\-
diff --git a/gas/testsuite/gas/maxq20/data3.s b/gas/testsuite/gas/maxq20/data3.s
new file mode 100644
index 0000000..c3cdbbb
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/data3.s
@@ -0,0 +1,379 @@
+;# data.s	
+;# checks all the data transfer instructions
+foo:
+	MOVE DPC, #01h
+	MOVE DPC, AP
+	MOVE DPC, APC
+	MOVE DPC, PSF
+	MOVE DPC, IC
+	MOVE DPC, IMR
+	MOVE DPC, SC
+	MOVE DPC, IIR
+	MOVE DPC, CKCN
+	MOVE DPC, WDCN
+	MOVE DPC, A[0]		;Just Check two boundary conditions
+	MOVE DPC, A[15]   
+	MOVE DPC, ACC
+	MOVE DPC, A[AP]
+	MOVE DPC, IP
+	MOVE DPC, @SP--
+	MOVE DPC, SP
+	MOVE DPC, IV
+	MOVE DPC, LC[0]
+	MOVE DPC, LC[1]
+	MOVE DPC, @BP[OFFS++]
+	MOVE DPC, @BP[OFFS--]
+	MOVE DPC, OFFS
+	MOVE DPC, GR
+	MOVE DPC, GRL
+	MOVE DPC, BP
+	MOVE DPC, GRS
+	MOVE DPC, GRH
+	MOVE DPC, GRXL
+	MOVE DPC, FP
+	MOVE DPC, @DP[0]	
+	MOVE DPC, @DP[1]	
+	MOVE DPC, @DP[0]++		
+	MOVE DPC, @DP[1]++
+	MOVE DPC, @DP[0]--
+	MOVE DPC, @DP[1]--
+	MOVE GR, #01h
+	MOVE GR, AP
+	MOVE GR, APC
+	MOVE GR, PSF
+	MOVE GR, IC
+	MOVE GR, IMR
+	MOVE GR, SC
+	MOVE GR, IIR
+	MOVE GR, CKCN
+	MOVE GR, WDCN
+	MOVE GR, A[0]		;Just Check two boundary conditions
+	MOVE GR, A[15]   
+	MOVE GR, ACC
+	MOVE GR, A[AP]
+	MOVE GR, IP
+	MOVE GR, @SP--
+	MOVE GR, SP
+	MOVE GR, IV
+	MOVE GR, LC[0]
+	MOVE GR, LC[1]
+	MOVE GR, @BP[OFFS++]
+	MOVE GR, @BP[OFFS--]
+	MOVE GR, OFFS
+	MOVE GR, DPC
+	MOVE GR, GRL
+	MOVE GR, BP
+	MOVE GR, GRS
+	MOVE GR, GRH
+	MOVE GR, GRXL
+	MOVE GR, FP
+	MOVE GR, @DP[0]	
+	MOVE GR, @DP[1]	
+	MOVE GR, @DP[0]++		
+	MOVE GR, @DP[1]++
+	MOVE GR, @DP[0]--
+	MOVE GR, @DP[1]--
+	MOVE GRL, #01h
+	MOVE GRL, AP
+	MOVE GRL, APC
+	MOVE GRL, PSF
+	MOVE GRL, IC
+	MOVE GRL, IMR
+	MOVE GRL, SC
+	MOVE GRL, IIR
+	MOVE GRL, CKCN
+	MOVE GRL, WDCN
+	MOVE GRL, A[0]		;Just Check two boundary conditions
+	MOVE GRL, A[15]   
+	MOVE GRL, ACC
+	MOVE GRL, A[AP]
+	MOVE GRL, IP
+	MOVE GRL, @SP--
+	MOVE GRL, SP
+	MOVE GRL, IV
+	MOVE GRL, LC[0]
+	MOVE GRL, LC[1]
+	MOVE GRL, @BP[OFFS++]
+	MOVE GRL, @BP[OFFS--]
+	MOVE GRL, OFFS
+	MOVE GRL, DPC
+	MOVE GRL, GR
+	MOVE GRL, BP
+	MOVE GRL, GRS
+	MOVE GRL, GRH
+	MOVE GRL, GRXL
+	MOVE GRL, FP
+	MOVE GRL, @DP[0]	
+	MOVE GRL, @DP[1]	
+	MOVE GRL, @DP[0]++		
+	MOVE GRL, @DP[1]++
+	MOVE GRL, @DP[0]--
+	MOVE GRL, @DP[1]--
+	MOVE BP, #01h
+	MOVE BP, AP
+	MOVE BP, APC
+	MOVE BP, PSF
+	MOVE BP, IC
+	MOVE BP, IMR
+	MOVE BP, SC
+	MOVE BP, IIR
+	MOVE BP, CKCN
+	MOVE BP, WDCN
+	MOVE BP, A[0]		;Just Check two boundary conditions
+	MOVE BP, A[15]   
+	MOVE BP, ACC
+	MOVE BP, A[AP]
+	MOVE BP, IP
+	MOVE BP, @SP--
+	MOVE BP, SP
+	MOVE BP, IV
+	MOVE BP, LC[0]
+	MOVE BP, LC[1]
+	MOVE BP, @BP[OFFS++]
+	MOVE BP, @BP[OFFS--]
+	MOVE BP, OFFS
+	MOVE BP, DPC
+	MOVE BP, GR
+	MOVE BP, GRL
+	MOVE BP, GRS
+	MOVE BP, GRH
+	MOVE BP, GRXL
+	MOVE BP, FP
+	MOVE BP, @DP[0]	
+	MOVE BP, @DP[1]	
+	MOVE BP, @DP[0]++		
+	MOVE BP, @DP[1]++
+	MOVE BP, @DP[0]--
+	MOVE BP, @DP[1]--
+	MOVE @DP[0], #01h
+	MOVE @DP[0], AP
+	MOVE @DP[0], APC
+	MOVE @DP[0], PSF
+	MOVE @DP[0], IC
+	MOVE @DP[0], IMR
+	MOVE @DP[0], SC
+	MOVE @DP[0], IIR
+	MOVE @DP[0], CKCN
+	MOVE @DP[0], WDCN
+	MOVE @DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @DP[0], A[15]   
+	MOVE @DP[0], ACC
+	MOVE @DP[0], A[AP]
+	MOVE @DP[0], IP
+	MOVE @DP[0], @SP--
+	MOVE @DP[0], SP
+	MOVE @DP[0], IV
+	MOVE @DP[0], LC[0]
+	MOVE @DP[0], LC[1]
+	MOVE @DP[0], @BP[OFFS++]
+	MOVE @DP[0], @BP[OFFS--]
+	MOVE @DP[0], OFFS
+	MOVE @DP[0], DPC
+	MOVE @DP[0], GR
+	MOVE @DP[0], GRL
+	MOVE @DP[0], BP
+	MOVE @DP[0], GRS
+	MOVE @DP[0], GRH
+	MOVE @DP[0], GRXL
+	MOVE @DP[0], FP
+	MOVE @++DP[0], #01h
+	MOVE @++DP[0], AP
+	MOVE @++DP[0], APC
+	MOVE @++DP[0], PSF
+	MOVE @++DP[0], IC
+	MOVE @++DP[0], IMR
+	MOVE @++DP[0], SC
+	MOVE @++DP[0], IIR
+	MOVE @++DP[0], CKCN
+	MOVE @++DP[0], WDCN
+	MOVE @++DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @++DP[0], A[15]   
+	MOVE @++DP[0], ACC
+	MOVE @++DP[0], A[AP]
+	MOVE @++DP[0], IP
+	MOVE @++DP[0], @SP--
+	MOVE @++DP[0], SP
+	MOVE @++DP[0], IV
+	MOVE @++DP[0], LC[0]
+	MOVE @++DP[0], LC[1]
+	MOVE @++DP[0], @BP[OFFS++]
+	MOVE @++DP[0], @BP[OFFS--]
+	MOVE @++DP[0], OFFS
+	MOVE @++DP[0], DPC
+	MOVE @++DP[0], GR
+	MOVE @++DP[0], GRL
+	MOVE @++DP[0], BP
+	MOVE @++DP[0], GRS
+	MOVE @++DP[0], GRH
+	MOVE @++DP[0], GRXL
+	MOVE @++DP[0], FP
+	MOVE @--DP[0], #01h
+	MOVE @--DP[0], AP
+	MOVE @--DP[0], APC
+	MOVE @--DP[0], PSF
+	MOVE @--DP[0], IC
+	MOVE @--DP[0], IMR
+	MOVE @--DP[0], SC
+	MOVE @--DP[0], IIR
+	MOVE @--DP[0], CKCN
+	MOVE @--DP[0], WDCN
+	MOVE @--DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @--DP[0], A[15]   
+	MOVE @--DP[0], ACC
+	MOVE @--DP[0], A[AP]
+	MOVE @--DP[0], IP
+	MOVE @--DP[0], @SP--
+	MOVE @--DP[0], SP
+	MOVE @--DP[0], IV
+	MOVE @--DP[0], LC[0]
+	MOVE @--DP[0], LC[1]
+	MOVE @--DP[0], @BP[OFFS++]
+	MOVE @--DP[0], @BP[OFFS--]
+	MOVE @--DP[0], OFFS
+	MOVE @--DP[0], DPC
+	MOVE @--DP[0], GR
+	MOVE @--DP[0], GRL
+	MOVE @--DP[0], BP
+	MOVE @--DP[0], GRS
+	MOVE @--DP[0], GRH
+	MOVE @--DP[0], GRXL
+	MOVE @--DP[0], FP
+	MOVE DP[0], #01h
+	MOVE DP[0], AP
+	MOVE DP[0], APC
+	MOVE DP[0], PSF
+	MOVE DP[0], IC
+	MOVE DP[0], IMR
+	MOVE DP[0], SC
+	MOVE DP[0], IIR
+	MOVE DP[0], CKCN
+	MOVE DP[0], WDCN
+	MOVE DP[0], A[0]		;Just Check two boundary conditions
+	MOVE DP[0], A[15]   
+	MOVE DP[0], ACC
+	MOVE DP[0], A[AP]
+	MOVE DP[0], IP
+	MOVE DP[0], @SP--
+	MOVE DP[0], SP
+	MOVE DP[0], IV
+	MOVE DP[0], LC[0]
+	MOVE DP[0], LC[1]
+	MOVE DP[0], @BP[OFFS++]
+	MOVE DP[0], @BP[OFFS--]
+	MOVE DP[0], OFFS
+	MOVE DP[0], DPC
+	MOVE DP[0], GR
+	MOVE DP[0], GRL
+	MOVE DP[0], BP
+	MOVE DP[0], GRS
+	MOVE DP[0], GRH
+	MOVE DP[0], GRXL
+	MOVE DP[0], FP
+	MOVE SC, #01h
+	MOVE SC, AP
+	MOVE SC, APC
+	MOVE SC, PSF
+	MOVE SC, IC
+	MOVE SC, IMR
+	MOVE SC, IIR
+	MOVE SC, CKCN
+	MOVE SC, WDCN
+	MOVE SC, A[0]		;Just Check two boundary conditions
+	MOVE SC, A[15]   
+	MOVE SC, ACC
+	MOVE SC, A[AP]
+	MOVE SC, IP
+	MOVE SC, @SP--
+	MOVE SC, SP
+	MOVE SC, IV
+	MOVE SC, LC[0]
+	MOVE SC, LC[1]
+	MOVE SC, @BP[OFFS++]
+	MOVE SC, @BP[OFFS--]
+	MOVE SC, OFFS
+	MOVE SC, DPC
+	MOVE SC, GR
+	MOVE SC, GRL
+	MOVE SC, BP
+	MOVE SC, GRS
+	MOVE SC, GRH
+	MOVE SC, GRXL
+	MOVE SC, FP
+	MOVE SC, @DP[0]	
+	MOVE SC, @DP[1]	
+	MOVE SC, @DP[0]++		
+	MOVE SC, @DP[1]++
+	MOVE SC, @DP[0]--
+	MOVE SC, @DP[1]--
+	MOVE CKCN, #01h
+	MOVE CKCN, AP
+	MOVE CKCN, APC
+	MOVE CKCN, PSF
+	MOVE CKCN, IC
+	MOVE CKCN, IMR
+	MOVE CKCN, SC
+	MOVE CKCN, IIR
+	MOVE CKCN, WDCN
+	MOVE CKCN, A[0]		;Just Check two boundary conditions
+	MOVE CKCN, A[15]   
+	MOVE CKCN, ACC
+	MOVE CKCN, A[AP]
+	MOVE CKCN, IP
+	MOVE CKCN, @SP--
+	MOVE CKCN, SP
+	MOVE CKCN, IV
+	MOVE CKCN, LC[0]
+	MOVE CKCN, LC[1]
+	MOVE CKCN, @BP[OFFS++]
+	MOVE CKCN, @BP[OFFS--]
+	MOVE CKCN, OFFS
+	MOVE CKCN, DPC
+	MOVE CKCN, GR
+	MOVE CKCN, GRL
+	MOVE CKCN, BP
+	MOVE CKCN, GRS
+	MOVE CKCN, GRH
+	MOVE CKCN, GRXL
+	MOVE CKCN, FP
+	MOVE CKCN, @DP[0]	
+	MOVE CKCN, @DP[1]	
+	MOVE CKCN, @DP[0]++		
+	MOVE CKCN, @DP[1]++
+	MOVE CKCN, @DP[0]--
+	MOVE CKCN, @DP[1]--
+	MOVE GRH, #01h
+	MOVE GRH, AP
+	MOVE GRH, APC
+	MOVE GRH, PSF
+	MOVE GRH, IC
+	MOVE GRH, IMR
+	MOVE GRH, SC
+	MOVE GRH, IIR
+	MOVE GRH, CKCN
+	MOVE GRH, WDCN
+	MOVE GRH, A[0]		;Just Check two boundary conditions
+	MOVE GRH, A[15]   
+	MOVE GRH, ACC
+	MOVE GRH, A[AP]
+	MOVE GRH, IP
+	MOVE GRH, @SP--
+	MOVE GRH, SP
+	MOVE GRH, IV
+	MOVE GRH, LC[0]
+	MOVE GRH, LC[1]
+	MOVE GRH, @BP[OFFS++]
+	MOVE GRH, @BP[OFFS--]
+	MOVE GRH, OFFS
+	MOVE GRH, DPC
+	MOVE GRH, GR
+	MOVE GRH, GRL
+	MOVE GRH, BP
+	MOVE GRH, GRS
+	MOVE GRH, GRXL
+	MOVE GRH, FP
+	MOVE GRH, @DP[0]	
+	MOVE GRH, @DP[1]	
+	MOVE GRH, @DP[0]++		
+	MOVE GRH, @DP[1]++
+	MOVE GRH, @DP[0]--
+	MOVE GRH, @DP[1]--
diff --git a/gas/testsuite/gas/maxq20/jump.d b/gas/testsuite/gas/maxq20/jump.d
new file mode 100644
index 0000000..0fb9d47
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/jump.d
@@ -0,0 +1,116 @@
+#objdump: -dw
+#name: Jump operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <LableStart>:
+   0:	00 0c [ 	]*JUMP  #00h
+   2:	ff 2c [ 	]*JUMP C , #ffh
+   4:	09 ac [ 	]*JUMP C , A\[0\]
+   6:	19 ac [ 	]*JUMP C , A\[1\]
+   8:	fc 6c [ 	]*JUMP NC , #fch
+   a:	09 ec [ 	]*JUMP NC , A\[0\]
+   c:	19 ec [ 	]*JUMP NC , A\[1\]
+   e:	f9 4c [ 	]*JUMP S , #f9h
+  10:	09 cc [ 	]*JUMP S , A\[0\]
+  12:	19 cc [ 	]*JUMP S , A\[1\]
+  14:	f6 1c [ 	]*JUMP Z , #f6h
+  16:	09 9c [ 	]*JUMP Z , A\[0\]
+  18:	19 9c [ 	]*JUMP Z , A\[1\]
+  1a:	f3 5c [ 	]*JUMP NZ , #f3h
+  1c:	09 dc [ 	]*JUMP NZ , A\[0\]
+  1e:	19 dc [ 	]*JUMP NZ , A\[1\]
+  20:	f0 3c [ 	]*JUMP E , #f0h
+  22:	ef 7c [ 	]*JUMP NE , #efh
+  24:	01 7c [ 	]*JUMP NE , #01h
+
+0+026 <Lable1>:
+  26:	00 0c [ 	]*JUMP  #00h
+  28:	ff 2c [ 	]*JUMP C , #ffh
+  2a:	09 ac [ 	]*JUMP C , A\[0\]
+  2c:	19 ac [ 	]*JUMP C , A\[1\]
+  2e:	fc 6c [ 	]*JUMP NC , #fch
+  30:	09 ec [ 	]*JUMP NC , A\[0\]
+  32:	19 ec [ 	]*JUMP NC , A\[1\]
+  34:	f9 4c [ 	]*JUMP S , #f9h
+  36:	09 cc [ 	]*JUMP S , A\[0\]
+  38:	19 cc [ 	]*JUMP S , A\[1\]
+  3a:	f6 1c [ 	]*JUMP Z , #f6h
+  3c:	09 9c [ 	]*JUMP Z , A\[0\]
+  3e:	19 9c [ 	]*JUMP Z , A\[1\]
+  40:	f3 5c [ 	]*JUMP NZ , #f3h
+  42:	09 dc [ 	]*JUMP NZ , A\[0\]
+  44:	19 dc [ 	]*JUMP NZ , A\[1\]
+  46:	f0 3c [ 	]*JUMP E , #f0h
+  48:	ef 7c [ 	]*JUMP NE , #efh
+  4a:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  4c:	c6 0c [ 	]*JUMP  #c6h
+  4e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  50:	c6 2c [ 	]*JUMP C , #c6h
+  52:	09 ac [ 	]*JUMP C , A\[0\]
+  54:	19 ac [ 	]*JUMP C , A\[1\]
+  56:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  58:	c6 6c [ 	]*JUMP NC , #c6h
+  5a:	09 ec [ 	]*JUMP NC , A\[0\]
+  5c:	19 ec [ 	]*JUMP NC , A\[1\]
+  5e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  60:	c6 1c [ 	]*JUMP Z , #c6h
+  62:	09 9c [ 	]*JUMP Z , A\[0\]
+  64:	19 9c [ 	]*JUMP Z , A\[1\]
+  66:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  68:	c6 5c [ 	]*JUMP NZ , #c6h
+  6a:	09 dc [ 	]*JUMP NZ , A\[0\]
+  6c:	19 dc [ 	]*JUMP NZ , A\[1\]
+  6e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  70:	c6 4c [ 	]*JUMP S , #c6h
+  72:	09 cc [ 	]*JUMP S , A\[0\]
+  74:	19 cc [ 	]*JUMP S , A\[1\]
+  76:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  78:	c6 3c [ 	]*JUMP E , #c6h
+  7a:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  7c:	c6 7c [ 	]*JUMP NE , #c6h
+  7e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  80:	c6 0c [ 	]*JUMP  #c6h
+  82:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  84:	c6 2c [ 	]*JUMP C , #c6h
+  86:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  88:	09 ac [ 	]*JUMP C , A\[0\]
+  8a:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  8c:	19 ac [ 	]*JUMP C , A\[1\]
+  8e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  90:	c6 7c [ 	]*JUMP NE , #c6h
+  92:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  94:	c6 1c [ 	]*JUMP Z , #c6h
+  96:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  98:	09 9c [ 	]*JUMP Z , A\[0\]
+  9a:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  9c:	19 9c [ 	]*JUMP Z , A\[1\]
+  9e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  a0:	c6 5c [ 	]*JUMP NZ , #c6h
+  a2:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  a4:	09 dc [ 	]*JUMP NZ , A\[0\]
+  a6:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  a8:	19 dc [ 	]*JUMP NZ , A\[1\]
+  aa:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  ac:	c6 4c [ 	]*JUMP S , #c6h
+  ae:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  b0:	09 cc [ 	]*JUMP S , A\[0\]
+  b2:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  b4:	19 cc [ 	]*JUMP S , A\[1\]
+  b6:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  b8:	c6 6c [ 	]*JUMP NC , #c6h
+  ba:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  bc:	09 ec [ 	]*JUMP NC , A\[0\]
+  be:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  c0:	19 ec [ 	]*JUMP NC , A\[1\]
+  c2:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  c4:	c6 3c [ 	]*JUMP E , #c6h
+	...
+
+0+4c6 <LongJump>:
+ 4c6:	3a da [ 	]*NOP 
+ 4c8:	3a da [ 	]*NOP 
+ 4ca:	3a da [ 	]*NOP 
+ 4cc:	3a da [ 	]*NOP 
+ 4ce:	3a da [ 	]*NOP 
diff --git a/gas/testsuite/gas/maxq20/jump.s b/gas/testsuite/gas/maxq20/jump.s
new file mode 100644
index 0000000..7948cb0
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/jump.s
@@ -0,0 +1,87 @@
+;# jump.s 
+;# Program flow instructions using JUMP
+.text
+LableStart:	
+		JUMP LableStart
+		JUMP C, LableStart
+		JUMP C, A[0]
+		JUMP C, A[1]
+		JUMP NC, LableStart
+		JUMP NC, A[0]
+		JUMP NC, A[1]
+		JUMP S, LableStart
+		JUMP S, A[0]
+		JUMP S, A[1]	
+		JUMP Z, LableStart
+		JUMP Z, A[0]
+		JUMP Z, A[1]	
+		JUMP NZ, LableStart
+		JUMP NZ, A[0]
+		JUMP NZ, A[1]
+		JUMP E, LableStart
+		JUMP NE, LableStart
+		JUMP NE, Lable1
+
+Lable1:			
+		SJUMP Lable1		;Checking the SJUMP opcode
+		SJUMP C, Lable1
+		SJUMP C, A[0]
+		SJUMP C, A[1]
+		SJUMP NC, Lable1
+		SJUMP NC, A[0]
+		SJUMP NC, A[1]
+		SJUMP S, Lable1
+		SJUMP S, A[0]
+		SJUMP S, A[1]	
+		SJUMP Z, Lable1
+		SJUMP Z, A[0]
+		SJUMP Z, A[1]	
+		SJUMP NZ, Lable1
+		SJUMP NZ, A[0]
+		SJUMP NZ, A[1]	
+		SJUMP E, Lable1
+		SJUMP NE, Lable1
+		JUMP LongJump
+		JUMP C, LongJump
+		JUMP C, A[0]
+		JUMP C, A[1]
+		JUMP NC, LongJump
+		JUMP NC, A[0]
+		JUMP NC, A[1]
+		JUMP Z, LongJump
+		JUMP Z, A[0]
+		JUMP Z, A[1]
+		JUMP NZ, LongJump
+		JUMP NZ, A[0]
+		JUMP NZ, A[1]
+		JUMP S, LongJump
+		JUMP S, A[0]
+		JUMP S, A[1]	
+		JUMP E, LongJump
+		JUMP NE, LongJump
+		LJUMP LongJump		;test LJUMP also
+		LJUMP C, LongJump
+		LJUMP C, A[0]
+		LJUMP C, A[1]
+		LJUMP NE, LongJump
+		LJUMP Z, LongJump
+		LJUMP Z, A[0]
+		LJUMP Z, A[1]
+		LJUMP NZ, LongJump
+		LJUMP NZ, A[0]
+		LJUMP NZ, A[1]
+		LJUMP S, LongJump
+		LJUMP S, A[0]
+		LJUMP S, A[1]
+		LJUMP NC, LongJump
+		LJUMP NC, A[0]
+		LJUMP NC, A[1]	 
+		LJUMP E, LongJump
+		.fill 0x200, 2, 0 	
+LongJump: 
+		NOP
+		NOP
+		NOP
+		NOP
+		NOP
+	
diff --git a/gas/testsuite/gas/maxq20/jzimm.d b/gas/testsuite/gas/maxq20/jzimm.d
new file mode 100644
index 0000000..667fa24
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/jzimm.d
@@ -0,0 +1,27 @@
+#objdump: -dw
+#name: Jump immediate operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+0000 <_main>:
+   0:	03 2c [ 	]*JUMP C , #03h
+   2:	03 4c [ 	]*JUMP S , #03h
+   4:	0f 0b [ 	]*MOVE  PFX\[0\], #0fh
+   6:	ff 1c [ 	]*JUMP Z , #ffh
+   8:	03 5c [ 	]*JUMP NZ , #03h
+   a:	03 2c [ 	]*JUMP C , #03h
+   c:	03 4c [ 	]*JUMP S , #03h
+   e:	0f 0b [ 	]*MOVE  PFX\[0\], #0fh
+  10:	ff 1c [ 	]*JUMP Z , #ffh
+  12:	03 5c [ 	]*JUMP NZ , #03h
+  14:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  16:	03 2c [ 	]*JUMP C , #03h
+  18:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  1a:	03 4c [ 	]*JUMP S , #03h
+  1c:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  1e:	0f 0b [ 	]*MOVE  PFX\[0\], #0fh
+  20:	ff 1c [ 	]*JUMP Z , #ffh
+  22:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  24:	03 5c [ 	]*JUMP NZ , #03h
+	...
diff --git a/gas/testsuite/gas/maxq20/jzimm.s b/gas/testsuite/gas/maxq20/jzimm.s
new file mode 100644
index 0000000..bf05cf4
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/jzimm.s
@@ -0,0 +1,17 @@
+.text
+
+_main:   
+ 	        JUMP C, #03h
+                JUMP S, #03h
+                JUMP Z, #fffh
+                JUMP NZ, #03h
+
+		SJUMP C, #03h
+                SJUMP S, #03h
+                SJUMP Z, #fffh
+                SJUMP NZ, #03h
+
+		LJUMP C, #03h
+                LJUMP S, #03h
+                LJUMP Z, #fffh
+                LJUMP NZ, #03h
diff --git a/gas/testsuite/gas/maxq20/logical.d b/gas/testsuite/gas/maxq20/logical.d
new file mode 100644
index 0000000..2f8cfd0
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/logical.d
@@ -0,0 +1,25 @@
+#objdump:-dw
+#name: logical operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	00 08 [ 	]*MOVE  AP, #00h
+   2:	ff 1a [ 	]*AND  #ffh
+   4:	f0 2a [ 	]*OR  #f0h
+   6:	fe 3a [ 	]*XOR  #feh
+   8:	1a 8a [ 	]*CPL 
+   a:	9a 8a [ 	]*NEG 
+   c:	2a 8a [ 	]*SLA 
+   e:	3a 8a [ 	]*SLA2 
+  10:	6a 8a [ 	]*SLA4 
+  12:	4a 8a [ 	]*RL 
+  14:	5a 8a [ 	]*RLC 
+  16:	fa 8a [ 	]*SRA 
+  18:	ea 8a [ 	]*SRA2 
+  1a:	ba 8a [ 	]*SRA4 
+  1c:	aa 8a [ 	]*SR 
+  1e:	ca 8a [ 	]*RR 
+  20:	da 8a [ 	]*RRC 
+	...
diff --git a/gas/testsuite/gas/maxq20/logical.s b/gas/testsuite/gas/maxq20/logical.s
new file mode 100644
index 0000000..ac02316
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/logical.s
@@ -0,0 +1,22 @@
+;# logical.s
+;# Verifies all the logical operation in the file
+
+.text	
+foo:
+	MOVE AP, #00h	;Set AC[0] as the active accumulator
+	AND #FFh	;AND AC[0] with 0xFF
+	OR #F0h
+	XOR #FEh
+	CPL
+	NEG
+	SLA
+	SLA2	
+	SLA4
+	RL	
+	RLC
+	SRA
+	SRA2
+	SRA4
+	SR
+	RR
+	RRC
diff --git a/gas/testsuite/gas/maxq20/math.d b/gas/testsuite/gas/maxq20/math.d
new file mode 100644
index 0000000..34a70dd
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/math.d
@@ -0,0 +1,41 @@
+#objdump:-dw
+#name: Math operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	01 4a [ 	]*ADD  #01h
+   2:	02 4a [ 	]*ADD  #02h
+   4:	03 4a [ 	]*ADD  #03h
+   6:	04 4a [ 	]*ADD  #04h
+   8:	05 4a [ 	]*ADD  #05h
+   a:	09 ca [ 	]*ADD  A\[0\]
+   c:	19 ca [ 	]*ADD  A\[1\]
+   e:	29 ca [ 	]*ADD  A\[2\]
+  10:	39 ca [ 	]*ADD  A\[3\]
+  12:	49 ca [ 	]*ADD  A\[4\]
+  14:	31 6a [ 	]*ADDC  #31h
+  16:	32 6a [ 	]*ADDC  #32h
+  18:	33 6a [ 	]*ADDC  #33h
+  1a:	09 ea [ 	]*ADDC  A\[0\]
+  1c:	19 ea [ 	]*ADDC  A\[1\]
+  1e:	29 ea [ 	]*ADDC  A\[2\]
+  20:	39 ea [ 	]*ADDC  A\[3\]
+  22:	01 5a [ 	]*SUB  #01h
+  24:	02 5a [ 	]*SUB  #02h
+  26:	03 5a [ 	]*SUB  #03h
+  28:	04 5a [ 	]*SUB  #04h
+  2a:	05 5a [ 	]*SUB  #05h
+  2c:	09 da [ 	]*SUB  A\[0\]
+  2e:	19 da [ 	]*SUB  A\[1\]
+  30:	29 da [ 	]*SUB  A\[2\]
+  32:	39 da [ 	]*SUB  A\[3\]
+  34:	49 da [ 	]*SUB  A\[4\]
+  36:	31 7a [ 	]*SUBB  #31h
+  38:	32 7a [ 	]*SUBB  #32h
+  3a:	33 7a [ 	]*SUBB  #33h
+  3c:	09 fa [ 	]*SUBB  A\[0\]
+  3e:	19 fa [ 	]*SUBB  A\[1\]
+  40:	29 fa [ 	]*SUBB  A\[2\]
+  42:	39 fa [ 	]*SUBB  A\[3\]
diff --git a/gas/testsuite/gas/maxq20/math.s b/gas/testsuite/gas/maxq20/math.s
new file mode 100644
index 0000000..b3c1bd7
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/math.s
@@ -0,0 +1,39 @@
+;# math.s
+;# Implements all the math intuctions
+
+.text
+foo:	
+	ADD #01h	; add 01h to accumulator
+	ADD #02h
+	ADD #03h
+	ADD #04h
+	ADD #05h
+	ADD A[0]	; Add Active accumulator+A[0]
+	ADD A[1]
+	ADD A[2]
+	ADD A[3]
+	ADD A[4]
+	ADDC #31h
+	ADDC #32h
+	ADDC #33h
+	ADDC A[0]
+	ADDC A[1]
+	ADDC A[2]
+	ADDC A[3]
+	SUB #01h	; Substract 01h from accumulator
+	SUB #02h
+	SUB #03h
+	SUB #04h
+	SUB #05h
+	SUB A[0]	; Active accumulator-A[0]
+	SUB A[1]
+	SUB A[2]
+	SUB A[3]
+	SUB A[4]	
+	SUBB #31h
+	SUBB #32h
+	SUBB #33h
+	SUBB A[0]
+	SUBB A[1]
+	SUBB A[2]
+	SUBB A[3]
diff --git a/gas/testsuite/gas/maxq20/maxq20.exp b/gas/testsuite/gas/maxq20/maxq20.exp
new file mode 100644
index 0000000..5d7f6cb
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/maxq20.exp
@@ -0,0 +1,55 @@
+#
+# MAXQ20 tests
+#
+proc run_list_test { name opts } {
+    global srcdir subdir
+    set testname "maxq20 $name"
+    set file $srcdir/$subdir/$name
+    gas_run ${name}.s $opts ">&dump.out"
+    if { [regexp_diff "dump.out" "${file}.l"] } then {
+	fail $testname
+	verbose "output is [file_contents "dump.out"]" 2
+	return
+    }
+    pass $testname
+}
+
+proc gas_64_check { } {
+    global NM
+    global NMFLAGS
+    global srcdir
+
+    catch "exec $srcdir/lib/run $NM $NMFLAGS --help" nm_help
+    return [regexp "targets:.*maxq" $nm_help];
+}
+
+proc gas_32_check { } {
+    global NM
+    global NMFLAGS
+    global srcdir
+
+    catch "exec $srcdir/lib/run $NM $NMFLAGS --help" nm_help
+    return [regexp "targets:.*maxq" $nm_help];
+}
+
+
+if [expr ([istarget "maxq-*-*"] ||  [istarget "maxq-coff-*-*"]) && [gas_32_check]]  then {
+
+    global ASFLAGS
+    set old_ASFLAGS "$ASFLAGS"
+    set ASFLAGS "$ASFLAGS"
+
+    run_dump_test "range"
+    run_dump_test "data3"
+    run_dump_test "data2"
+    run_dump_test "call"
+    run_dump_test "jump"
+    run_dump_test "logical"
+    run_dump_test "math"
+    run_dump_test "bits"
+    run_dump_test "data1"
+    run_dump_test "jzimm"
+
+    set ASFLAGS "$old_ASFLAGS"
+}
+
diff --git a/gas/testsuite/gas/maxq20/pfx2.s b/gas/testsuite/gas/maxq20/pfx2.s
new file mode 100644
index 0000000..b2fcec2
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/pfx2.s
@@ -0,0 +1,5 @@
+.text
+	MOVE A[10], #1234h
+	MOVE A[9], #1212h
+	MOVE A[8], #1111h
+	MOVE A[7], #2222h
diff --git a/gas/testsuite/gas/maxq20/pmtest.d b/gas/testsuite/gas/maxq20/pmtest.d
new file mode 100644
index 0000000..b93e69c
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/pmtest.d
@@ -0,0 +1,25 @@
+#objdump: -dw
+#name: MaC supoprt check
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <.text>:
+   0:	05 13 [ 	]*MOVE  13h, #05h
+   2:	e9 53 [ 	]*MOVE  53h, #e9h
+   4:	09 e3 [ 	]*MOVE  63h, A\[0\]
+   6:	12 14 [ 	]*MOVE  14h, #12h
+   8:	12 44 [ 	]*MOVE  44h, #12h
+   a:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+   c:	09 84 [ 	]*MOVE  04h, A\[0\]
+   e:	7b 15 [ 	]*MOVE  15h, #7bh
+  10:	13 25 [ 	]*MOVE  25h, #13h
+  12:	d9 e5 [ 	]*MOVE  65h, A\[13\]
+  14:	13 15 [ 	]*MOVE  15h, #13h
+  16:	13 a5 [ 	]*MOVE  25h, 13h
+  18:	12 13 [ 	]*MOVE  13h, #12h
+  1a:	12 2b [ 	]*MOVE  PFX\[2\], #12h
+  1c:	34 59 [ 	]*MOVE  A\[5\], #34h
+  1e:	04 2b [ 	]*MOVE  PFX\[2\], #04h
+  20:	d2 79 [ 	]*MOVE  A\[7\], #d2h
+	...
diff --git a/gas/testsuite/gas/maxq20/pmtest.s b/gas/testsuite/gas/maxq20/pmtest.s
new file mode 100644
index 0000000..70b898d
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/pmtest.s
@@ -0,0 +1,25 @@
+;# Peripheral(plugable) module test file 
+.text
+
+; Timer1 test module configured at mod. no. 3
+move T1CN, #05h
+move T1MD, #233
+move T1CL,A[0]
+; Timer2 module test plugged at mod. no. 4
+move T2CFG, #12h
+move T2V, #12h
+move T2C, A[0]
+
+; MAC module test plugged at 5
+move MCNT, #123
+move MA, #13h
+move MC0, A[13]
+
+;test the pm support 
+move 15h,#13h
+move 25h, 13h
+move 13h, #12h
+
+move A[13], #1234h	; PFX 2 test
+move A[15], #1234
+
diff --git a/gas/testsuite/gas/maxq20/pxf0.s b/gas/testsuite/gas/maxq20/pxf0.s
new file mode 100644
index 0000000..7672186
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/pxf0.s
@@ -0,0 +1,4 @@
+.text
+	MOVE A[0],#1234h
+	MOVE A[1],4321h
+
diff --git a/gas/testsuite/gas/maxq20/range.d b/gas/testsuite/gas/maxq20/range.d
new file mode 100644
index 0000000..3453b1a
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/range.d
@@ -0,0 +1,49 @@
+#objdump:-dw
+#name: limit checks for maxq immediate data
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <.text>:
+   0:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+   2:	ff 09 [ 	]*MOVE  A\[0\], #ffh
+   4:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+   6:	ff 08 [ 	]*MOVE  AP, #ffh
+   8:	01 09 [ 	]*MOVE  A\[0\], #01h
+   a:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+   c:	83 08 [ 	]*MOVE  AP, #83h
+   e:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  10:	82 08 [ 	]*MOVE  AP, #82h
+  12:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  14:	81 08 [ 	]*MOVE  AP, #81h
+  16:	7d 09 [ 	]*MOVE  A\[0\], #7dh
+  18:	7e 09 [ 	]*MOVE  A\[0\], #7eh
+  1a:	80 09 [ 	]*MOVE  A\[0\], #80h
+  1c:	fe 09 [ 	]*MOVE  A\[0\], #feh
+  1e:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  20:	ff 0d [ 	]*MOVE  @\+\+SP, #ffh
+  22:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  24:	82 0d [ 	]*MOVE  @\+\+SP, #82h
+  26:	fe 0d [ 	]*MOVE  @\+\+SP, #feh
+  28:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  2a:	81 0d [ 	]*MOVE  @\+\+SP, #81h
+  2c:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  2e:	80 0d [ 	]*MOVE  @\+\+SP, #80h
+  30:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  32:	ff 4a [ 	]*ADD  #ffh
+  34:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  36:	81 4a [ 	]*ADD  #81h
+  38:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  3a:	7f 4a [ 	]*ADD  #7fh
+  3c:	7f 4a [ 	]*ADD  #7fh
+  3e:	80 4a [ 	]*ADD  #80h
+  40:	81 4a [ 	]*ADD  #81h
+  42:	fe 4a [ 	]*ADD  #feh
+  44:	ff 4a [ 	]*ADD  #ffh
+  46:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  48:	02 4a [ 	]*ADD  #02h
+  4a:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  4c:	81 4a [ 	]*ADD  #81h
+  4e:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  50:	7f 4a [ 	]*ADD  #7fh
+	...
diff --git a/gas/testsuite/gas/maxq20/range.s b/gas/testsuite/gas/maxq20/range.s
new file mode 100644
index 0000000..f3cdc95
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/range.s
@@ -0,0 +1,30 @@
+;# checks the 8 bit ranges
+;# all negative values should contain a Prefix for MAXQ20
+;# immediate values with one operand for MAXQ10 skips PFX
+.text 
+	move A[0], #-1  
+	move Ap, #-1
+	move a[0], #1
+	move AP, #-125	; AP is an 8 bit register 
+	move AP, #-126
+	move AP, #-127
+	move A[0], #125		; A[0] is an 16 bit register - no pfx req. here
+	move A[0], #126
+	move A[0], #128
+	move A[0], #254	        ; ---------------
+	move @++SP, #-1		; check PFX generation for mem operands
+	move @++sp, #-126	; -
+	move @++sp, #254		; - no pFX here
+	move @++sp, #-127	; -
+	move @++sp, #-128	;--------------------------
+	Add #-1			;Check PFX gen. for single operand instructions
+	Add #-127
+	Add #-129
+	Add #127
+	Add #128
+	add #129
+	add #254
+	add #ffh
+	add #-254
+	add #-127
+	add #-129		; --------------------