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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-08-08 04:06:32 +0000 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-09-05 03:05:11 +0000 |
| commit | 9294a13008b0c048c83a880bce9469bccec14d36 (patch) | |
| tree | 0fe3e08eb840de5f34c19be2b499fe9841933851 /gas | |
| parent | 292273af3700fef7d03d716f9bc67cb07089f110 (diff) | |
| download | gdb-9294a13008b0c048c83a880bce9469bccec14d36.zip gdb-9294a13008b0c048c83a880bce9469bccec14d36.tar.gz gdb-9294a13008b0c048c83a880bce9469bccec14d36.tar.bz2 | |
RISC-V: Prohibit combination of 'E' and 'H'
According to the ratified privileged specification (version 20211203),
it says:
> The hypervisor extension depends on an "I" base integer ISA with 32 x
> registers (RV32I or RV64I), not RV32E, which has only 16 x registers.
Also in the latest draft, it also prohibits RV64E with the 'H' extension.
This commit prohibits the combination of 'E' and 'H' extensions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_check_conflicts): Prohibit 'E' and
'H' combinations.
gas/ChangeLog:
* testsuite/gas/riscv/march-fail-rv32eh.d: New failure test to
make sure that RV32E + 'H' is prohibited.
* testsuite/gas/riscv/march-fail-rv32eh.l: Likewise.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/testsuite/gas/riscv/march-fail-rv32eh.d | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/march-fail-rv32eh.l | 2 |
2 files changed, 5 insertions, 0 deletions
diff --git a/gas/testsuite/gas/riscv/march-fail-rv32eh.d b/gas/testsuite/gas/riscv/march-fail-rv32eh.d new file mode 100644 index 0000000..b57199e --- /dev/null +++ b/gas/testsuite/gas/riscv/march-fail-rv32eh.d @@ -0,0 +1,3 @@ +#as: -march=rv32eh +#source: empty.s +#error_output: march-fail-rv32eh.l diff --git a/gas/testsuite/gas/riscv/march-fail-rv32eh.l b/gas/testsuite/gas/riscv/march-fail-rv32eh.l new file mode 100644 index 0000000..c7cd1cc --- /dev/null +++ b/gas/testsuite/gas/riscv/march-fail-rv32eh.l @@ -0,0 +1,2 @@ +.*Assembler messages: +.*Error: .*rv32e does not support the `h' extension |