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authorJose E. Marchesi <jose.marchesi@oracle.com>2014-10-09 13:16:53 +0100
committerNick Clifton <nickc@redhat.com>2014-10-09 13:16:53 +0100
commit3d68f91c0fb05b426e554004cabd3ded4c91f9c8 (patch)
tree0297b29c1d0d20a3d36868c0357e23a0db4f6efd /gas
parentfcbdedf866d777b3598cf8703737eb0f987c2aca (diff)
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This is a series of patches that add support for the SPARC M7 cpu to
binutils. They were discussed and approved here: https://sourceware.org/ml/binutils/2014-10/msg00038.html
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog41
-rw-r--r--gas/config/tc-sparc.c150
-rw-r--r--gas/doc/c-sparc.texi43
-rw-r--r--gas/testsuite/ChangeLog18
-rw-r--r--gas/testsuite/gas/sparc/hpcvis3.d10
-rw-r--r--gas/testsuite/gas/sparc/hpcvis3.s10
-rw-r--r--gas/testsuite/gas/sparc/mcdper.d15
-rw-r--r--gas/testsuite/gas/sparc/mcdper.s5
-rw-r--r--gas/testsuite/gas/sparc/mwait.d13
-rw-r--r--gas/testsuite/gas/sparc/mwait.s7
-rw-r--r--gas/testsuite/gas/sparc/sparc.exp4
-rw-r--r--gas/testsuite/gas/sparc/sparc5vis4.d38
-rw-r--r--gas/testsuite/gas/sparc/sparc5vis4.s31
-rw-r--r--gas/testsuite/gas/sparc/xcrypto.d105
-rw-r--r--gas/testsuite/gas/sparc/xcrypto.s98
15 files changed, 522 insertions, 66 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index ff149d3..6abdfe3 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,44 @@
+2014-10-09 Jose E. Marchesi &lt;jose.marchesi@oracle.com&gt;
+
+ * config/tc-sparc.c (v9a_asr_table): Entry for %cps removed.
+ (sparc_arch_table): Remove the HWCAP_RANDOM, HWCAP_TRANS and
+ HWCAP_ASI_CACHE_SPARING from the architectures using them.
+ (HWS_V8): New define.
+ (HWS_V9): Likewise.
+ (HWS_VA): Likewise.
+ (HWS_VB): Likewise.
+ (HWS_VC): Likewise.
+ (HWS_VD): Likewise.
+ (HWS_VE): Likewise.
+ (HWS_VV): Likewise.
+ (sparc_arch): Use the HWS_* macros. Fix the `sparc4' architecture
+ to cover the HWCAP_ASI_BLK_INIT and HWCAP_IMA capabilities.
+ (hwcap_seen): Variable widened to 64 bits.
+ (hwcap_allowed): Likewise.
+ (sparc_arch): new field `hwcap2_allowed'.
+ (sparc_arch_table): provide hwcap2_allowed values for existing
+ archs.
+ (sparc_md_end): Add a HWCAPS2 object attribute to the elf object
+ in case any of the HWCAP2_* caps are used.
+ (sparc_ip): Take into account the new hwcaps2 bitmap to build the
+ list of seen/allowed hwcaps.
+ (get_hwcap_name): Argument widened to 64 bits to handle HWCAP2
+ bits.
+ (HWS_VM): New define.
+ (HWS2_VM): Likewise.
+ (sparc_arch): New architectures `sparc5', `v9m' and `v8plusm'.
+ (v9a_asr_table): Add the %mwait (%asr28) ancillary state register
+ to the table.
+ (sparc_ip): Handle the %mcdper ancillary state register as an
+ operand.
+ (sparc_ip): Handle } arguments as fdrd floating point registers
+ (double) that are the same than frs1.
+ * doc/c-sparc.texi (Sparc-Opts): Document the -Av9e, -Av8pluse and
+ -xarch=v9e command line options. Also fix the description of the
+ -Av9v and -Av8plusv command line options.
+ Document the -Av9m, -Av8plusm,-Asparc5, -xarch=v9m and
+ -xarch=sparc5 command line options.
+
2014-09-29 Terry Guo <terry.guo@arm.com>
* as.c (create_obj_attrs_section): Move it and call it from ...
diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index 7497618..1d2f945 100644
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -77,11 +77,11 @@ static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
#ifndef TE_SOLARIS
/* Bitmask of instruction types seen so far, used to populate the
GNU attributes section with hwcap information. */
-static int hwcap_seen;
+static bfd_uint64_t hwcap_seen;
#endif
#endif
-static int hwcap_allowed;
+static bfd_uint64_t hwcap_allowed;
static int architecture_requested;
static int warn_on_bump;
@@ -221,6 +221,25 @@ static void output_insn (const struct sparc_opcode *, struct sparc_it *);
enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus,
v8plusa, v9, v9a, v9b, v9_64};
+/* Hardware capability sets, used to keep sparc_arch_table easy to
+ read. */
+#define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD
+#define HWS_V9 HWS_V8 | HWCAP_POPC
+#define HWS_VA HWS_V9 | HWCAP_VIS
+#define HWS_VB HWS_VA | HWCAP_VIS2
+#define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT
+#define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC
+#define HWS_VE HWS_VD \
+ | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \
+ | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \
+ | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE
+#define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA
+#define HWS_VM HWS_VV
+
+#define HWS2_VM \
+ HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \
+ | HWCAP2_XMPMUL | HWCAP2_XMONT
+
static struct sparc_arch {
char *name;
char *opcode_arch;
@@ -231,41 +250,50 @@ static struct sparc_arch {
/* Allowable arg to -A? */
int user_option_p;
int hwcap_allowed;
+ int hwcap2_allowed;
} sparc_arch_table[] = {
- { "v6", "v6", v6, 0, 1, 0 },
- { "v7", "v7", v7, 0, 1, 0 },
- { "v8", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
- { "v8a", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
- { "sparc", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
- { "sparcvis", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
- { "sparcvis2", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
- { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF },
- { "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA },
- { "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
- { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU },
- { "sparc4", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
- { "leon", "leon", leon, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
- { "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
- { "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
- { "sparc86x", "sparclite", sparc86x, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
- { "v8plus", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
- { "v8plusa", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS },
- { "v8plusb", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2 },
- { "v8plusc", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
- { "v8plusd", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
- { "v8pluse", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
- { "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
- { "v9", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
- { "v9a", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
- { "v9b", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
- { "v9c", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
- { "v9d", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
- { "v9e", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
- { "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
+ { "v6", "v6", v6, 0, 1, 0, 0 },
+ { "v7", "v7", v7, 0, 1, 0, 0 },
+ { "v8", "v8", v8, 32, 1, HWS_V8, 0 },
+ { "v8a", "v8", v8, 32, 1, HWS_V8, 0 },
+ { "sparc", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 },
+ { "sparcvis", "v9a", v9, 0, 1, HWS_VA, 0 },
+ { "sparcvis2", "v9b", v9, 0, 1, HWS_VB, 0 },
+ { "sparcfmaf", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF, 0 },
+ { "sparcima", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_IMA, 0 },
+ { "sparcvis3", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC, 0 },
+ { "sparcvis3r", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU, 0 },
+
+ { "sparc4", "v9b", v9, 0, 1, HWS_VV, 0 },
+ { "sparc5", "v9b", v9, 0, 1, HWS_VM, HWS2_VM },
+
+ { "leon", "leon", leon, 32, 1, HWS_V8, 0 },
+ { "sparclet", "sparclet", sparclet, 32, 1, HWS_V8, 0 },
+ { "sparclite", "sparclite", sparclite, 32, 1, HWS_V8, 0 },
+ { "sparc86x", "sparclite", sparc86x, 32, 1, HWS_V8, 0 },
+
+ { "v8plus", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 },
+ { "v8plusa", "v9a", v9, 0, 1, HWCAP_V8PLUS|HWS_VA, 0 },
+ { "v8plusb", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VB, 0 },
+ { "v8plusc", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VC, 0 },
+ { "v8plusd", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VD, 0 },
+ { "v8pluse", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VE, 0 },
+ { "v8plusv", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VV, 0 },
+ { "v8plusm", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VM, 0 },
+
+ { "v9", "v9", v9, 0, 1, HWS_V9, 0 },
+ { "v9a", "v9a", v9, 0, 1, HWS_VA, 0 },
+ { "v9b", "v9b", v9, 0, 1, HWS_VB, 0 },
+ { "v9c", "v9b", v9, 0, 1, HWS_VC, 0 },
+ { "v9d", "v9b", v9, 0, 1, HWS_VD, 0 },
+ { "v9e", "v9b", v9, 0, 1, HWS_VE, 0 },
+ { "v9v", "v9b", v9, 0, 1, HWS_VV, 0 },
+ { "v9m", "v9b", v9, 0, 1, HWS_VM, HWS2_VM },
+
/* This exists to allow configure.tgt to pass one
value to specify both the default machine and default word size. */
- { "v9-64", "v9", v9, 64, 0, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
- { NULL, NULL, v8, 0, 0, 0 }
+ { "v9-64", "v9", v9, 64, 0, HWS_V9, 0 },
+ { NULL, NULL, v8, 0, 0, 0, 0 }
};
/* Variant of default_arch */
@@ -516,7 +544,8 @@ md_parse_option (int c, char *arg)
if (!architecture_requested
|| opcode_arch > max_architecture)
max_architecture = opcode_arch;
- hwcap_allowed |= sa->hwcap_allowed;
+ hwcap_allowed
+ |= (((bfd_uint64_t) sa->hwcap2_allowed) << 32) | sa->hwcap_allowed;
architecture_requested = 1;
}
break;
@@ -810,9 +839,9 @@ struct priv_reg_entry v9a_asr_table[] =
{"pause", 27},
{"pic", 17},
{"pcr", 16},
+ {"mwait", 28},
{"gsr", 19},
{"dcr", 18},
- {"cps", 28},
{"cfr", 26},
{"clear_softint", 21},
{"", -1}, /* End marker. */
@@ -942,6 +971,7 @@ void
sparc_md_end (void)
{
unsigned long mach = bfd_mach_sparc;
+ int hwcaps, hwcaps2;
if (sparc_arch_size == 64)
switch (current_architecture)
@@ -965,8 +995,13 @@ sparc_md_end (void)
bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
#if defined(OBJ_ELF) && !defined(TE_SOLARIS)
- if (hwcap_seen)
- bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcap_seen);
+ hwcaps = hwcap_seen & U0xffffffff;
+ hwcaps2 = hwcap_seen >> 32;
+
+ if (hwcaps)
+ bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcaps);
+ if (hwcaps2)
+ bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS2, hwcaps2);
#endif
}
@@ -1422,7 +1457,7 @@ md_assemble (char *str)
}
static const char *
-get_hwcap_name (int mask)
+get_hwcap_name (bfd_uint64_t mask)
{
if (mask & HWCAP_MUL32)
return "mul32";
@@ -1482,6 +1517,25 @@ get_hwcap_name (int mask)
return "cbcond";
if (mask & HWCAP_CRC32C)
return "crc32c";
+
+ mask = mask >> 32;
+ if (mask & HWCAP2_FJATHPLUS)
+ return "fjathplus";
+ if (mask & HWCAP2_VIS3B)
+ return "vis3b";
+ if (mask & HWCAP2_ADP)
+ return "adp";
+ if (mask & HWCAP2_SPARC5)
+ return "sparc5";
+ if (mask & HWCAP2_MWAIT)
+ return "mwait";
+ if (mask & HWCAP2_XMPMUL)
+ return "xmpmul";
+ if (mask & HWCAP2_XMONT)
+ return "xmont";
+ if (mask & HWCAP2_NSEC)
+ return "nsec";
+
return "UNKNOWN";
}
@@ -2306,6 +2360,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
case 'g':
case 'H':
case 'J':
+ case '}':
{
char format;
@@ -2368,6 +2423,13 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
break;
} /* if not an 'f' register. */
+ if (*args == '}' && mask != RS2 (opcode))
+ {
+ error_message
+ = _(": Instruction requires frs2 and frsd must be the same register");
+ goto error;
+ }
+
switch (*args)
{
case 'v':
@@ -2390,6 +2452,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
case 'g':
case 'H':
case 'J':
+ case '}':
opcode |= RD (mask);
continue;
} /* Pack it in. */
@@ -2843,6 +2906,12 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
s += 5;
continue;
+ case '{':
+ if (strncmp (s, "%mcdper",7) != 0)
+ break;
+ s += 7;
+ continue;
+
case 'E':
if (strncmp (s, "%ccr", 4) != 0)
break;
@@ -2933,7 +3002,8 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
{
/* We have a match. Now see if the architecture is OK. */
int needed_arch_mask = insn->architecture;
- int hwcaps = insn->hwcaps;
+ bfd_uint64_t hwcaps
+ = (((bfd_uint64_t) insn->hwcaps2) << 32) | insn->hwcaps;
#if defined(OBJ_ELF) && !defined(TE_SOLARIS)
if (hwcaps)
diff --git a/gas/doc/c-sparc.texi b/gas/doc/c-sparc.texi
index 8915528..6036766 100644
--- a/gas/doc/c-sparc.texi
+++ b/gas/doc/c-sparc.texi
@@ -60,7 +60,9 @@ is explicitly requested. SPARC v9 is always incompatible with sparclite.
@kindex -Av9b
@kindex -Av9c
@kindex -Av9d
+@kindex -Av9e
@kindex -Av9v
+@kindex -Av9m
@kindex -Asparc
@kindex -Asparcvis
@kindex -Asparcvis2
@@ -70,7 +72,7 @@ is explicitly requested. SPARC v9 is always incompatible with sparclite.
@kindex -Asparcvis3r
@item -Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite
@itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv
-@itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v
+@itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m
@itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima
@itemx -Asparcvis3 | -Asparcvis3r
Use one of the @samp{-A} options to select one of the SPARC
@@ -81,9 +83,10 @@ or feature requiring an incompatible or higher level.
@samp{-Av8plus}, @samp{-Av8plusa}, @samp{-Av8plusb}, @samp{-Av8plusc},
@samp{-Av8plusd}, and @samp{-Av8plusv} select a 32 bit environment.
-@samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d}, and
-@samp{-Av9v} select a 64 bit environment and are not available unless GAS
-is explicitly configured with 64 bit environment support.
+@samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d},
+@samp{-Av9e}, @samp{-Av9v} and @samp{-Av9m} select a 64 bit
+environment and are not available unless GAS is explicitly configured
+with 64 bit environment support.
@samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with
UltraSPARC VIS 1.0 extensions.
@@ -98,10 +101,17 @@ as well as the instructions enabled by @samp{-Av8plusb} and @samp{-Av9b}.
multiply-add, VIS 3.0, and HPC extension instructions, as well as the
instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}.
-@samp{-Av8plusv} and @samp{-Av9v} enable the 'random', transactional
-memory, floating point unfused multiply-add, integer multiply-add, and
-cache sparing store instructions, as well as the instructions enabled
-by @samp{-Av8plusd} and @samp{-Av9d}.
+@samp{-Av8pluse} and @samp{-Av9e} enable the cryptographic
+instructions, as well as the instructions enabled by @samp{-Av8plusd}
+and @samp{-Av9d}.
+
+@samp{-Av8plusv} and @samp{-Av9v} enable floating point unfused
+multiply-add, and integer multiply-add, as well as the instructions
+enabled by @samp{-Av8pluse} and @samp{-Av9e}.
+
+@samp{-Av8plusm} and @samp{-Av9m} enable the VIS 4.0, subtract extended,
+xmpmul, xmontmul and xmontsqr instructions, as well as the instructions
+enabled by @samp{-Av8plusv} and @samp{-Av9v}.
@samp{-Asparc} specifies a v9 environment. It is equivalent to
@samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise.
@@ -121,21 +131,22 @@ multiply-add instructions enabled.
@samp{-Asparcvis3} specifies a v9b environment with the VIS 3.0,
HPC , and floating point fused multiply-add instructions enabled.
-@samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0,
-HPC, transactional memory, random, and floating point unfused multiply-add
-instructions enabled.
+@samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0, HPC,
+and floating point unfused multiply-add instructions enabled.
+
+@samp{-Asparc5} is equivalent to @samp{-Av9m}.
@item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
@itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a
-@itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9v
+@itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v | -xarch=v9m
@itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2
@itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3
-@itemx -xarch=sparcvis3r
+@itemx -xarch=sparcvis3r | -xarch=sparc5
For compatibility with the SunOS v9 assembler. These options are
equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
--Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9v, -Asparc, -Asparcvis,
--Asparcvis2, -Asparcfmaf, -Asparcima, -Asparcvis3, and -Asparcvis3r,
-respectively.
+-Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9e, -Av9v, -Av9m,
+-Asparc, -Asparcvis, -Asparcvis2, -Asparcfmaf, -Asparcima,
+-Asparcvis3, and -Asparcvis3r, respectively.
@item -bump
Warn whenever it is necessary to switch to another level.
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 5d74cea..68aa318 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,21 @@
+2014-10-09 Jose E. Marchesi &lt;jose.marchesi@oracle.com&gt;
+
+ * gas/sparc/hpcvis3.d: Remove tests for the `chkpt', `commit',
+ `random', `wr r,i,%cps' and `rd r,%cps' instructions.
+ * gas/sparc/hpcvis3.s: Likewise.
+ * gas/sparc/xcrypto.d: New file.
+ * gas/sparc/xcrypto.s: Likewise.
+ * gas/sparc/mwait.d: New file.
+ * gas/sparc/mwait.s: Likewise.
+ * gas/sparc/mcdper.s: New file.
+ * gas/sparc/mcdper.d: Likewise.
+ * gas/sparc/sparc5vis4.d: New file.
+ * gas/sparc/sparc5vis4.s: Likewise.
+ * gas/sparc/sparc.exp (sparc_elf_setup): Run the xcrypto test.
+ Run the mwait test.
+ Run the mcdper test.
+` Run the sparc5vis4 test.
+
2014-09-27 Alan Modra <amodra@gmail.com>
* gas/elf/group2.d, * gas/elf/group2.s: New test.
diff --git a/gas/testsuite/gas/sparc/hpcvis3.d b/gas/testsuite/gas/sparc/hpcvis3.d
index 8b920a5..2c09504 100644
--- a/gas/testsuite/gas/sparc/hpcvis3.d
+++ b/gas/testsuite/gas/sparc/hpcvis3.d
@@ -7,11 +7,11 @@
Disassembly of section .text:
0+ <.text>:
- 0: 83 47 00 00 rd %cps, %g1
- 4: b9 80 a0 03 wr %g2, 3, %cps
+ 0: 01 00 00 00 nop
+ 4: 01 00 00 00 nop
8: c7 08 c0 00 ldx \[ %g3 \], %efsr
- c: 30 50 00 01 chkpt 0x10
- 10: bd f0 00 00 commit
+ c: 01 00 00 00 nop
+ 10: 01 00 00 00 nop
14: 87 a0 4a 22 fnadds %f1, %f2, %f3
18: 8d a0 8a 44 fnaddd %f2, %f4, %f6
1c: 8f a0 cb 25 fnmuls %f3, %f5, %f7
@@ -41,7 +41,7 @@ Disassembly of section .text:
7c: 95 f9 11 c6 fnumaddd %f4, %f6, %f8, %f10
80: 8f b1 42 26 addxc %g5, %g6, %g7
84: 97 b2 42 6a addxccc %o1, %o2, %o3
- 88: 8d b0 02 a0 random %f6
+ 88: 01 00 00 00 nop
8c: 9f b3 42 ce umulxhi %o5, %sp, %o7
90: b5 b0 02 f9 lzcnt %i1, %i2
94: 81 b0 03 7b cmask8 %i3
diff --git a/gas/testsuite/gas/sparc/hpcvis3.s b/gas/testsuite/gas/sparc/hpcvis3.s
index e960557..0fe151c 100644
--- a/gas/testsuite/gas/sparc/hpcvis3.s
+++ b/gas/testsuite/gas/sparc/hpcvis3.s
@@ -1,10 +1,10 @@
# Test HPC/VIS3 instructions
.text
- rd %cps, %g1
- wr %g2, 0x3, %cps
+ nop
+ nop
ldx [%g3], %efsr
- chkpt 1f
-1: commit
+ nop
+1: nop
fnadds %f1, %f2, %f3
fnaddd %f2, %f4, %f6
fnmuls %f3, %f5, %f7
@@ -34,7 +34,7 @@
fnumaddd %f4, %f6, %f8, %f10
addxc %g5, %g6, %g7
addxccc %o1, %o2, %o3
- random %f6
+ nop
umulxhi %o5, %o6, %o7
lzcnt %i1, %i2
cmask8 %i3
diff --git a/gas/testsuite/gas/sparc/mcdper.d b/gas/testsuite/gas/sparc/mcdper.d
new file mode 100644
index 0000000..f37f4b3
--- /dev/null
+++ b/gas/testsuite/gas/sparc/mcdper.d
@@ -0,0 +1,15 @@
+#as: -Av9m
+#objdump: -dr
+#name: sparc OSA2015 %mcdper asr
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 83 43 80 00 rd %mcdper, %g1
+ 4: 9d 80 60 03 wr %g1, 3, %mcdper
+ 8: 9d 80 40 02 wr %g1, %g2, %mcdper
+
+
+
diff --git a/gas/testsuite/gas/sparc/mcdper.s b/gas/testsuite/gas/sparc/mcdper.s
new file mode 100644
index 0000000..0891424
--- /dev/null
+++ b/gas/testsuite/gas/sparc/mcdper.s
@@ -0,0 +1,5 @@
+# Test reads/writes to the %mcdper asr register
+ .text
+ rd %mcdper, %g1
+ wr %g1, 0x3, %mcdper
+ wr %g1, %g2, %mcdper
diff --git a/gas/testsuite/gas/sparc/mwait.d b/gas/testsuite/gas/sparc/mwait.d
new file mode 100644
index 0000000..bbae4fd
--- /dev/null
+++ b/gas/testsuite/gas/sparc/mwait.d
@@ -0,0 +1,13 @@
+#as: -Av9m
+#objdump: -dr
+#name: sparc OSA2015 %mwait asr and MWAIT instruction
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 83 47 00 00 rd %mwait, %g1
+ 4: b9 80 a0 03 wr %g2, 3, %mwait
+ 8: b9 80 00 01 mwait %g1
+ c: b9 80 20 03 mwait 3
diff --git a/gas/testsuite/gas/sparc/mwait.s b/gas/testsuite/gas/sparc/mwait.s
new file mode 100644
index 0000000..0379746
--- /dev/null
+++ b/gas/testsuite/gas/sparc/mwait.s
@@ -0,0 +1,7 @@
+# Test reads/writes to the %mwait asr register and the MWAIT
+# instruction
+ .text
+ rd %mwait, %g1
+ wr %g2, 0x3, %mwait
+ mwait %g1
+ mwait 0x3
diff --git a/gas/testsuite/gas/sparc/sparc.exp b/gas/testsuite/gas/sparc/sparc.exp
index 0504b8f..8178e0c 100644
--- a/gas/testsuite/gas/sparc/sparc.exp
+++ b/gas/testsuite/gas/sparc/sparc.exp
@@ -79,6 +79,7 @@ if [istarget sparc*-*-*] {
run_dump_test "hpcvis3"
run_dump_test "ima"
run_dump_test "crypto"
+ run_dump_test "xcrypto"
run_dump_test "cbcond"
run_dump_test "pause"
run_dump_test "cfr"
@@ -89,6 +90,9 @@ if [istarget sparc*-*-*] {
run_dump_test "ld_st_fsr"
run_dump_test "edge"
run_dump_test "flush"
+ run_dump_test "mwait"
+ run_dump_test "mcdper"
+ run_dump_test "sparc5vis4"
run_list_test "pr4587" ""
}
diff --git a/gas/testsuite/gas/sparc/sparc5vis4.d b/gas/testsuite/gas/sparc/sparc5vis4.d
new file mode 100644
index 0000000..61a2de8
--- /dev/null
+++ b/gas/testsuite/gas/sparc/sparc5vis4.d
@@ -0,0 +1,38 @@
+#as: -Av9m
+#objdump: -dr
+#name: sparc SPARC5 and VIS4.0
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 87 b0 48 22 subxc %g1, %g2, %g3
+ 4: 87 b0 48 62 subxccc %g1, %g2, %g3
+ 8: 91 b0 a4 84 fpadd8 %f2, %f4, %f8
+ c: 99 b2 24 ca fpadds8 %f8, %f10, %f12
+ 10: a1 b3 24 ee fpaddus8 %f12, %f14, %f16
+ 14: a9 b4 24 72 fpaddus16 %f16, %f18, %f20
+ 18: 83 b0 86 84 fpcmple8 %f2, %f4, %g1
+ 1c: 85 b1 07 86 fpcmpgt8 %f4, %f6, %g2
+ 20: 87 b1 a5 c8 fpcmpule16 %f6, %f8, %g3
+ 24: 89 b2 25 6a fpcmpugt16 %f8, %f10, %g4
+ 28: 8b b2 a5 ec fpcmpule32 %f10, %f12, %g5
+ 2c: 8d b3 25 8e fpcmpugt32 %f12, %f14, %g6
+ 30: a5 b3 a3 b0 fpmax8 %f14, %f16, %f18
+ 34: ad b4 a3 d4 fpmax16 %f18, %f20, %f22
+ 38: b5 b5 a3 f8 fpmax32 %f22, %f24, %f26
+ 3c: bd b6 ab bc fpmaxu8 %f26, %f28, %f30
+ 40: 87 b7 ab c1 fpmaxu16 %f30, %f32, %f34
+ 44: 8f b0 eb e5 fpmaxu32 %f34, %f36, %f38
+ 48: 97 b1 e3 49 fpmin8 %f38, %f40, %f42
+ 4c: 9f b2 e3 6d fpmin16 %f42, %f44, %f46
+ 50: a7 b3 e3 91 fpmin32 %f46, %f48, %f50
+ 54: af b4 eb 55 fpminu8 %f50, %f52, %f54
+ 58: b7 b5 eb 79 fpminu16 %f54, %f56, %f58
+ 5c: bf b6 eb 9d fpminu32 %f58, %f60, %f62
+ 60: 8d b0 aa 84 fpsub8 %f2, %f4, %f6
+ 64: 95 b1 aa c8 fpsubs8 %f6, %f8, %f10
+ 68: 9d b2 aa ec fpsubus8 %f10, %f12, %f14
+ 6c: a5 b3 aa 70 fpsubus16 %f14, %f16, %f18
+ 70: bf b0 09 3f faligndatai %f0, %f62, %f4, %f62
diff --git a/gas/testsuite/gas/sparc/sparc5vis4.s b/gas/testsuite/gas/sparc/sparc5vis4.s
new file mode 100644
index 0000000..4bd7942
--- /dev/null
+++ b/gas/testsuite/gas/sparc/sparc5vis4.s
@@ -0,0 +1,31 @@
+# Test SPARC5/VIS4 instructions
+ .text
+ subxc %g1, %g2, %g3
+ subxccc %g1, %g2, %g3
+ fpadd8 %f2, %f4, %f8
+ fpadds8 %f8, %f10, %f12
+ fpaddus8 %f12, %f14, %f16
+ fpaddus16 %f16, %f18, %f20
+ fpcmple8 %f2, %f4, %g1
+ fpcmpgt8 %f4, %f6, %g2
+ fpcmpule16 %f6, %f8, %g3
+ fpcmpugt16 %f8, %f10, %g4
+ fpcmpule32 %f10, %f12, %g5
+ fpcmpugt32 %f12, %f14, %g6
+ fpmax8 %f14, %f16, %f18
+ fpmax16 %f18, %f20, %f22
+ fpmax32 %f22, %f24, %f26
+ fpmaxu8 %f26, %f28, %f30
+ fpmaxu16 %f30, %f32, %f34
+ fpmaxu32 %f34, %f36, %f38
+ fpmin8 %f38, %f40, %f42
+ fpmin16 %f42, %f44, %f46
+ fpmin32 %f46, %f48, %f50
+ fpminu8 %f50, %f52, %f54
+ fpminu16 %f54, %f56, %f58
+ fpminu32 %f58, %f60, %f62
+ fpsub8 %f2, %f4, %f6
+ fpsubs8 %f6, %f8, %f10
+ fpsubus8 %f10, %f12, %f14
+ fpsubus16 %f14, %f16, %f18
+ faligndatai %f0, %f62, %f4, %f62
diff --git a/gas/testsuite/gas/sparc/xcrypto.d b/gas/testsuite/gas/sparc/xcrypto.d
new file mode 100644
index 0000000..fbf8ba3
--- /dev/null
+++ b/gas/testsuite/gas/sparc/xcrypto.d
@@ -0,0 +1,105 @@
+#as: -Av9m
+#objdump: -dr
+#name: OSA2015 crypto instructions
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 83 b0 29 00 xmpmul 0
+ 4: 83 b0 29 01 xmpmul 1
+ 8: 83 b0 29 02 xmpmul 2
+ c: 83 b0 29 03 xmpmul 3
+ 10: 83 b0 29 04 xmpmul 4
+ 14: 83 b0 29 05 xmpmul 5
+ 18: 83 b0 29 06 xmpmul 6
+ 1c: 83 b0 29 07 xmpmul 7
+ 20: 83 b0 29 08 xmpmul 8
+ 24: 83 b0 29 09 xmpmul 9
+ 28: 83 b0 29 0a xmpmul 0xa
+ 2c: 83 b0 29 0b xmpmul 0xb
+ 30: 83 b0 29 0c xmpmul 0xc
+ 34: 83 b0 29 0d xmpmul 0xd
+ 38: 83 b0 29 0e xmpmul 0xe
+ 3c: 83 b0 29 0f xmpmul 0xf
+ 40: 83 b0 29 10 xmpmul 0x10
+ 44: 83 b0 29 11 xmpmul 0x11
+ 48: 83 b0 29 12 xmpmul 0x12
+ 4c: 83 b0 29 13 xmpmul 0x13
+ 50: 83 b0 29 14 xmpmul 0x14
+ 54: 83 b0 29 15 xmpmul 0x15
+ 58: 83 b0 29 16 xmpmul 0x16
+ 5c: 83 b0 29 17 xmpmul 0x17
+ 60: 83 b0 29 18 xmpmul 0x18
+ 64: 83 b0 29 19 xmpmul 0x19
+ 68: 83 b0 29 1a xmpmul 0x1a
+ 6c: 83 b0 29 1b xmpmul 0x1b
+ 70: 83 b0 29 1c xmpmul 0x1c
+ 74: 83 b0 29 1d xmpmul 0x1d
+ 78: 83 b0 29 1e xmpmul 0x1e
+ 7c: 83 b0 29 1f xmpmul 0x1f
+ 80: 83 b0 29 20 xmontmul 0
+ 84: 83 b0 29 21 xmontmul 1
+ 88: 83 b0 29 22 xmontmul 2
+ 8c: 83 b0 29 23 xmontmul 3
+ 90: 83 b0 29 24 xmontmul 4
+ 94: 83 b0 29 25 xmontmul 5
+ 98: 83 b0 29 26 xmontmul 6
+ 9c: 83 b0 29 27 xmontmul 7
+ a0: 83 b0 29 28 xmontmul 8
+ a4: 83 b0 29 29 xmontmul 9
+ a8: 83 b0 29 2a xmontmul 0xa
+ ac: 83 b0 29 2b xmontmul 0xb
+ b0: 83 b0 29 2c xmontmul 0xc
+ b4: 83 b0 29 2d xmontmul 0xd
+ b8: 83 b0 29 2e xmontmul 0xe
+ bc: 83 b0 29 2f xmontmul 0xf
+ c0: 83 b0 29 30 xmontmul 0x10
+ c4: 83 b0 29 31 xmontmul 0x11
+ c8: 83 b0 29 32 xmontmul 0x12
+ cc: 83 b0 29 33 xmontmul 0x13
+ d0: 83 b0 29 34 xmontmul 0x14
+ d4: 83 b0 29 35 xmontmul 0x15
+ d8: 83 b0 29 36 xmontmul 0x16
+ dc: 83 b0 29 37 xmontmul 0x17
+ e0: 83 b0 29 38 xmontmul 0x18
+ e4: 83 b0 29 39 xmontmul 0x19
+ e8: 83 b0 29 3a xmontmul 0x1a
+ ec: 83 b0 29 3b xmontmul 0x1b
+ f0: 83 b0 29 3c xmontmul 0x1c
+ f4: 83 b0 29 3d xmontmul 0x1d
+ f8: 83 b0 29 3e xmontmul 0x1e
+ fc: 83 b0 29 3f xmontmul 0x1f
+ 100: 83 b0 29 40 xmontsqr 0
+ 104: 83 b0 29 41 xmontsqr 1
+ 108: 83 b0 29 42 xmontsqr 2
+ 10c: 83 b0 29 43 xmontsqr 3
+ 110: 83 b0 29 44 xmontsqr 4
+ 114: 83 b0 29 45 xmontsqr 5
+ 118: 83 b0 29 46 xmontsqr 6
+ 11c: 83 b0 29 47 xmontsqr 7
+ 120: 83 b0 29 48 xmontsqr 8
+ 124: 83 b0 29 49 xmontsqr 9
+ 128: 83 b0 29 4a xmontsqr 0xa
+ 12c: 83 b0 29 4b xmontsqr 0xb
+ 130: 83 b0 29 4c xmontsqr 0xc
+ 134: 83 b0 29 4d xmontsqr 0xd
+ 138: 83 b0 29 4e xmontsqr 0xe
+ 13c: 83 b0 29 4f xmontsqr 0xf
+ 140: 83 b0 29 50 xmontsqr 0x10
+ 144: 83 b0 29 51 xmontsqr 0x11
+ 148: 83 b0 29 52 xmontsqr 0x12
+ 14c: 83 b0 29 53 xmontsqr 0x13
+ 150: 83 b0 29 54 xmontsqr 0x14
+ 154: 83 b0 29 55 xmontsqr 0x15
+ 158: 83 b0 29 56 xmontsqr 0x16
+ 15c: 83 b0 29 57 xmontsqr 0x17
+ 160: 83 b0 29 58 xmontsqr 0x18
+ 164: 83 b0 29 59 xmontsqr 0x19
+ 168: 83 b0 29 5a xmontsqr 0x1a
+ 16c: 83 b0 29 5b xmontsqr 0x1b
+ 170: 83 b0 29 5c xmontsqr 0x1c
+ 174: 83 b0 29 5d xmontsqr 0x1d
+ 178: 83 b0 29 5e xmontsqr 0x1e
+ 17c: 83 b0 29 5f xmontsqr 0x1f
diff --git a/gas/testsuite/gas/sparc/xcrypto.s b/gas/testsuite/gas/sparc/xcrypto.s
new file mode 100644
index 0000000..d793ce0
--- /dev/null
+++ b/gas/testsuite/gas/sparc/xcrypto.s
@@ -0,0 +1,98 @@
+# Test OSA2015 CRYPTO instructions
+ .text
+ xmpmul 0
+ xmpmul 1
+ xmpmul 2
+ xmpmul 3
+ xmpmul 4
+ xmpmul 5
+ xmpmul 6
+ xmpmul 7
+ xmpmul 8
+ xmpmul 9
+ xmpmul 10
+ xmpmul 11
+ xmpmul 12
+ xmpmul 13
+ xmpmul 14
+ xmpmul 15
+ xmpmul 16
+ xmpmul 17
+ xmpmul 18
+ xmpmul 19
+ xmpmul 20
+ xmpmul 21
+ xmpmul 22
+ xmpmul 23
+ xmpmul 24
+ xmpmul 25
+ xmpmul 26
+ xmpmul 27
+ xmpmul 28
+ xmpmul 29
+ xmpmul 30
+ xmpmul 31
+ xmontmul 0
+ xmontmul 1
+ xmontmul 2
+ xmontmul 3
+ xmontmul 4
+ xmontmul 5
+ xmontmul 6
+ xmontmul 7
+ xmontmul 8
+ xmontmul 9
+ xmontmul 10
+ xmontmul 11
+ xmontmul 12
+ xmontmul 13
+ xmontmul 14
+ xmontmul 15
+ xmontmul 16
+ xmontmul 17
+ xmontmul 18
+ xmontmul 19
+ xmontmul 20
+ xmontmul 21
+ xmontmul 22
+ xmontmul 23
+ xmontmul 24
+ xmontmul 25
+ xmontmul 26
+ xmontmul 27
+ xmontmul 28
+ xmontmul 29
+ xmontmul 30
+ xmontmul 31
+ xmontsqr 0
+ xmontsqr 1
+ xmontsqr 2
+ xmontsqr 3
+ xmontsqr 4
+ xmontsqr 5
+ xmontsqr 6
+ xmontsqr 7
+ xmontsqr 8
+ xmontsqr 9
+ xmontsqr 10
+ xmontsqr 11
+ xmontsqr 12
+ xmontsqr 13
+ xmontsqr 14
+ xmontsqr 15
+ xmontsqr 16
+ xmontsqr 17
+ xmontsqr 18
+ xmontsqr 19
+ xmontsqr 20
+ xmontsqr 21
+ xmontsqr 22
+ xmontsqr 23
+ xmontsqr 24
+ xmontsqr 25
+ xmontsqr 26
+ xmontsqr 27
+ xmontsqr 28
+ xmontsqr 29
+ xmontsqr 30
+ xmontsqr 31