[binutils][Arm] Fix Branch Future relocation handling and testisms

bfd/ChangeLog:
2019-05-21  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR/target 24460
	* elf32-arm.c (get_value_helper): Remove.
	(elf32_arm_final_link_relocate): Fix branch future relocations.

gas/ChangeLog:
2019-05-21  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* testsuite/gas/arm/armv8_1-m-bf.d: Allow different branch target naming
	conventions.
	* testsuite/gas/arm/armv8_1-m-bfl.d: Likewise.
	* testsuite/gas/arm/armv8_1-m-bfcsel.d: Likewise.
	* testsuite/gas/arm/armv8_1-m-loloop.d: Likewise.
	* testsuite/gas/arm/armv8_1-m-bf-rel.d: Skip for vxworks.
	* testsuite/gas/arm/armv8_1-m-bf-rela.d: New test.
	* testsuite/gas/arm/armv8_1-m-bfl-rel.d: Skip for vxworks.
	* testsuite/gas/arm/armv8_1-m-bfl-rela.d: New test.

ld/ChangeLog:
2019-05-21  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* testsuite/ld-arm/arm-elf.exp: Add tests
	* testsuite/ld-arm/bfs-0.s: New test.
	* testsuite/ld-arm/bfs-1.s: New test.
	* testsuite/ld-arm/branch-futures.d: New test.

9 files changed, 51 insertions, 15 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index fbfa00b..90fc3c3 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2019-05-21  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	* testsuite/gas/arm/armv8_1-m-bf.d: Allow different branch target naming
+	conventions.
+	* testsuite/gas/arm/armv8_1-m-bfl.d: Likewise.
+	* testsuite/gas/arm/armv8_1-m-bfcsel.d: Likewise.
+	* testsuite/gas/arm/armv8_1-m-loloop.d: Likewise.
+	* testsuite/gas/arm/armv8_1-m-bf-rel.d: Skip for vxworks.
+	* testsuite/gas/arm/armv8_1-m-bf-rela.d: New test.
+	* testsuite/gas/arm/armv8_1-m-bfl-rel.d: Skip for vxworks.
+	* testsuite/gas/arm/armv8_1-m-bfl-rela.d: New test.
+
 2019-05-21  John Darrington <john@darrington.wattle.id.au>
 
 	* expr.c (literal_prefix_dollar_hex): New variable.
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d
index e429c13..bdb265c 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d
@@ -1,7 +1,7 @@
-#name: Valid Armv8.1-M Mainline BF instruction with relocation
+#name: Valid Armv8.1-M Mainline BF instruction with REL
 #as: -march=armv8.1-m.main
 #objdump: -dr --prefix-addresses --show-raw-insn
-#skip: *-*-pe *-wince-* 
+#skip: *-*-pe *-wince-* *-vxworks
 
 .*: +file format .*arm.*
 
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-rela.d b/gas/testsuite/gas/arm/armv8_1-m-bf-rela.d
new file mode 100644
index 0000000..d363d09
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-rela.d
@@ -0,0 +1,12 @@
+#name: Valid Armv8.1-M Mainline BF instruction with RELA
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+#source:armv8_1-m-bf-rel.s
+#noskip: *-vxworks
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f0c0 e001 	bf	2, 00000004 <.target\+0x4>
+			0: R_ARM_THM_BF16	.target-0x4
+
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf.d b/gas/testsuite/gas/arm/armv8_1-m-bf.d
index dd30b2a..99de065 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bf.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf.d
@@ -5,9 +5,9 @@
 .*: +file format .*arm.*
 
 Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f0c0 e803 	bf	2, 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> f0c0 e803 	bf	2, 0000000a <.*>
 0[0-9a-f]+ <[^>]+> 4609      	mov	r1, r1
-0[0-9a-f]+ <[^>]+> f140 e801 	bf	4, 0000000c <foo\+0xc>
+0[0-9a-f]+ <[^>]+> f140 e801 	bf	4, 0000000c <.*>
 0[0-9a-f]+ <[^>]+> 460a      	mov	r2, r1
 0[0-9a-f]+ <[^>]+> 4613      	mov	r3, r2
 0[0-9a-f]+ <[^>]+> 4614      	mov	r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d
index a498f06..b66e929 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d
@@ -5,8 +5,8 @@
 .*: +file format .*arm.*
 
 Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f080 e803 	bfcsel	2, 0000000a <foo\+0xa>, 4, eq
+0[0-9a-f]+ <[^>]+> f080 e803 	bfcsel	2, 0000000a <.*>, 4, eq
 0[0-9a-f]+ <[^>]+> 4609      	mov	r1, r1
-0[0-9a-f]+ <[^>]+> d000      	beq.n	0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> d000      	beq.n	0000000a <.*>
 0[0-9a-f]+ <[^>]+> 4613      	mov	r3, r2
 0[0-9a-f]+ <[^>]+> 4614      	mov	r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d b/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d
index 13c6bf1..951074c 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d
@@ -1,7 +1,7 @@
-#name: Valid Armv8.1-M Mainline BFL instruction with relocation
+#name: Valid Armv8.1-M Mainline BFL instruction with REL
 #as: -march=armv8.1-m.main
 #objdump: -dr --prefix-addresses --show-raw-insn
-#skip: *-*-pe *-wince-*
+#skip: *-*-pe *-wince-* *-vxworks
 
 .*: +file format .*arm.*
 
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d b/gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d
new file mode 100644
index 0000000..291d10b
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d
@@ -0,0 +1,12 @@
+#name: Valid Armv8.1-M Mainline BFL instruction with RELA
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+#source: armv8_1-m-bfl-rel.s
+#noskip: *-vxworks
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f080 c001 	bfl	2, 00000004 <.target\+0x4>
+			0: R_ARM_THM_BF18	.target-0x4
+
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl.d b/gas/testsuite/gas/arm/armv8_1-m-bfl.d
index e15636b..b28d0b1 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bfl.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl.d
@@ -5,9 +5,9 @@
 .*: +file format .*arm.*
 
 Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f080 c803 	bfl	2, 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> f080 c803 	bfl	2, 0000000a <.*>
 0[0-9a-f]+ <[^>]+> 4608      	mov	r0, r1
-0[0-9a-f]+ <[^>]+> f100 c801 	bfl	4, 0000000c <foo\+0xc>
+0[0-9a-f]+ <[^>]+> f100 c801 	bfl	4, 0000000c <.*>
 0[0-9a-f]+ <[^>]+> 460a      	mov	r2, r1
 0[0-9a-f]+ <[^>]+> 4613      	mov	r3, r2
 0[0-9a-f]+ <[^>]+> 4614      	mov	r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-loloop.d b/gas/testsuite/gas/arm/armv8_1-m-loloop.d
index 1e02b82..20506c6 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-loloop.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-loloop.d
@@ -6,12 +6,12 @@
 .*: +file format .*arm.*
 
 Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f042 c00d 	wls	lr, r2, 0000001c <foo\+0x1c>
+0[0-9a-f]+ <[^>]+> f042 c00d 	wls	lr, r2, 0000001c <.*>
 0[0-9a-f]+ <[^>]+> f042 e001 	dls	lr, r2
 0[0-9a-f]+ <[^>]+> f04e e001 	dls	lr, lr
-0[0-9a-f]+ <[^>]+> f00f c009 	le	lr, 00000000 <foo>
-0[0-9a-f]+ <[^>]+> f02f c00b 	le	00000000 <foo>
-0[0-9a-f]+ <[^>]+> f00f c24b 	le	lr, fffffb84 <foo\+0xfffffb84>
-0[0-9a-f]+ <[^>]+> f02f c007 	le	00000010 <foo\+0x10>
+0[0-9a-f]+ <[^>]+> f00f c009 	le	lr, 00000000 <.*>
+0[0-9a-f]+ <[^>]+> f02f c00b 	le	00000000 <.*>
+0[0-9a-f]+ <[^>]+> f00f c24b 	le	lr, fffffb84 <.*>
+0[0-9a-f]+ <[^>]+> f02f c007 	le	00000010 <.*>
 0[0-9a-f]+ <[^>]+> 4613      	mov	r3, r2
 #...