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| author | Jan Beulich <jbeulich@suse.com> | 2019-07-01 08:37:40 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2019-07-01 08:37:40 +0200 |
| commit | c3949f432f4f7e4a776bd15e10dad56593abeb47 (patch) | |
| tree | bbec6b4c7d278e8d2456b396ea52e364254ff64c /gas | |
| parent | 5641ec015a191e0584fd4cae57bb3262f7a51735 (diff) | |
| download | gdb-c3949f432f4f7e4a776bd15e10dad56593abeb47.zip gdb-c3949f432f4f7e4a776bd15e10dad56593abeb47.tar.gz gdb-c3949f432f4f7e4a776bd15e10dad56593abeb47.tar.bz2 | |
x86: limit ImmExt abuse
In quite a few cases ImmExt gets used when there's not really any
immediate, but rather a degenerate ModR/M byte. ENCL{S,U} show how this
case is supposed to be dealt with. Eliminate most abuses, leaving in
place (for now) only ones where process_immext() is involved.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 7 | ||||
| -rw-r--r-- | gas/config/tc-i386.c | 23 |
2 files changed, 17 insertions, 13 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 2206e3d..d78bbc9 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,12 @@ 2019-07-01 Jan Beulich <jbeulich@suse.com> + * config/tc-i386.c (output_insn): Adjust recognition of xFENCE + insns. Move PadLock special case of prefix emission to 3-byte + long base opcode handling. + (i386_index_check): Check for CpuPadLock instead of ImmExt. + +2019-07-01 Jan Beulich <jbeulich@suse.com> + * config/tc-i386.c (optimize_encoding): Handle AND / OR with both operands being the same register. * doc/c-i386.texi: Update -O2 documentation. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 56ccd12..1741c0e 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -8283,7 +8283,7 @@ output_insn (void) Xfence instructions. */ if (i.tm.base_opcode != 0xf18 && i.tm.base_opcode != 0xf0d - && i.tm.base_opcode != 0xfae + && i.tm.base_opcode != 0xfaef8 && (i.has_regmmx || i.tm.cpu_flags.bitfield.cpummx || i.tm.cpu_flags.bitfield.cpua3dnow @@ -8331,12 +8331,9 @@ output_insn (void) unsigned int prefix; if (avoid_fence - && i.tm.base_opcode == 0xfae - && i.operands == 1 - && i.imm_operands == 1 - && (i.op[0].imms->X_add_number == 0xe8 - || i.op[0].imms->X_add_number == 0xf0 - || i.op[0].imms->X_add_number == 0xf8)) + && (i.tm.base_opcode == 0xfaee8 + || i.tm.base_opcode == 0xfaef0 + || i.tm.base_opcode == 0xfaef8)) { /* Encode lfence, mfence, and sfence as f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ @@ -8365,17 +8362,17 @@ output_insn (void) if (i.tm.base_opcode & 0xff000000) { prefix = (i.tm.base_opcode >> 24) & 0xff; - add_prefix (prefix); + if (!i.tm.cpu_flags.bitfield.cpupadlock + || prefix != REPE_PREFIX_OPCODE + || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) + add_prefix (prefix); } break; case 2: if ((i.tm.base_opcode & 0xff0000) != 0) { prefix = (i.tm.base_opcode >> 16) & 0xff; - if (!i.tm.cpu_flags.bitfield.cpupadlock - || prefix != REPE_PREFIX_OPCODE - || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) - add_prefix (prefix); + add_prefix (prefix); } break; case 1: @@ -9788,7 +9785,7 @@ i386_index_check (const char *operand_string) enum flag_code addr_mode = i386_addressing_mode (); if (current_templates->start->opcode_modifier.isstring - && !current_templates->start->opcode_modifier.immext + && !current_templates->start->cpu_flags.bitfield.cpupadlock && (current_templates->end[-1].opcode_modifier.isstring || i.mem_operands)) { |