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authorPrzemyslaw Wirkus <przemyslaw.wirkus@arm.com>2021-03-12 14:18:59 +0000
committerPrzemyslaw Wirkus <przemyslaw.wirkus@arm.com>2021-03-12 14:20:46 +0000
commit7fce7ea986bc66d4af3c21d4f6ab2a987f3aac46 (patch)
tree08c07d9e7fde9270e9257a54796fc0df721abe83 /gas
parent203a206d14e4892bc4ab9448e08617506b5d613d (diff)
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aarch64: Add few missing system registers
This patch adds few missing system registers to GAS: LORC_EL1, LOREA_EL1, LORN_EL1, LORSA_EL1, ICC_CTLR_EL3, ICC_SRE_ELX, ICH_VTR_EL2. gas/ChangeLog: 2021-03-02 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * testsuite/gas/aarch64/illegal-sysreg-7.d: New test. * testsuite/gas/aarch64/illegal-sysreg-7.l: New test. * testsuite/gas/aarch64/illegal-sysreg-7.s: New test. * testsuite/gas/aarch64/sysreg-7.d: New test. * testsuite/gas/aarch64/sysreg-7.s: New test. opcodes/ChangeLog: 2021-03-02 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1, icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog8
-rw-r--r--gas/testsuite/gas/aarch64/illegal-sysreg-7.d2
-rw-r--r--gas/testsuite/gas/aarch64/illegal-sysreg-7.l2
-rw-r--r--gas/testsuite/gas/aarch64/illegal-sysreg-7.s2
-rw-r--r--gas/testsuite/gas/aarch64/sysreg-7.d25
-rw-r--r--gas/testsuite/gas/aarch64/sysreg-7.s20
6 files changed, 59 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 01161d5..79332f0 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * testsuite/gas/aarch64/illegal-sysreg-7.d: New test.
+ * testsuite/gas/aarch64/illegal-sysreg-7.l: New test.
+ * testsuite/gas/aarch64/illegal-sysreg-7.s: New test.
+ * testsuite/gas/aarch64/sysreg-7.d: New test.
+ * testsuite/gas/aarch64/sysreg-7.s: New test.
+
2021-03-12 Clément Chigot <clement.chigot@atos.net>
* config/tc-ppc.c (ppc_xcoff_text_section, ppc_xcoff_data_section,
diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-7.d b/gas/testsuite/gas/aarch64/illegal-sysreg-7.d
new file mode 100644
index 0000000..d7a11ed
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-7.d
@@ -0,0 +1,2 @@
+#source: illegal-sysreg-7.s
+#warning_output: illegal-sysreg-7.l
diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-7.l b/gas/testsuite/gas/aarch64/illegal-sysreg-7.l
new file mode 100644
index 0000000..1db54b3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-7.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Warning: specified register cannot be written to at operand 1 -- `msr ich_vtr_el2,x0'
diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-7.s b/gas/testsuite/gas/aarch64/illegal-sysreg-7.s
new file mode 100644
index 0000000..311e182
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-7.s
@@ -0,0 +1,2 @@
+/* Write to R/O system registers. */
+msr ich_vtr_el2, x0
diff --git a/gas/testsuite/gas/aarch64/sysreg-7.d b/gas/testsuite/gas/aarch64/sysreg-7.d
new file mode 100644
index 0000000..1564f53
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg-7.d
@@ -0,0 +1,25 @@
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+
+.*: d538a460 mrs x0, lorc_el1
+.*: d538a420 mrs x0, lorea_el1
+.*: d538a440 mrs x0, lorn_el1
+.*: d538a400 mrs x0, lorsa_el1
+.*: d53ecc80 mrs x0, icc_ctlr_el3
+.*: d538cca0 mrs x0, icc_sre_el1
+.*: d53cc9a0 mrs x0, icc_sre_el2
+.*: d53ecca0 mrs x0, icc_sre_el3
+.*: d53ccb20 mrs x0, ich_vtr_el2
+.*: d518a460 msr lorc_el1, x0
+.*: d518a420 msr lorea_el1, x0
+.*: d518a440 msr lorn_el1, x0
+.*: d518a400 msr lorsa_el1, x0
+.*: d51ecc80 msr icc_ctlr_el3, x0
+.*: d518cca0 msr icc_sre_el1, x0
+.*: d51cc9a0 msr icc_sre_el2, x0
+.*: d51ecca0 msr icc_sre_el3, x0
diff --git a/gas/testsuite/gas/aarch64/sysreg-7.s b/gas/testsuite/gas/aarch64/sysreg-7.s
new file mode 100644
index 0000000..3d438d1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg-7.s
@@ -0,0 +1,20 @@
+/* Read from system registers. */
+mrs x0, lorc_el1
+mrs x0, lorea_el1
+mrs x0, lorn_el1
+mrs x0, lorsa_el1
+mrs x0, icc_ctlr_el3
+mrs x0, icc_sre_el1
+mrs x0, icc_sre_el2
+mrs x0, icc_sre_el3
+mrs x0, ich_vtr_el2
+
+/* Write to system registers. */
+msr lorc_el1, x0
+msr lorea_el1, x0
+msr lorn_el1, x0
+msr lorsa_el1, x0
+msr icc_ctlr_el3, x0
+msr icc_sre_el1, x0
+msr icc_sre_el2, x0
+msr icc_sre_el3, x0