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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-06-30 22:44:12 +0200 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-07-01 07:28:40 -0600 |
| commit | c62d5acf8478b0cb3c93130cb15fa76aecd93a02 (patch) | |
| tree | c2921c7aa874b3b427e38e487a09fa8a54915e6b /gas | |
| parent | 259a2647dc158e196e4e03719cdc6bb0ff657d1d (diff) | |
| download | gdb-c62d5acf8478b0cb3c93130cb15fa76aecd93a02.zip gdb-c62d5acf8478b0cb3c93130cb15fa76aecd93a02.tar.gz gdb-c62d5acf8478b0cb3c93130cb15fa76aecd93a02.tar.bz2 | |
RISC-V: Add support for the Zvkn ISA extension
Zvkn is part of the vector crypto extensions.
Zvkn is shorthand for the following set of extensions:
- Zvkned
- Zvknhb
- Zvbb
- Zvkt
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvkn extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvkn.d: New test.
* testsuite/gas/riscv/zvkn.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/testsuite/gas/riscv/zvkn.d | 45 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zvkn.s | 36 |
2 files changed, 81 insertions, 0 deletions
diff --git a/gas/testsuite/gas/riscv/zvkn.d b/gas/testsuite/gas/riscv/zvkn.d new file mode 100644 index 0000000..abb92b9 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkn.d @@ -0,0 +1,45 @@ +#as: -march=rv64gc_zvkn +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+a280a277[ ]+vaesdf.vv[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+06860257[ ]+vandn.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+04860257[ ]+vandn.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+0685c257[ ]+vandn.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+0485c257[ ]+vandn.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+4a852257[ ]+vbrev.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+48852257[ ]+vbrev.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a842257[ ]+vbrev8.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+48842257[ ]+vbrev8.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a862257[ ]+vclz.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+48862257[ ]+vclz.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a86a257[ ]+vctz.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+4886a257[ ]+vctz.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a872257[ ]+vcpop.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+48872257[ ]+vcpop.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+56860257[ ]+vrol.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+54860257[ ]+vrol.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+5685c257[ ]+vrol.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+5485c257[ ]+vrol.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+52860257[ ]+vror.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+50860257[ ]+vror.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+5285c257[ ]+vror.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+5085c257[ ]+vror.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+52803257[ ]+vror.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+548fb257[ ]+vror.vi[ ]+v4,v8,63,v0.t +[ ]+[0-9a-f]+:[ ]+d6860257[ ]+vwsll.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+d4860257[ ]+vwsll.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+d685c257[ ]+vwsll.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+d485c257[ ]+vwsll.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+d6803257[ ]+vwsll.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+d48fb257[ ]+vwsll.vi[ ]+v4,v8,31,v0.t + diff --git a/gas/testsuite/gas/riscv/zvkn.s b/gas/testsuite/gas/riscv/zvkn.s new file mode 100644 index 0000000..44e8f17 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkn.s @@ -0,0 +1,36 @@ + vaesdf.vv v4, v8 + vsha2ch.vv v4, v8, v12 + vandn.vv v4, v8, v12 + vandn.vv v4, v8, v12, v0.t + vandn.vx v4, v8, a1 + vandn.vx v4, v8, a1, v0.t + vbrev.v v4, v8 + vbrev.v v4, v8, v0.t + vbrev8.v v4, v8 + vbrev8.v v4, v8, v0.t + vrev8.v v4, v8 + vrev8.v v4, v8, v0.t + vrev8.v v4, v8 + vrev8.v v4, v8, v0.t + vclz.v v4, v8 + vclz.v v4, v8, v0.t + vctz.v v4, v8 + vctz.v v4, v8, v0.t + vcpop.v v4, v8 + vcpop.v v4, v8, v0.t + vrol.vv v4, v8, v12 + vrol.vv v4, v8, v12, v0.t + vrol.vx v4, v8, a1 + vrol.vx v4, v8, a1, v0.t + vror.vv v4, v8, v12 + vror.vv v4, v8, v12, v0.t + vror.vx v4, v8, a1 + vror.vx v4, v8, a1, v0.t + vror.vi v4, v8, 0 + vror.vi v4, v8, 63, v0.t + vwsll.vv v4, v8, v12 + vwsll.vv v4, v8, v12, v0.t + vwsll.vx v4, v8, a1 + vwsll.vx v4, v8, a1, v0.t + vwsll.vi v4, v8, 0 + vwsll.vi v4, v8, 31, v0.t |