aarch64: Fix MOVPRFX markup for bf16 conversions

bfcvt converts a .S input to a .H output, so any predicated movprfx
needs to operate on .S rather than .H.  In common with SVE2 narrowing
top operations, bfcvtnt doesn't accept movprfx.

2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
	* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
	Remove C_SCAN_MOVPRFX for SVE bfcvtnt.

gas/
	* testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than
	.s for the movprfx.
	* testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly.
	* testsuite/gas/aarch64/sve-movprfx_28.d,
	* testsuite/gas/aarch64/sve-movprfx_28.l,
	* testsuite/gas/aarch64/sve-movprfx_28.s: New test.

6 files changed, 95 insertions, 2 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 8bad416..cff57b0 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than
+	.s for the movprfx.
+	* testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly.
+	* testsuite/gas/aarch64/sve-movprfx_28.d,
+	* testsuite/gas/aarch64/sve-movprfx_28.l,
+	* testsuite/gas/aarch64/sve-movprfx_28.s: New test.
+
 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 
 	* config/tc-i386.c (output_disp): Tighten base_opcode check.
diff --git a/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d b/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d
index 4ba95b8..e51bd11 100644
--- a/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d
+++ b/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d
@@ -23,5 +23,5 @@ Disassembly of section \.text:
  *[0-9a-f]+:	64e34440 	bfmlalt	z0\.s, z2\.h, z3\.h\[0\]
  *[0-9a-f]+:	0420bc20 	movprfx	z0, z1
  *[0-9a-f]+:	658aa040 	bfcvt	z0\.h, p0/m, z2\.s
- *[0-9a-f]+:	04512020 	movprfx	z0\.h, p0/m, z1\.h
+ *[0-9a-f]+:	04912020 	movprfx	z0\.s, p0/m, z1\.s
  *[0-9a-f]+:	658aa040 	bfcvt	z0\.h, p0/m, z2\.s
diff --git a/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s b/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s
index c322532..d46da21 100644
--- a/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s
+++ b/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s
@@ -27,5 +27,5 @@ movprfx z0, z1
 bfcvt z0.h, p0/m, z2.s
 
 # Predicated movprfx + bfcvt
-movprfx z0.h, p0/m, z1.h
+movprfx z0.s, p0/m, z1.s
 bfcvt z0.h, p0/m, z2.s
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_28.d b/gas/testsuite/gas/aarch64/sve-movprfx_28.d
new file mode 100644
index 0000000..808d07d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_28.d
@@ -0,0 +1,31 @@
+#source: sve-movprfx_28.s
+#warning_output: sve-movprfx_28.l
+#as: -I$srcdir/$subdir --generate-missing-build-notes=no
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+:	04912420 	movprfx	z0\.s, p1/m, z1\.s
+[^:]+:	658aa440 	bfcvt	z0\.h, p1/m, z2\.s
+[^:]+:	04902420 	movprfx	z0\.s, p1/z, z1\.s
+[^:]+:	658aa440 	bfcvt	z0\.h, p1/m, z2\.s
+[^:]+:	04512420 	movprfx	z0\.h, p1/m, z1\.h
+[^:]+:	658aa440 	bfcvt	z0\.h, p1/m, z2\.s  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04502420 	movprfx	z0\.h, p1/z, z1\.h
+[^:]+:	658aa440 	bfcvt	z0\.h, p1/m, z2\.s  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	0420bc20 	movprfx	z0, z1
+[^:]+:	658aa440 	bfcvt	z0\.h, p1/m, z2\.s
+[^:]+:	0420bc20 	movprfx	z0, z1
+[^:]+:	648aa440 	bfcvtnt	z0\.h, p1/m, z2\.s  // note: SVE `movprfx' compatible instruction expected
+[^:]+:	04912420 	movprfx	z0\.s, p1/m, z1\.s
+[^:]+:	648aa440 	bfcvtnt	z0\.h, p1/m, z2\.s  // note: SVE `movprfx' compatible instruction expected
+[^:]+:	04902420 	movprfx	z0\.s, p1/z, z1\.s
+[^:]+:	648aa440 	bfcvtnt	z0\.h, p1/m, z2\.s  // note: SVE `movprfx' compatible instruction expected
+[^:]+:	04512420 	movprfx	z0\.h, p1/m, z1\.h
+[^:]+:	648aa440 	bfcvtnt	z0\.h, p1/m, z2\.s  // note: SVE `movprfx' compatible instruction expected
+[^:]+:	04502420 	movprfx	z0\.h, p1/z, z1\.h
+[^:]+:	648aa440 	bfcvtnt	z0\.h, p1/m, z2\.s  // note: SVE `movprfx' compatible instruction expected
+[^:]+:	d65f03c0 	ret
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_28.l b/gas/testsuite/gas/aarch64/sve-movprfx_28.l
new file mode 100644
index 0000000..a75289c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_28.l
@@ -0,0 +1,8 @@
+[^:]*: Assembler messages:
+.*:15: Warning: register size not compatible with previous `movprfx' at operand 1 -- `bfcvt z0.h,p1/m,z2.s'
+.*:19: Warning: register size not compatible with previous `movprfx' at operand 1 -- `bfcvt z0.h,p1/m,z2.s'
+.*:27: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
+.*:31: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
+.*:35: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
+.*:39: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
+.*:43: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_28.s b/gas/testsuite/gas/aarch64/sve-movprfx_28.s
new file mode 100644
index 0000000..9ef0ad5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_28.s
@@ -0,0 +1,45 @@
+	.text
+	.arch armv8-a+sve+bf16
+
+f:
+	// OK
+	movprfx z0.s, p1/m, z1.s
+	bfcvt z0.h, p1/m, z2.s
+
+	// OK
+	movprfx z0.s, p1/z, z1.s
+	bfcvt z0.h, p1/m, z2.s
+
+	// Wrong size
+	movprfx z0.h, p1/m, z1.h
+	bfcvt z0.h, p1/m, z2.s
+
+	// Wrong size
+	movprfx z0.h, p1/z, z1.h
+	bfcvt z0.h, p1/m, z2.s
+
+	// OK
+	movprfx z0, z1
+	bfcvt z0.h, p1/m, z2.s
+
+	// Not prefixable
+	movprfx z0, z1
+	bfcvtnt z0.h, p1/m, z2.s
+
+	// Not prefixable
+	movprfx z0.s, p1/m, z1.s
+	bfcvtnt z0.h, p1/m, z2.s
+
+	// Not prefixable
+	movprfx z0.s, p1/z, z1.s
+	bfcvtnt z0.h, p1/m, z2.s
+
+	// Not prefixable
+	movprfx z0.h, p1/m, z1.h
+	bfcvtnt z0.h, p1/m, z2.s
+
+	// Not prefixable
+	movprfx z0.h, p1/z, z1.h
+	bfcvtnt z0.h, p1/m, z2.s
+
+	ret