diff options
author | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-11-07 16:38:59 +0000 |
---|---|---|
committer | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-11-07 16:42:36 +0000 |
commit | df6780137dc9d832db8c5525ecc760acdbcde5c9 (patch) | |
tree | 13d42c9514e6d84686a0f15776cf27c70854cf32 /gas/testsuite | |
parent | 8ae2d3d9eabfd3dff6a540e7789e368e8d75fbce (diff) | |
download | gdb-df6780137dc9d832db8c5525ecc760acdbcde5c9.zip gdb-df6780137dc9d832db8c5525ecc760acdbcde5c9.tar.gz gdb-df6780137dc9d832db8c5525ecc760acdbcde5c9.tar.bz2 |
[binutils][aarch64] Bfloat16 enablement [2/X]
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.
This patch introduces the following BFloat16 instructions to the
aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b],
bfcvtn2.
Committed on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (vectype_to_qualifier): Special case the
S_2H operand qualifier.
* doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions.
* testsuite/gas/aarch64/bfloat16.d: New test.
* testsuite/gas/aarch64/bfloat16.s: New test.
* testsuite/gas/aarch64/illegal-bfloat16.d: New test.
* testsuite/gas/aarch64/illegal-bfloat16.l: New test.
* testsuite/gas/aarch64/illegal-bfloat16.s: New test.
* testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test.
* testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test.
include/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros.
(AARCH64_ARCH_V8_6): Include BFloat16 feature macros.
(enum aarch64_opnd_qualifier): Introduce new operand qualifier
AARCH64_OPND_QLF_S_2H.
(enum aarch64_insn_class): Introduce new class "bfloat16".
(BFLOAT16_SVE_INSNC): New feature set for bfloat16
instructions to support the movprfx constraint.
opcodes/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
in reglane special case.
* aarch64-dis-2.c (aarch64_opcode_lookup_1,
aarch64_find_next_opcode): Account for new instructions.
* aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
in reglane special case.
* aarch64-opc.c (struct operand_qualifier_data): Add data for
new AARCH64_OPND_QLF_S_2H qualifier.
* aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
(aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve,
aarch64_feature_bfloat16_bfmmla4): New feature sets.
(BFLOAT_SVE, BFLOAT): New feature set macros.
(BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros
to define BFloat16 instructions.
(aarch64_opcode_table): Define new instructions bfdot,
bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
bfcvtn2, bfcvt.
Regression tested on aarch64-elf.
Is it ok for trunk?
Regards,
Mihail
Diffstat (limited to 'gas/testsuite')
-rw-r--r-- | gas/testsuite/gas/aarch64/bfloat16.d | 56 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/bfloat16.s | 70 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/illegal-bfloat16.d | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/illegal-bfloat16.l | 95 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/illegal-bfloat16.s | 67 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d | 27 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s | 31 |
7 files changed, 350 insertions, 0 deletions
diff --git a/gas/testsuite/gas/aarch64/bfloat16.d b/gas/testsuite/gas/aarch64/bfloat16.d new file mode 100644 index 0000000..78d10cb --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16.d @@ -0,0 +1,56 @@ +#as: -march=armv8.6-a+bf16+sve +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0000000000000000 <\.text>: + *[0-9a-f]+: 647b82b1 bfdot z17\.s, z21\.h, z27\.h + *[0-9a-f]+: 64608000 bfdot z0\.s, z0\.h, z0\.h + *[0-9a-f]+: 647d42b1 bfdot z17\.s, z21\.h, z5\.h\[3\] + *[0-9a-f]+: 64784000 bfdot z0\.s, z0\.h, z0\.h\[3\] + *[0-9a-f]+: 64604000 bfdot z0\.s, z0\.h, z0\.h\[0\] + *[0-9a-f]+: 647be6b1 bfmmla z17\.s, z21\.h, z27\.h + *[0-9a-f]+: 6460e400 bfmmla z0\.s, z0\.h, z0\.h + *[0-9a-f]+: 658ab6b1 bfcvt z17\.h, p5/m, z21\.s + *[0-9a-f]+: 658aa000 bfcvt z0\.h, p0/m, z0\.s + *[0-9a-f]+: 648ab6b1 bfcvtnt z17\.h, p5/m, z21\.s + *[0-9a-f]+: 648aa000 bfcvtnt z0\.h, p0/m, z0\.s + *[0-9a-f]+: 64fb86b1 bfmlalt z17\.s, z21\.h, z27\.h + *[0-9a-f]+: 64e08400 bfmlalt z0\.s, z0\.h, z0\.h + *[0-9a-f]+: 64fb82b1 bfmlalb z17\.s, z21\.h, z27\.h + *[0-9a-f]+: 64e08000 bfmlalb z0\.s, z0\.h, z0\.h + *[0-9a-f]+: 64e546b1 bfmlalt z17\.s, z21\.h, z5\.h\[0\] + *[0-9a-f]+: 64f84c00 bfmlalt z0\.s, z0\.h, z0\.h\[7\] + *[0-9a-f]+: 64e542b1 bfmlalb z17\.s, z21\.h, z5\.h\[0\] + *[0-9a-f]+: 64f84800 bfmlalb z0\.s, z0\.h, z0\.h\[7\] + *[0-9a-f]+: 2e5bfeb1 bfdot v17\.2s, v21\.4h, v27\.4h + *[0-9a-f]+: 2e40fc00 bfdot v0\.2s, v0\.4h, v0\.4h + *[0-9a-f]+: 6e5bfeb1 bfdot v17\.4s, v21\.8h, v27\.8h + *[0-9a-f]+: 6e40fc00 bfdot v0\.4s, v0\.8h, v0\.8h + *[0-9a-f]+: 0f7bfab1 bfdot v17\.2s, v21\.4h, v27\.2h\[3\] + *[0-9a-f]+: 0f60f800 bfdot v0\.2s, v0\.4h, v0\.2h\[3\] + *[0-9a-f]+: 4f7bfab1 bfdot v17\.4s, v21\.8h, v27\.2h\[3\] + *[0-9a-f]+: 4f60f800 bfdot v0\.4s, v0\.8h, v0\.2h\[3\] + *[0-9a-f]+: 0f5bf2b1 bfdot v17\.2s, v21\.4h, v27\.2h\[0\] + *[0-9a-f]+: 0f40f000 bfdot v0\.2s, v0\.4h, v0\.2h\[0\] + *[0-9a-f]+: 4f5bf2b1 bfdot v17\.4s, v21\.8h, v27\.2h\[0\] + *[0-9a-f]+: 4f40f000 bfdot v0\.4s, v0\.8h, v0\.2h\[0\] + *[0-9a-f]+: 6e5beeb1 bfmmla v17\.4s, v21\.8h, v27\.8h + *[0-9a-f]+: 6e40ec00 bfmmla v0\.4s, v0\.8h, v0\.8h + *[0-9a-f]+: 2edbfeb1 bfmlalb v17\.4s, v21\.8h, v27\.8h + *[0-9a-f]+: 2ec0fc00 bfmlalb v0\.4s, v0\.8h, v0\.8h + *[0-9a-f]+: 6edbfeb1 bfmlalt v17\.4s, v21\.8h, v27\.8h + *[0-9a-f]+: 6ec0fc00 bfmlalt v0\.4s, v0\.8h, v0\.8h + *[0-9a-f]+: 0fcff2b1 bfmlalb v17\.4s, v21\.8h, v15\.h\[0\] + *[0-9a-f]+: 0ff0f800 bfmlalb v0\.4s, v0\.8h, v0\.h\[7\] + *[0-9a-f]+: 4fcff2b1 bfmlalt v17\.4s, v21\.8h, v15\.h\[0\] + *[0-9a-f]+: 4ff0f800 bfmlalt v0\.4s, v0\.8h, v0\.h\[7\] + *[0-9a-f]+: 0ea16ab1 bfcvtn v17\.4h, v21\.4s + *[0-9a-f]+: 0ea16800 bfcvtn v0\.4h, v0\.4s + *[0-9a-f]+: 4ea16ab1 bfcvtn2 v17\.8h, v21\.4s + *[0-9a-f]+: 4ea16800 bfcvtn2 v0\.8h, v0\.4s + *[0-9a-f]+: 1e6342b1 bfcvt h17, s21 + *[0-9a-f]+: 1e634000 bfcvt h0, s0 diff --git a/gas/testsuite/gas/aarch64/bfloat16.s b/gas/testsuite/gas/aarch64/bfloat16.s new file mode 100644 index 0000000..5850a9c --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16.s @@ -0,0 +1,70 @@ +/* The instructions with non-zero register numbers are there to ensure we have + the correct argument positioning (i.e. check that the first argument is at + the end of the word etc). + The instructions with all-zero register numbers are to ensure the previous + encoding didn't just "happen" to fit -- so that if we change the registers + that changes the correct part of the word. + Each of the numbered patterns begin and end with a 1, so we can replace + them with all-zeros and see the entire range has changed. */ + +// SVE +bfdot z17.s, z21.h, z27.h +bfdot z0.s, z0.h, z0.h + +bfdot z17.s, z21.h, z5.h[3] +bfdot z0.s, z0.h, z0.h[3] +bfdot z0.s, z0.h, z0.h[0] + +bfmmla z17.s, z21.h, z27.h +bfmmla z0.s, z0.h, z0.h + +bfcvt z17.h, p5/m, z21.s +bfcvt z0.h, p0/m, z0.s +bfcvtnt z17.h, p5/m, z21.s +bfcvtnt z0.h, p0/m, z0.s + +bfmlalt z17.s, z21.h, z27.h +bfmlalt z0.s, z0.h, z0.h +bfmlalb z17.s, z21.h, z27.h +bfmlalb z0.s, z0.h, z0.h + +bfmlalt z17.s, z21.h, z5.h[0] +bfmlalt z0.s, z0.h, z0.h[7] +bfmlalb z17.s, z21.h, z5.h[0] +bfmlalb z0.s, z0.h, z0.h[7] + +// SIMD +bfdot v17.2s, v21.4h, v27.4h +bfdot v0.2s, v0.4h, v0.4h +bfdot v17.4s, v21.8h, v27.8h +bfdot v0.4s, v0.8h, v0.8h + +bfdot v17.2s, v21.4h, v27.2h[3] +bfdot v0.2s, v0.4h, v0.2h[3] +bfdot v17.4s, v21.8h, v27.2h[3] +bfdot v0.4s, v0.8h, v0.2h[3] +bfdot v17.2s, v21.4h, v27.2h[0] +bfdot v0.2s, v0.4h, v0.2h[0] +bfdot v17.4s, v21.8h, v27.2h[0] +bfdot v0.4s, v0.8h, v0.2h[0] + +bfmmla v17.4s, v21.8h, v27.8h +bfmmla v0.4s, v0.8h, v0.8h + +bfmlalb v17.4s, v21.8h, v27.8h +bfmlalb v0.4s, v0.8h, v0.8h +bfmlalt v17.4s, v21.8h, v27.8h +bfmlalt v0.4s, v0.8h, v0.8h + +bfmlalb v17.4s, v21.8h, v15.h[0] +bfmlalb v0.4s, v0.8h, v0.h[7] +bfmlalt v17.4s, v21.8h, v15.h[0] +bfmlalt v0.4s, v0.8h, v0.h[7] + +bfcvtn v17.4h, v21.4s +bfcvtn v0.4h, v0.4s +bfcvtn2 v17.8h, v21.4s +bfcvtn2 v0.8h, v0.4s + +bfcvt h17, s21 +bfcvt h0, s0 diff --git a/gas/testsuite/gas/aarch64/illegal-bfloat16.d b/gas/testsuite/gas/aarch64/illegal-bfloat16.d new file mode 100644 index 0000000..275ac33 --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-bfloat16.d @@ -0,0 +1,4 @@ +#name: Illegal Bfloat16 instructions +#as: -march=armv8.6-a+bf16+sve +#source: illegal-bfloat16.s +#error_output: illegal-bfloat16.l diff --git a/gas/testsuite/gas/aarch64/illegal-bfloat16.l b/gas/testsuite/gas/aarch64/illegal-bfloat16.l new file mode 100644 index 0000000..c20f132 --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-bfloat16.l @@ -0,0 +1,95 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot z0\.s,z1\.h,z2\.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfdot z0\.s, z1\.h, z2\.h +[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot z0\.s,z1\.h,z3\.s\[3\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfdot z0\.s, z1\.h, z3\.h\[3\] +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `bfdot z0\.s,z1\.h,z3\.h\[4\]' +[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfdot z0\.s,z1\.h,z8\.h\[3\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmmla z0\.s,z1\.h,z2\.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmmla z0\.s, z1\.h, z2\.h +[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt z0\.h,p1/z,z2\.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfcvt z0\.h, p1/m, z2\.s +[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt z0\.h,p1/m,z2\.h' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfcvt z0\.h, p1/m, z2\.s +[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvtnt z0\.h,p1/z,z2\.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfcvtnt z0\.h, p1/m, z2\.s +[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvtnt z0\.h,p1/m,z2\.h' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfcvtnt z0\.h, p1/m, z2\.s +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt z0\.s,z0\.h,z0\.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlalt z0\.s, z0\.h, z0\.h +[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h' +[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalt z0\.s,z0\.h,z32\.h' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalt z0\.s,z0\.h,z0\.h\[8\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt z0\.s,z0\.h,z0\.s\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlalt z0\.s, z0\.h, z0\.h\[0\] +[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfmlalt z0\.s,z0\.h,z8\.h\[0\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb z0\.s,z0\.h,z0\.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlalb z0\.s, z0\.h, z0\.h +[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalb z0\.s,z32\.h,z0\.h' +[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalb z0\.s,z0\.h,z32\.h' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalb z0\.s,z0\.h,z0\.h\[8\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb z0\.s,z0\.h,z0\.s\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlalb z0\.s, z0\.h, z0\.h\[0\] +[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalb z0\.s,z32\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfmlalb z0\.s,z0\.h,z8\.h\[0\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot v0\.2s,v1\.4h,v2\.2s\[3\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfdot v0\.2s, v1\.4h, v2\.2h\[3\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: bfdot v0\.4s, v1\.8h, v2\.2h\[3\] +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `bfdot v0\.4s,v1\.8h,v2\.2h\[4\]' +[^ :]+:[0-9]+: Error: invalid element size 8 and vector size combination s at operand 3 -- `bfmmla v0\.4s,v1\.8h,v2\.8s' +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmmla v0\.4s,v1\.4h,v2\.8h' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmmla v0\.4s, v1\.8h, v2\.8h +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb v0\.4s,v0\.4h,v0\.8h' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlalb v0\.4s, v0\.8h, v0\.8h +[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb v32\.4s,v0\.8h,v0\.8h' +[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalb v0\.4s,v32\.8h,v0\.8h' +[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector register -- `bfmlalb v0\.4s,v0\.8h,v32\.8h' +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt v0\.4s,v0\.8h,v0\.4h' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlalt v0\.4s, v0\.8h, v0\.8h +[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt v32\.4s,v0\.8h,v0\.8h' +[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalt v0\.4s,v32\.8h,v0\.8h' +[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector register -- `bfmlalt v0\.4s,v0\.8h,v32\.8h' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalb v0\.4s,v0\.8h,v0\.h\[8\]' +[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb v32\.4s,v0\.8h,v0\.h\[0\]' +[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalb v0\.4s,v32\.8h,v0\.h\[0\]' +[^ :]+:[0-9]+: Error: register number out of range 0 to 15 at operand 3 -- `bfmlalb v0\.4s,v0\.8h,v16\.h\[0\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb v0\.4s,v0\.4h,v0\.h\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlalb v0\.4s, v0\.8h, v0\.h\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb v0\.4s,v0\.8h,v0\.s\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlalb v0\.4s, v0\.8h, v0\.h\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt v0\.4s,v0\.8h,v0\.s\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlalt v0\.4s, v0\.8h, v0\.h\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt v0\.4s,v0\.4h,v0\.h\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlalt v0\.4s, v0\.8h, v0\.h\[0\] +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalt v0\.4s,v0\.8h,v0\.h\[8\]' +[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt v32\.4s,v0\.8h,v0\.h\[0\]' +[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalt v0\.4s,v32\.8h,v0\.h\[0\]' +[^ :]+:[0-9]+: Error: register number out of range 0 to 15 at operand 3 -- `bfmlalt v0\.4s,v0\.8h,v16\.h\[0\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt h0,h1' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfcvt h0, s1 diff --git a/gas/testsuite/gas/aarch64/illegal-bfloat16.s b/gas/testsuite/gas/aarch64/illegal-bfloat16.s new file mode 100644 index 0000000..6b53334 --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-bfloat16.s @@ -0,0 +1,67 @@ +// SVE +bfdot z0.s, z1.h, z2.s // Fails from size types + +bfdot z0.s, z1.h, z3.s[3] // Fails from size types +bfdot z0.s, z1.h, z3.h[4] // Fails from index size +bfdot z0.s, z1.h, z8.h[3] // Fails from vector number + +bfmmla z0.s, z1.h, z2.s // Fails from size types + +bfcvt z0.h, p1/z, z2.s // Fails from merge type +bfcvt z0.h, p1/m, z2.h // Fails from size type + +bfcvtnt z0.h, p1/z, z2.s // Fails from merge type +bfcvtnt z0.h, p1/m, z2.h // Fails from size type + +bfmlalt z0.s, z0.h, z0.s // Fails from size type +bfmlalt z32.s, z0.h, z0.h +bfmlalt z0.s, z32.h, z0.h +bfmlalt z0.s, z0.h, z32.h + +bfmlalt z0.s, z0.h, z0.h[8] // Fails from index size +bfmlalt z0.s, z0.h, z0.s[0] // Fails from size type +bfmlalt z32.s, z0.h, z0.h[0] +bfmlalt z0.s, z32.h, z0.h[0] +bfmlalt z0.s, z0.h, z8.h[0] // Fails from vector index + +bfmlalb z0.s, z0.h, z0.s // Fails from size type +bfmlalb z32.s, z0.h, z0.h +bfmlalb z0.s, z32.h, z0.h +bfmlalb z0.s, z0.h, z32.h + +bfmlalb z0.s, z0.h, z0.h[8] // Fails from index size +bfmlalb z0.s, z0.h, z0.s[0] // Fails from size type +bfmlalb z32.s, z0.h, z0.h[0] +bfmlalb z0.s, z32.h, z0.h[0] +bfmlalb z0.s, z0.h, z8.h[0] // Fails from vector index + +// SIMD +bfdot v0.2s, v1.4h, v2.2s[3] // Fails from size types +bfdot v0.4s, v1.8h, v2.2h[4] // Fails from index size + +bfmmla v0.4s, v1.8h, v2.8s // Fails from size types +bfmmla v0.4s, v1.4h, v2.8h // Fails from size types + +bfmlalb v0.4s, v0.4h, v0.8h +bfmlalb v32.4s, v0.8h, v0.8h +bfmlalb v0.4s, v32.8h, v0.8h +bfmlalb v0.4s, v0.8h, v32.8h +bfmlalt v0.4s, v0.8h, v0.4h +bfmlalt v32.4s, v0.8h, v0.8h +bfmlalt v0.4s, v32.8h, v0.8h +bfmlalt v0.4s, v0.8h, v32.8h + +bfmlalb v0.4s, v0.8h, v0.h[8] +bfmlalb v32.4s, v0.8h, v0.h[0] +bfmlalb v0.4s, v32.8h, v0.h[0] +bfmlalb v0.4s, v0.8h, v16.h[0] +bfmlalb v0.4s, v0.4h, v0.h[0] +bfmlalb v0.4s, v0.8h, v0.s[0] +bfmlalt v0.4s, v0.8h, v0.s[0] +bfmlalt v0.4s, v0.4h, v0.h[0] +bfmlalt v0.4s, v0.8h, v0.h[8] +bfmlalt v32.4s, v0.8h, v0.h[0] +bfmlalt v0.4s, v32.8h, v0.h[0] +bfmlalt v0.4s, v0.8h, v16.h[0] + +bfcvt h0, h1 // Fails from size types diff --git a/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d b/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d new file mode 100644 index 0000000..a797158 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d @@ -0,0 +1,27 @@ +#as: -march=armv8.6-a+bf16+sve +#objdump: -dr + +.* file format .* + + +Disassembly of section \.text: + +0000000000000000 <\.text>: + *[0-9a-f]+: 0420bc20 movprfx z0, z1 + *[0-9a-f]+: 64638040 bfdot z0\.s, z2\.h, z3\.h + *[0-9a-f]+: 0420bc20 movprfx z0, z1 + *[0-9a-f]+: 64634040 bfdot z0\.s, z2\.h, z3\.h\[0\] + *[0-9a-f]+: 0420bc20 movprfx z0, z1 + *[0-9a-f]+: 6463e440 bfmmla z0\.s, z2\.h, z3\.h + *[0-9a-f]+: 0420bc20 movprfx z0, z1 + *[0-9a-f]+: 64e38040 bfmlalb z0\.s, z2\.h, z3\.h + *[0-9a-f]+: 0420bc20 movprfx z0, z1 + *[0-9a-f]+: 64e38440 bfmlalt z0\.s, z2\.h, z3\.h + *[0-9a-f]+: 0420bc20 movprfx z0, z1 + *[0-9a-f]+: 64e34040 bfmlalb z0\.s, z2\.h, z3\.h\[0\] + *[0-9a-f]+: 0420bc20 movprfx z0, z1 + *[0-9a-f]+: 64e34440 bfmlalt z0\.s, z2\.h, z3\.h\[0\] + *[0-9a-f]+: 0420bc20 movprfx z0, z1 + *[0-9a-f]+: 658aa040 bfcvt z0\.h, p0/m, z2\.s + *[0-9a-f]+: 04512020 movprfx z0\.h, p0/m, z1\.h + *[0-9a-f]+: 658aa040 bfcvt z0\.h, p0/m, z2\.s diff --git a/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s b/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s new file mode 100644 index 0000000..c322532 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s @@ -0,0 +1,31 @@ +.text +.arch armv8.2-a+bf16+sve + +movprfx z0, z1 +bfdot z0.s, z2.h, z3.h + +movprfx z0, z1 +bfdot z0.s, z2.h, z3.h[0] + +movprfx z0, z1 +bfmmla z0.s, z2.h, z3.h + +movprfx z0, z1 +bfmlalb z0.s, z2.h, z3.h + +movprfx z0, z1 +bfmlalt z0.s, z2.h, z3.h + +movprfx z0, z1 +bfmlalb z0.s, z2.h, z3.h[0] + +movprfx z0, z1 +bfmlalt z0.s, z2.h, z3.h[0] + +# Unpredicated movprfx + bfcvt +movprfx z0, z1 +bfcvt z0.h, p0/m, z2.s + +# Predicated movprfx + bfcvt +movprfx z0.h, p0/m, z1.h +bfcvt z0.h, p0/m, z2.s |