RISC-V: Improve li expansion for better code density.

li is a pseudo instruction in RISC-V, it might expand to more than one
instructions if the immediate value can't fit addi or lui, but the
assembler will always using 4-byte instructions during expansion.

For example:

 li a0, 0x12345001

will expand into

 12345537 lui a0,0x12345
 00150513 addi a0,a0,1

but addi could be compress into

 0505 addi a0,a0,1

It because load_const use macro_build to emit instructions,
and macro_build call append_insn, and expect it will compress
it if possible, but the fact is append_insn never compress anything,

So this patch redirect the li expansion flow to normal instruction
emission flow via md_assemble, added md_assemblef as an wrapper for
that for easier emit instruction with printf-style argument to build
instruction.

gas/ChangeLog:

	* tc-riscv.c (md_assemblef): New.
	(load_const) Use md_assemblef instead of macro_build to emit
	instructions.
	* testsuite/gas/riscv/li32.d: New.
	* testsuite/gas/riscv/li32.s: Ditto.
	* testsuite/gas/riscv/li64.d: Ditto.
	* testsuite/gas/riscv/li64.s: Ditto.

4 files changed, 75 insertions, 0 deletions

diff --git a/gas/testsuite/gas/riscv/li32.d b/gas/testsuite/gas/riscv/li32.d
new file mode 100644
index 0000000..ff0827d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/li32.d
@@ -0,0 +1,17 @@
+#as: -march=rv32ic -mabi=ilp32
+#objdump: -dr
+
+.*:     file format elf32-littleriscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[^:]+:[ 	]+6521[ 	]+lui[ 	]+a0,0x8
+[^:]+:[ 	]+0505[ 	]+addi[ 	]+a0,a0,1
+[^:]+:[ 	]+6509[ 	]+lui[ 	]+a0,0x2
+[^:]+:[ 	]+f0150513[ 	]+addi[ 	]+a0,a0,-255 # .*
+[^:]+:[ 	]+12345537[ 	]+lui[ 	]+a0,0x12345
+[^:]+:[ 	]+0505[ 	]+addi[ 	]+a0,a0,1
+[^:]+:[ 	]+f2345537[ 	]+lui[ 	]+a0,0xf2345
+[^:]+:[ 	]+0505[ 	]+addi[ 	]+a0,a0,1
diff --git a/gas/testsuite/gas/riscv/li32.s b/gas/testsuite/gas/riscv/li32.s
new file mode 100644
index 0000000..1930cd8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/li32.s
@@ -0,0 +1,5 @@
+target:
+        li  a0, 0x8001
+        li  a0, 0x1f01
+        li  a0, 0x12345001
+        li  a0, 0xf2345001
diff --git a/gas/testsuite/gas/riscv/li64.d b/gas/testsuite/gas/riscv/li64.d
new file mode 100644
index 0000000..5421303
--- /dev/null
+++ b/gas/testsuite/gas/riscv/li64.d
@@ -0,0 +1,44 @@
+#as: -march=rv64ic -mabi=lp64
+#objdump: -dr
+
+.*:     file format elf64-littleriscv
+
+
+Disassembly of section .text:
+
+0000000000000000 <target>:
+[^:]+:[ 	]+6521[ 	]+lui[ 	]+a0,0x8
+[^:]+:[ 	]+2505[ 	]+addiw[ 	]+a0,a0,1
+[^:]+:[ 	]+6509[ 	]+lui[ 	]+a0,0x2
+[^:]+:[ 	]+f015051b[ 	]+addiw[ 	]+a0,a0,-255
+[^:]+:[ 	]+12345537[ 	]+lui[ 	]+a0,0x12345
+[^:]+:[ 	]+2505[ 	]+addiw[ 	]+a0,a0,1
+[^:]+:[ 	]+000f2537[ 	]+lui[ 	]+a0,0xf2
+[^:]+:[ 	]+3455051b[ 	]+addiw[ 	]+a0,a0,837
+[^:]+:[ 	]+0532[ 	]+slli[ 	]+a0,a0,0xc
+[^:]+:[ 	]+0505[ 	]+addi[ 	]+a0,a0,1
+[^:]+:[ 	]+00f12537[ 	]+lui[ 	]+a0,0xf12
+[^:]+:[ 	]+3455051b[ 	]+addiw[ 	]+a0,a0,837
+[^:]+:[ 	]+0532[ 	]+slli[ 	]+a0,a0,0xc
+[^:]+:[ 	]+0505[ 	]+addi[ 	]+a0,a0,1
+[^:]+:[ 	]+ff010537[ 	]+lui[ 	]+a0,0xff010
+[^:]+:[ 	]+f015051b[ 	]+addiw[ 	]+a0,a0,-255
+[^:]+:[ 	]+054e[ 	]+slli[ 	]+a0,a0,0x13
+[^:]+:[ 	]+80150513[ 	]+addi[ 	]+a0,a0,-2047 # .*
+[^:]+:[ 	]+0536[ 	]+slli[ 	]+a0,a0,0xd
+[^:]+:[ 	]+f0150513[ 	]+addi[ 	]+a0,a0,-255
+[^:]+:[ 	]+0010051b[ 	]+addiw[ 	]+a0,zero,1
+[^:]+:[ 	]+151a[ 	]+slli[ 	]+a0,a0,0x26
+[^:]+:[ 	]+1565[ 	]+addi[ 	]+a0,a0,-7
+[^:]+:[ 	]+0536[ 	]+slli[ 	]+a0,a0,0xd
+[^:]+:[ 	]+34550513[ 	]+addi[ 	]+a0,a0,837
+[^:]+:[ 	]+0532[ 	]+slli[ 	]+a0,a0,0xc
+[^:]+:[ 	]+0505[ 	]+addi[ 	]+a0,a0,1
+[^:]+:[ 	]+01fc4537[ 	]+lui[ 	]+a0,0x1fc4
+[^:]+:[ 	]+c915051b[ 	]+addiw[ 	]+a0,a0,-879
+[^:]+:[ 	]+0536[ 	]+slli[ 	]+a0,a0,0xd
+[^:]+:[ 	]+1565[ 	]+addi[ 	]+a0,a0,-7
+[^:]+:[ 	]+0536[ 	]+slli[ 	]+a0,a0,0xd
+[^:]+:[ 	]+34550513[ 	]+addi[ 	]+a0,a0,837 # .*
+[^:]+:[ 	]+0532[ 	]+slli[ 	]+a0,a0,0xc
+[^:]+:[ 	]+0505[ 	]+addi[ 	]+a0,a0,1
diff --git a/gas/testsuite/gas/riscv/li64.s b/gas/testsuite/gas/riscv/li64.s
new file mode 100644
index 0000000..aab19eb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/li64.s
@@ -0,0 +1,9 @@
+target:
+        li  a0, 0x8001
+        li  a0, 0x1f01
+        li  a0, 0x12345001
+        li  a0, 0xf2345001
+        li  a0, 0xf12345001
+        li  a0, 0xff00ff00ff001f01
+        li  a0, 0x7ffffffff2345001
+        li  a0, 0x7f0f243ff2345001