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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2019-08-22 10:20:01 +0100 |
|---|---|---|
| committer | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2019-08-22 10:20:01 +0100 |
| commit | a051e2f3e0c1cedf4be0e1fedcd383fd203c769c (patch) | |
| tree | 6683cd0307952826230ed8d7319ce0f67a082592 /gas/testsuite | |
| parent | baf46cd78048e1b959462567556e1de1ef6b9039 (diff) | |
| download | gdb-a051e2f3e0c1cedf4be0e1fedcd383fd203c769c.zip gdb-a051e2f3e0c1cedf4be0e1fedcd383fd203c769c.tar.gz gdb-a051e2f3e0c1cedf4be0e1fedcd383fd203c769c.tar.bz2 | |
[AArch64][gas] Update MTE system register encodings
The MTE specification adjusted the encoding of the TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12 system registers.
This patch brings binutils up to date.
The references for the encodings are at:
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsre0_el1 (also contains TFSR_EL12 description)
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el1
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el2
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el3
Tested check-gas for aarch64-none-elf.
opcodes/
* aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
(aarch64_sys_reg_supported_p): Update checks for the above.
gas/
* testsuite/gas/aarch64/sysreg-4.d: Update expected disassembly for
tfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12 system registers.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg-4.d | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/gas/testsuite/gas/aarch64/sysreg-4.d b/gas/testsuite/gas/aarch64/sysreg-4.d index bc3d0bd..c25536d 100644 --- a/gas/testsuite/gas/aarch64/sysreg-4.d +++ b/gas/testsuite/gas/aarch64/sysreg-4.d @@ -21,21 +21,21 @@ Disassembly of section \.text: .*: d5380388 mrs x8, id_pfr2_el1 .*: d53b42e1 mrs x1, tco .*: d53b42e2 mrs x2, tco -.*: d5386621 mrs x1, tfsre0_el1 -.*: d5386501 mrs x1, tfsr_el1 -.*: d53c6502 mrs x2, tfsr_el2 -.*: d53e6603 mrs x3, tfsr_el3 -.*: d53d660c mrs x12, tfsr_el12 +.*: d5385621 mrs x1, tfsre0_el1 +.*: d5385601 mrs x1, tfsr_el1 +.*: d53c5602 mrs x2, tfsr_el2 +.*: d53e5603 mrs x3, tfsr_el3 +.*: d53d560c mrs x12, tfsr_el12 .*: d53810a1 mrs x1, rgsr_el1 .*: d53810c3 mrs x3, gcr_el1 .*: d5390084 mrs x4, gmid_el1 .*: d51b42e1 msr tco, x1 .*: d51b42e2 msr tco, x2 -.*: d5186621 msr tfsre0_el1, x1 -.*: d5186501 msr tfsr_el1, x1 -.*: d51c6502 msr tfsr_el2, x2 -.*: d51e6603 msr tfsr_el3, x3 -.*: d51d660c msr tfsr_el12, x12 +.*: d5185621 msr tfsre0_el1, x1 +.*: d5185601 msr tfsr_el1, x1 +.*: d51c5602 msr tfsr_el2, x2 +.*: d51e5603 msr tfsr_el3, x3 +.*: d51d560c msr tfsr_el12, x12 .*: d51810a1 msr rgsr_el1, x1 .*: d51810c3 msr gcr_el1, x3 .*: d503489f msr tco, #0x8 |