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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-11-13 16:59:21 +0100 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2022-11-17 16:43:55 +0800 |
| commit | 01804a098dea7d08857eee82bcaad04676dd8ea1 (patch) | |
| tree | 69ec5662e29df0e9632fca8f788acb0383440ef2 /gas/doc | |
| parent | 4a3bc79bf4c0e89c876c930a1e95a02213277460 (diff) | |
| download | gdb-01804a098dea7d08857eee82bcaad04676dd8ea1.zip gdb-01804a098dea7d08857eee82bcaad04676dd8ea1.tar.gz gdb-01804a098dea7d08857eee82bcaad04676dd8ea1.tar.bz2 | |
RISC-V: Add T-Head Int vendor extension
This patch adds the XTheadInt extension, which provides interrupt
stack management instructions.
The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
https://github.com/riscv-non-isa/riscv-toolchain-conventions
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'gas/doc')
| -rw-r--r-- | gas/doc/c-riscv.texi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index f2a69d8..d61e8e47 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -739,6 +739,11 @@ The XTheadFmv extension provides access to the upper 32 bits of a doulbe-precisi It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf}. +@item XTheadInt +The XTheadInt extension provides access to ISR stack management instructions. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf}. + @item XTheadMac The XTheadMac extension provides multiply-accumulate instructions. |