Add support for .extCondCode, .extCoreRegister and .extAuxRegister.

gas/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/textauxregister.d: New file.
	* testsuite/gas/arc/textauxregister.s: Likewise.
	* testsuite/gas/arc/textcondcode.d: Likewise.
	* testsuite/gas/arc/textcondcode.s: Likewise.
	* testsuite/gas/arc/textcoreregister.d: Likewise.
	* testsuite/gas/arc/textcoreregister.s: Likewise.
	* testsuite/gas/arc/textpseudoop.d: Likewise.
	* testsuite/gas/arc/textpseudoop.s: Likewise.
	* testsuite/gas/arc/ld2.d: Update test.
	* testsuite/gas/arc/st.d: Likewise.
	* testsuite/gas/arc/taux.d: Likewise.
	* doc/c-arc.texi (ARC Directives): Add .extCondCode,
	.extCoreRegister and .extAuxRegister documentation.
	* config/tc-arc.c (arc_extcorereg): New function.
	(md_pseudo_table): Add .extCondCode, .extCoreRegister and
	.extAuxRegister pseudo-ops.
	(extRegister_t): New type.
	(ext_condcode, arc_aux_hash): New global variable.
	(find_opcode_match): Check for extensions.
	(preprocess_operands): Likewise.
	(md_begin): Add aux registers in a hash.
	(assemble_insn): Update use arc_flags member.
	(tokenize_extregister): New function.
	(create_extcore_section): Likewise.
	* config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Increase to 10.
	(arc_flags): Delete code, add flgp.

include/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (flag_class_t): Update.
	(ARC_OPCODE_NONE): Define.
	(ARC_OPCODE_ARCALL): Likewise.
	(ARC_OPCODE_ARCFPX): Likewise.
	(ARC_REGISTER_READONLY): Likewise.
	(ARC_REGISTER_WRITEONLY): Likewise.
	(ARC_REGISTER_NOSHORT_CUT): Likewise.
	(arc_aux_reg): Add cpu.

opcodes/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (find_format): Check for extension flags.
	(print_flags): New function.
	(print_insn_arc): Update for .extCondCode, .extCoreRegister and
	.extAuxRegister.
	* arc-ext.c (arcExtMap_coreRegName): Use
	LAST_EXTENSION_CORE_REGISTER.
	(arcExtMap_coreReadWrite): Likewise.
	(dump_ARC_extmap): Update printing.
	* arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
	(arc_aux_regs): Add cpu field.
	* arc-regs.h: Add cpu field, lower case name aux registers.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>

1 files changed, 79 insertions, 3 deletions

diff --git a/gas/doc/c-arc.texi b/gas/doc/c-arc.texi
index a237285..a3e18cf 100644
--- a/gas/doc/c-arc.texi
+++ b/gas/doc/c-arc.texi
@@ -335,11 +335,11 @@ two.  If no alignment is specified, as will set the alignment to the
 largest power of two less than or equal to the size of the symbol, up
 to a maximum of 16.
 
-@cindex @code{lcommon} directive
+@cindex @code{lcommon} directive, ARC
 @item .lcommon @var{symbol}, @var{length}[, @var{alignment}]
 The same as @code{lcomm} directive.
 
-@cindex @code{cpu} directive
+@cindex @code{cpu} directive, ARC
 @item .cpu @var{cpu}
 The @code{.cpu} directive must be followed by the desired core
 version.  Permitted values for CPU are:
@@ -362,8 +362,84 @@ Note: the @code{.cpu} directive overrides the command line option
 @code{-mcpu=@var{cpu}}; a warning is emitted when the version is not
 consistent between the two.
 
+@item .extAuxRegister @var{name}, @var{addr}, @var{mode}
+@cindex @code{extAuxRegister} directive, ARC
+Auxiliary registers can be defined in the assembler source code by
+using this directive.  The first parameter, @var{name}, is the name of the
+new auxiliary register.  The second parameter, @var{addr}, is
+address the of the auxiliary register.  The third parameter,
+@var{mode}, specifies whether the register is readable and/or writable
+and is one of:
+@table @code
+@item r
+Read only;
+
+@item w
+Write only;
+
+@item r|w
+Read and write.
+
+@end table
+
+For example:
+@example
+	.extAuxRegister mulhi, 0x12, w
+@end example
+specifies a write only extension auxiliary register, @var{mulhi} at
+address 0x12.
+
+@item .extCondCode @var{suffix}, @var{val}
+@cindex @code{extCondCode} directive, ARC
+ARC supports extensible condition codes.  This directive defines a new
+condition code, to be known by the suffix, @var{suffix} and will
+depend on the value, @var{val} in the condition code.
+
+For example:
+@example
+	.extCondCode is_busy,0x14
+	add.is_busy  r1,r2,r3
+@end example
+will only execute the @code{add} instruction if the condition code
+value is 0x14.
+
+@item .extCoreRegister @var{name}, @var{regnum}, @var{mode}, @var{shortcut}
+@cindex @code{extCoreRegister} directive, ARC
+Specifies an extension core register named @var{name} as a synonym for
+the register numbered @var{regnum}.  The register number must be
+between 32 and 59.  The third argument, @var{mode}, indicates whether
+the register is readable and/or writable and is one of:
+@table @code
+@item r
+Read only;
+
+@item w
+Write only;
+
+@item r|w
+Read and write.
+
+@end table
+
+The final parameter, @var{shortcut} indicates whether the register has
+a short cut in the pipeline.  The valid values are:
+@table @code
+@item can_shortcut
+The register has a short cut in the pipeline;
+
+@item cannot_shortcut
+The register does not have a short cut in the pipeline.
+@end table
+
+For example:
+@example
+	.extCoreRegister mlo, 57, r , can_shortcut
+@end example
+defines a read only extension core register, @code{mlo}, which is
+register 57, and can short cut the pipeline.
+
 @item .extInstruction @var{name}, @var{opcode}, @var{subopcode}, @var{suffixclass}, @var{syntaxclass}
-@cindex @code{extInstruction} directive
+@cindex @code{extInstruction} directive, ARC
 ARC allows the user to specify extension instructions.  These
 extension instructions are not macros; the assembler creates encodings
 for use of these instructions according to the specification by the