diff options
author | Jan Beulich <jbeulich@suse.com> | 2022-11-14 17:10:14 +0100 |
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committer | Jan Beulich <jbeulich@suse.com> | 2022-11-14 17:10:14 +0100 |
commit | 255571cdbf05213cc96feefb779c4158df453398 (patch) | |
tree | 92daf98c6503570887e8cfbb77b3bff6d5a9a77d /gas/config | |
parent | 36f779c06332319d9dc2d456e098a99b2540cefc (diff) | |
download | gdb-255571cdbf05213cc96feefb779c4158df453398.zip gdb-255571cdbf05213cc96feefb779c4158df453398.tar.gz gdb-255571cdbf05213cc96feefb779c4158df453398.tar.bz2 |
x86: fold special-operand insn attributes into a single enum
Attributes which aren't used together in any single insn template can be
converted from individual booleans to a single enum, as was done for a few
other attributes before. This is more space efficient. Collect together
all attributes which express special operand constraints (and which fit
the criteria for folding).
Diffstat (limited to 'gas/config')
-rw-r--r-- | gas/config/tc-i386.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index ffb17dc..71437d4 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -2075,7 +2075,7 @@ operand_size_match (const insn_template *t) { if (i.types[j].bitfield.class != Reg && i.types[j].bitfield.class != RegSIMD - && t->opcode_modifier.anysize) + && t->opcode_modifier.operandconstraint == ANY_SIZE) continue; if (t->operand_types[j].bitfield.class == Reg @@ -4522,7 +4522,7 @@ load_insn_p (void) { /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu, bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */ - if (i.tm.opcode_modifier.anysize) + if (i.tm.opcode_modifier.operandconstraint == ANY_SIZE) return 0; /* pop. */ @@ -5122,7 +5122,7 @@ md_assemble (char *line) if (!process_operands ()) return; } - else if (!quiet_warnings && i.tm.opcode_modifier.ugh) + else if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH) { /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ as_warn (_("translating to `%sp'"), i.tm.name); @@ -6035,7 +6035,7 @@ check_VecOperands (const insn_template *t) } /* Check if default mask is allowed. */ - if (t->opcode_modifier.nodefmask + if (t->opcode_modifier.operandconstraint == NO_DEFAULT_MASK && (!i.mask.reg || i.mask.reg->reg_num == 0)) { i.error = no_default_mask; @@ -6117,7 +6117,7 @@ check_VecOperands (const insn_template *t) /* For some special instructions require that destination must be distinct from source registers. */ - if (t->opcode_modifier.distinctdest) + if (t->opcode_modifier.operandconstraint == DISTINCT_DEST) { unsigned int dest_reg = i.operands - 1; @@ -7062,7 +7062,7 @@ process_suffix (void) i.suffix = QWORD_MNEM_SUFFIX; else if (i.reg_operands && (i.operands > 1 || i.types[0].bitfield.class == Reg) - && !i.tm.opcode_modifier.addrprefixopreg) + && i.tm.opcode_modifier.operandconstraint != ADDR_PREFIX_OP_REG) { unsigned int numop = i.operands; @@ -7429,7 +7429,7 @@ process_suffix (void) break; } - if (i.tm.opcode_modifier.addrprefixopreg) + if (i.tm.opcode_modifier.operandconstraint == ADDR_PREFIX_OP_REG) { gas_assert (!i.suffix); gas_assert (i.reg_operands); @@ -7823,7 +7823,7 @@ process_operands (void) } } } - else if (i.tm.opcode_modifier.implicit1stxmm0) + else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_1ST_XMM0) { gas_assert ((MAX_OPERANDS - 1) > dupl && (i.tm.opcode_modifier.vexsources @@ -7891,7 +7891,7 @@ process_operands (void) i.reg_operands--; i.tm.operands--; } - else if (i.tm.opcode_modifier.implicitquadgroup) + else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_QUAD_GROUP) { unsigned int regnum, first_reg_in_group, last_reg_in_group; @@ -7908,7 +7908,7 @@ process_operands (void) register_prefix, i.op[1].regs->reg_name, last_reg_in_group, i.tm.name); } - else if (i.tm.opcode_modifier.regkludge) + else if (i.tm.opcode_modifier.operandconstraint == REG_KLUDGE) { /* The imul $imm, %reg instruction is converted into imul $imm, %reg, %reg, and the clr %reg instruction @@ -7978,7 +7978,7 @@ process_operands (void) i.tm.base_opcode |= i.op[op].regs->reg_num; if ((i.op[op].regs->reg_flags & RegRex) != 0) i.rex |= REX_B; - if (!quiet_warnings && i.tm.opcode_modifier.ugh) + if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH) { /* Warn about some common errors, but press on regardless. The first case can be generated by gcc (<= 2.8.1). */ @@ -8205,7 +8205,7 @@ build_modrm_byte (void) unsigned int vvvv; /* Swap two source operands if needed. */ - if (i.tm.opcode_modifier.swapsources) + if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCES) { vvvv = source; source = dest; |