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| author | Alan Modra <amodra@gmail.com> | 2021-01-01 09:17:13 +1030 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2021-01-01 10:31:02 +1030 |
| commit | c2795844e6a42cf207cbb7c72c2a898f78374a52 (patch) | |
| tree | cdaeab9b9388afe2a8f8e2dcbee714ebe14f4bb7 /gas/ChangeLog-2020 | |
| parent | 57f60d20ca5ea2d2b8d30ed209619aede9683b53 (diff) | |
| download | gdb-c2795844e6a42cf207cbb7c72c2a898f78374a52.zip gdb-c2795844e6a42cf207cbb7c72c2a898f78374a52.tar.gz gdb-c2795844e6a42cf207cbb7c72c2a898f78374a52.tar.bz2 | |
ChangeLog rotation
Diffstat (limited to 'gas/ChangeLog-2020')
| -rw-r--r-- | gas/ChangeLog-2020 | 6119 |
1 files changed, 6119 insertions, 0 deletions
diff --git a/gas/ChangeLog-2020 b/gas/ChangeLog-2020 new file mode 100644 index 0000000..8cdf93b --- /dev/null +++ b/gas/ChangeLog-2020 @@ -0,0 +1,6119 @@ +2020-12-18 Alan Modra <amodra@gmail.com> + + * ecoff.c (ecoff_frob_symbol): Rename scom_section to + ecoff_scom_section, move to file scope and statically initialise. + +2020-12-16 Alan Modra <amodra@gmail.com> + + * config/obj-elf.c (obj_elf_section): Don't set elf_osabi here. + (obj_elf_type): Likewise. + +2020-12-15 Alan Modra <amodra@gmail.com> + + PR 27071 + * config/obj-elf.c (elf_obj_symbol_clone_hook): New function. + (elf_format_ops): Set symbol_clone_hook. + * config/obj-elf.h (elf_obj_symbol_clone_hook): Declare. + (obj_symbol_clone_hook): Define. + * listing.c (buffer_line): Avoid integer overflow on paper_width + set to zero. + +2020-12-14 Alan Modra <amodra@gmail.com> + + * testsuite/gas/elf/section27.s: Reorder .text, .data and .bss + so that output section order does not depend on those sections + being already created. Use ".section .text" rather than ".text". + +2020-12-13 Borislav Petkov <bp@suse.de> + + * testsuite/gas/i386/align-branch-9.s: Don't use labels that are + automatically local for ELF targets. + * testsuite/gas/i386/branch.s: Likewise. + * testsuite/gas/i386/x86-64-align-branch-9.s: Likewise. + * testsuite/gas/i386/x86-64-branch.s: Likewise. + * testsuite/gas/i386/align-branch-9.d: Adjust to match more targets. + * testsuite/gas/i386/branch.d: Likewise. + * testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-9.d: Likewise. + * testsuite/gas/i386/x86-64-branch.d: Likewise. + +2020-12-11 Sergey Belyashov <sergey.belyashov@gmail.com> + Nick Clifton <nickc@redhat.com> + + PR 27047 + * config/tc-z80.c (s_bss): New function. + (md_pseudo_table): Add bss entry. + +2020-12-10 Nelson Chu <nelson.chu@sifive.com> + + * config/tc-riscv.c (riscv_ext): New function. Use md_assemblef + to expand the zext and sext pseudos, to give them a chance to be + expanded into c-ext instructions. + (macro): Handle M_ZEXTH, M_ZEXTW, M_SEXTB and M_SEXTH. + * testsuite/gas/riscv/ext.s: New testcase. + * testsuite/gas/riscv/ext-32.d: Likewise. + * testsuite/gas/riscv/ext-64.d: Likewise. + +2020-12-10 Nelson Chu <nelson.chu@sifive.com> + + * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZICSR + and INSN_CLASS_ZIFENCEI. + * testsuite/gas/riscv/march-imply-i.s: New testcase. + * testsuite/gas/riscv/march-imply-i2p0-01.d: New testcase. The version + of i is less than 2.1, and zi* are supported in the chosen spec, so + enable the fence.i and csr instructions, also output the implicit zi* to + the arch string. + * testsuite/gas/riscv/march-imply-i2p0-02.d: Likewise, but the zi* are + not supported in the spec 2.2. Enable the related instructions since + i's version is less than 2.1, but do not output them. + * testsuite/gas/riscv/march-imply-i2p1-01.d: New testcase. The version + of i is 2.1, so don't add it's implicit zi*, and disable the related + instructions. + * testsuite/gas/riscv/march-imply-i2p1-01.l: Likewise. + * testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise, and set the zi* + explicitly, so enable the related instructions. + * testsuite/gas/riscv/march-imply-i2p0.d: Removed. + * testsuite/gas/riscv/march-imply-i2p1.d: Removed. + +2020-12-08 H.J. Lu <hongjiu.lu@intel.com> + + * config/obj-elf.c (SEC_ASSEMBLER_SHF_MASK): New. + (get_section_by_match): Also check if SEC_ASSEMBLER_SHF_MASK of + sh_flags matches. Rename info to sh_info. + (obj_elf_change_section): Don't check previous SHF_GNU_RETAIN. + Rename info to sh_info. + (obj_elf_section): Rename info to sh_info. Set sh_flags for + SHF_GNU_RETAIN. + * config/obj-elf.h (elf_section_match): Rename info to sh_info. + Add sh_flags. + * testsuite/gas/elf/elf.exp: Run section27. + * testsuite/gas/elf/section24b.d: Updated. + * testsuite/gas/elf/section27.d: New file. + * testsuite/gas/elf/section27.s: Likewise. + +2020-12-04 Andreas Krebbel <krebbel@linux.ibm.com> + + * testsuite/gas/s390/zarch-z10.s: Add tests for risbgz. + * testsuite/gas/s390/zarch-z10.d: Add regexp for risbgz. + * testsuite/gas/s390/zarch-zEC12.s: Add tests for risbgnz. + * testsuite/gas/s390/zarch-zEC12.d: Add regexp for risbgnz. + +2020-12-03 Andreas Krebbel <krebbel@linux.ibm.com> + + * testsuite/gas/s390/esa-g5.s: Test new extended mnemonics. + * testsuite/gas/s390/esa-g5.d: Likewise. + * testsuite/gas/s390/esa-z900.s: Likewise. + * testsuite/gas/s390/esa-z900.d: Likewise. + * testsuite/gas/s390/zarch-z900.s: Likewise. + * testsuite/gas/s390/zarch-z900.d: Likewise. + +2020-12-01 Nelson Chu <nelson.chu@sifive.com> + + * testsuite/gas/riscv/attribute-10.d: Updated. + * testsuite/gas/riscv/march-imply-g.d: New testcase for g. + * testsuite/gas/riscv/march-imply-unsupported.d: The zicsr and zifencei + are not supported in the ISA spec v2.2, so don't add and output them. + +2020-12-01 Nelson Chu <nelson.chu@sifive.com> + + * config/tc-riscv.c (riscv_subset_supports): Updated. + * testsuite/gas/riscv/march-imply-i2p0.d: New testcase. Need to + add the implicit zicsr and zifencei when i's version less than 2.1. + * testsuite/gas/riscv/march-imply-i2p1.d: New testcase. + * testsuite/gas/riscv/march-imply-d.d: Likewise. + * testsuite/gas/riscv/march-imply-f.d: Likewise. + * testsuite/gas/riscv/march-imply-q.d: Likewise. + * testsuite/gas/riscv/march-fail-rv32iq.l: Updated. + * testsuite/gas/riscv/march-fail-rv32id.d: Removed. + * testsuite/gas/riscv/march-fail-rv32id.l: Likewise. + * testsuite/gas/riscv/march-fail-rv64iq.d: Likewise. + * testsuite/gas/riscv/march-fail-rv64iq.l: Likewise. + +2020-12-01 Nelson Chu <nelson.chu@sifive.com> + + * config/tc-riscv.c (riscv_get_default_ext_version): + Change the version type from unsigned to int. + (riscv_set_arch): Use as_bad rather than as_fatal to + report more errors. + * testsuite/gas/riscv/attribute-02.d: Updated since x must be + set with versions. + * testsuite/gas/riscv/attribute-03.d: Likewise. + * testsuite/gas/riscv/march-ok-two-nse.d: Likewise. + * testsuite/gas/riscv/attribute-09.d: zicsr wasn't supported + in the spec 2.2, so choose the newer spec. + * testsuite/gas/riscv/march-fail-base-01.l: Updated since as_bad. + * testsuite/gas/riscv/march-fail-base-02.l: Likewise. + * testsuite/gas/riscv/march-fail-order-std.l: Likewise. + * testsuite/gas/riscv/march-fail-order-x.l: Likewise. + * testsuite/gas/riscv/march-fail-order-z.l: Likewise. + * testsuite/gas/riscv/march-fail-porder.l: Likewise. + * testsuite/gas/riscv/march-fail-rv32ef.l: Likewise. + * testsuite/gas/riscv/march-fail-rv32id.l: Likewise. + * testsuite/gas/riscv/march-fail-rv32iq.l: Likewise. + * testsuite/gas/riscv/march-fail-rv64iq.l: Likewise. + * testsuite/gas/riscv/march-fail-single-char.l: Likewise. + * testsuite/gas/riscv/march-fail-unknown-std.l: Likewise. + * testsuite/gas/riscv/march-fail-unknown.l: Likewise. + * testsuite/gas/riscv/march-fail-uppercase.l: Likewise. + * testsuite/gas/riscv/march-fail-version.l: Likewise. + * testsuite/gas/riscv/march-fail-isa-spec.d: Likewise. + * testsuite/gas/riscv/march-fail-isa-spec.l: Likewise. + +2020-12-01 Nelson Chu <nelson.chu@sifive.com> + + * testsuite/gas/riscv/march-fail-order-z.d: New testcase, check + orders of prefixed z extensions. + * testsuite/gas/riscv/march-fail-order-z.l: Likewise. + * testsuite/gas/riscv/march-fail-single-char-h.d: New testcase. + * testsuite/gas/riscv/march-fail-single-char.l: Updated. + * testsuite/gas/riscv/march-fail-unknown-h.d: New testcase. + * testsuite/gas/riscv/march-fail-unknown.l: Updated. + +2020-12-01 Nelson Chu <nelson.chu@sifive.com> + + * testsuite/gas/riscv/march-fail-uppercase-base.d: Updated. + * testsuite/gas/riscv/march-fail-uppercase.l: Updated. + * testsuite/gas/riscv/march-fail-uppercase-x.d: New testcase. + +2020-12-01 Nelson Chu <nelson.chu@sifive.com> + + (These are new testcases that cover more cases) + * testsuite/gas/riscv/march-fail-base-01.d: The first extension must + be e, i or g. + * testsuite/gas/riscv/march-fail-base-01.l: Likewise. + * testsuite/gas/riscv/march-fail-base-02.d: rv64e is an invalid base ISA. + * testsuite/gas/riscv/march-fail-base-02.l: Likewise. + * testsuite/gas/riscv/march-fail-order-std.d: Check orders of standard + extensions. + * testsuite/gas/riscv/march-fail-order-std.l: Likewise. + * testsuite/gas/riscv/march-fail-order-x.d: Check orders of prefixed + x extensions. + * testsuite/gas/riscv/march-fail-order-x.l: Likewise. + * testsuite/gas/riscv/march-fail-porder-x-std.d: Check orders when + standard and prefixed extensions are set at the same time. + * testsuite/gas/riscv/march-fail-porder-x-z.d: Likewise. + * testsuite/gas/riscv/march-fail-porder-z-std.d: Likewise. + * testsuite/gas/riscv/march-fail-porder.l: Likewise. + * testsuite/gas/riscv/march-fail-single-char-s.d: Only standard + extensions can use single char. + * testsuite/gas/riscv/march-fail-single-char-x.d: Likewise. + * testsuite/gas/riscv/march-fail-single-char-z.d: Likewise. + * testsuite/gas/riscv/march-fail-single-char.l: Likewise. + * testsuite/gas/riscv/march-fail-unknown-s.d: All extensions + should be known, except the non-standard x extensions. + * testsuite/gas/riscv/march-fail-unknown-std.d: Likewise. + * testsuite/gas/riscv/march-fail-unknown-std.l: Likewise. + * testsuite/gas/riscv/march-fail-unknown-z.d: Likewise. + * testsuite/gas/riscv/march-fail-unknown.l: Likewise. + * testsuite/gas/riscv/march-fail-uppercase-base.d: Do not + allow any uppercase in the arch string. + * testsuite/gas/riscv/march-fail-uppercase-std.d: Likewise. + * testsuite/gas/riscv/march-fail-uppercase-z.d: Likewise. + * testsuite/gas/riscv/march-fail-uppercase.l: Likewise. + * testsuite/gas/riscv/march-fail-version-x.d: Failed to set versions. + * testsuite/gas/riscv/march-fail-version-z.d: Likewise. + * testsuite/gas/riscv/march-fail-version.l: Likewise. + * testsuite/gas/riscv/march-fail-rv32ef.l: Updated. + * testsuite/gas/riscv/march-fail-rv32id.d: Need f-ext. + * testsuite/gas/riscv/march-fail-rv32iq.d: Should be rv64. + * testsuite/gas/riscv/march-fail-rv32iq.l: Likewise. + * testsuite/gas/riscv/march-fail-rv64iq.d: Need d-ext and f-ext. + * testsuite/gas/riscv/march-fail-rv64iq.l: Likewise. + + (The following testcases are removed and covered by new testcases) + * testsuite/gas/riscv/march-fail-rv32i.d: march-fail-uppercase-base. + * testsuite/gas/riscv/march-fail-rv32i.l: Likewise. + * testsuite/gas/riscv/march-fail-rv32iam.d: march-fail-order-std. + * testsuite/gas/riscv/march-fail-rv32iam.l: Likewise. + * testsuite/gas/riscv/march-fail-rv32ic.d: march-fail-uppercase-std. + * testsuite/gas/riscv/march-fail-rv32ic.l: Likewise. + * testsuite/gas/riscv/march-fail-rv32icx2p.d: march-fail-version-x. + * testsuite/gas/riscv/march-fail-rv32icx2p.l: Likewise. + * testsuite/gas/riscv/march-fail-rv32imc.d: march-fail-order-std. + * testsuite/gas/riscv/march-fail-rv32imc.l: Likewise. + * testsuite/gas/riscv/march-fail-rv64I.d: march-fail-uppercase-std. + * testsuite/gas/riscv/march-fail-rv64I.l: Likewise. + * testsuite/gas/riscv/march-fail-rv64e.d: march-fail-base-02. + * testsuite/gas/riscv/march-fail-rv64e.l: Likewise. + * testsuite/gas/riscv/march-fail-s-with-version.d: march-fail-unknown-s. + * testsuite/gas/riscv/march-fail-s-with-version.l: Likewise. + * testsuite/gas/riscv/march-fail-s.d: march-fail-unknown-s. + * testsuite/gas/riscv/march-fail-s.l: Likewise. + * testsuite/gas/riscv/march-fail-sx.d: march-fail-unknown-s. + * testsuite/gas/riscv/march-fail-sx.l: Likewise. + +2002-11-29 Borislav Petkov <bp@suse.de> + + * testsuite/gas/i386/branch.d: Add new branch insns test. + * testsuite/gas/i386/branch.s: Likewise. + * testsuite/gas/i386/i386.exp: Insert the new branch test. + * testsuite/gas/i386/x86-64-branch.d: Test for branch hints insns. + * testsuite/gas/i386/x86-64-branch.s: Likewise. + * testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise. + +2020-11-27 Jozef Lawrynowicz <jozef.l@mittosystems.com> + + * testsuite/gas/elf/elf.exp: Run new tests. + * testsuite/gas/elf/section25.d: New test. + * testsuite/gas/elf/section25.s: New test. + * testsuite/gas/elf/section26.d: New test. + * testsuite/gas/elf/section26.s: New test. + +2020-11-25 Alan Modra <amodra@gmail.com> + + * output-file.c (output_file_close): Remove "can't close" from + error message. + * testsuite/gas/mips/reginfo-2.l: Update expected output. + +2020-11-04 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * config/tc-aarch64.c (aarch64_cpus): Add Cortex-A78C. + * doc/c-aarch64.texi: Document -mcpu=cortex-a78c. + * doc/NEWS: Update news. + +2020-11-19 Jozef Lawrynowicz <jozef.l@mittosystems.com> + + * testsuite/gas/elf/section22.d: Allow FreeBSD OSABI in readelf + output. + * testsuite/gas/elf/section23a.d: Likewise. + * testsuite/gas/elf/section24a.d: Likewise. + +2020-11-18 Alan Modra <amodra@gmail.com> + + * doc/as.texi (.nop): Document optional size arg. + * dwarf2dbg.c (dwarf2_gen_line_info_1): Only check SEC_ALLOC + when ELF. Warn whenever dwarf line number information is ignored. + * frags.c (frag_offset_ignore_align_p): New function. + * frags.h (frag_offset_ignore_align_p): Declare. + * read.c (s_nop): Extend to support optional size arg. + * testsuite/gas/elf/dwarf2-20.d: Expect warnings, and exact range. + * testsuite/gas/elf/dwarf2-20.s: Emit 16 bytes worth of nops. + * testsuite/gas/m68hc11/indexed12.d: Expect warnings. + +2020-11-18 Jozef Lawrynowicz <jozef.l@mittosystems.com> + H.J. Lu <hongjiu.lu@intel.com> + + * NEWS: Announce SHF_GNU_RETAIN support. + * config/obj-elf.c (obj_elf_change_section): Merge SHF_GNU_RETAIN bit + between section declarations. + (obj_elf_parse_section_letters): Handle 'R' flag. + Handle numeric flag values within the SHF_MASKOS range. + (obj_elf_section): Validate SHF_GNU_RETAIN usage. + * doc/as.texi: Document 'R' flag to .section directive. + * testsuite/gas/elf/elf.exp: Run new tests. + * testsuite/gas/elf/section10.d: Unset SHF_GNU_RETAIN bit. + * testsuite/gas/elf/section10.s: Likewise. + * testsuite/gas/elf/section22.d: New test. + * testsuite/gas/elf/section22.s: New test. + * testsuite/gas/elf/section23.s: New test. + * testsuite/gas/elf/section23a.d: New test. + * testsuite/gas/elf/section23b.d: New test. + * testsuite/gas/elf/section23b.err: New test. + * testsuite/gas/elf/section24.s: New test. + * testsuite/gas/elf/section24a.d: New test. + * testsuite/gas/elf/section24b.d: New test. + +2020-11-13 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * NEWS: Update news. + * config/tc-aarch64.c: Add option +pauth to -march. + * doc/c-aarch64.texi: Update docs. + * testsuite/gas/aarch64/pac-feat.d: New test. + * testsuite/gas/aarch64/pac-feat.s: New test. + +2020-11-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * NEWS: Update news. + * config/tc-aarch64.c: New feature flag +flagm. + * doc/c-aarch64.texi: Update docs. + * testsuite/gas/aarch64/flagm.d: New test. + * testsuite/gas/aarch64/flagm.s: New test. + +2020-11-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * config/tc-arm.c (arm_cpus): Add Cortex-A78C. + * doc/c-arm.texi: Document -mcpu=cortex-a78c. + * testsuite/gas/arm/cpu-cortex-a78c.d: New test. + +2020-11-14 Borislav Petkov <bp@suse.de> + + * testsuite/gas/i386/x86-64-segovr.d: Adjust regexes. + * testsuite/gas/i386/x86-64-nops.d: Likewise. + * testsuite/gas/i386/x86-64-nops-1.d: Likewise. + * testsuite/gas/i386/x86-64-nops-1-g64.d: Likewise. + * testsuite/gas/i386/x86-64-nops-1-core2.d: Likewise. + * testsuite/gas/i386/x86-64-nops-1-k8.d: Likewise. + * testsuite/gas/i386/x86-64-nops-2.d: Likewise. + * testsuite/gas/i386/x86-64-nops-3.d: Likewise. + * testsuite/gas/i386/x86-64-nops-4.d: Likewise. + * testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise. + * testsuite/gas/i386/x86-64-nops-4-k8.d: Likewise. + * testsuite/gas/i386/x86-64-nops-5.d: Likewise. + * testsuite/gas/i386/x86-64-nops-5-k8.d: Likewise. + * testsuite/gas/i386/x86-64-nops-7.d: Likewise. + * testsuite/gas/i386/x86-64-nop-1.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-2c.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-6.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-7.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-8.d: Likewise. + * testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise. + * testsuite/gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise. + * testsuite/gas/i386/ilp32/x86-64-nops-1.d: Likewise. + * testsuite/gas/i386/ilp32/x86-64-nops-2.d: Likewise. + * testsuite/gas/i386/ilp32/x86-64-nops-3.d: Likewise. + * testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise. + * testsuite/gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise. + * testsuite/gas/i386/ilp32/x86-64-nops-4.d: Likewise. + * testsuite/gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise. + * testsuite/gas/i386/ilp32/x86-64-nops-5.d: Likewise. + * testsuite/gas/i386/ilp32/x86-64-nops.d:: Likewise. + +2020-11-12 Jozef Lawrynowicz <jozef.l@mittosystems.com> + + * config/tc-msp430.c (OPTION_MOVE_DATA): Define. + (md_parse_option): Ignore OPTION_MOVE_DATA. + (md_longopts): Handle -md option. + * testsuite/gas/msp430/msp430.exp: Run new test. + * testsuite/gas/msp430/empty.s: New test. + * testsuite/gas/msp430/ignore-md.d: New test. + +2020-11-12 Nick Clifton <nickc@redhat.com> + + PR 26850 + * dwarf2dbg.c (dwarf2_gen_line_info_1): Do not record lines in + sections that are not executable or not loadable. + (out_debug_line): Move warning message into dwarf2_gen_line_info_1. + * testsuite/gas/elf/dwarf2-20.s: New test. + * testsuite/gas/elf/dwarf2-20.d: New test driver. + * testsuite/gas/elf/elf.exp: Run the new test. + * testsuite/gas/elf/warn-2.s: Use the .nop directive. + +2020-11-11 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * testsuite/gas/aarch64/ls64.s: Update test. + +2020-11-09 Denys Zagorui <dzagorui@cisco.com> + + * config/obj-elf (obj_elf_init_stab_section): Improve + reproducibility for stabs debugging data format + +2020-11-09 Spencer E. Olson <olsonse@umich.edu> + + * testsuite/gas/pru/misc.s: Add tests for lmbd (left-most bit + detect). + * testsuite/gas/pru/misc.d: Update expected disassembly. + +2020-11-09 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * config/tc-aarch64.c: Fix comment. + * testsuite/gas/aarch64/ls64.d: New test. + * testsuite/gas/aarch64/ls64.s: Test for ACCDATA_EL1 register. + +2020-11-09 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * config/tc-aarch64.c (process_omitted_operand): Add AARCH64_OPND_Rt_LS64. + (parse_operands): Parse Rt range for AARCH64_OPND_Rt_LS64. + * testsuite/gas/aarch64/ls64-invalid.l: Update test. + * testsuite/gas/aarch64/ls64-invalid.s: Update test. + * testsuite/gas/aarch64/ls64.s: Update test. + +2020-11-09 Andreas Schwab <schwab@linux-m68k.org> + + * Makefile.am (development.exp): Fix regexp. + * Makefile.in: Regenerate. + +2020-11-09 Nelson Chu <nelson.chu@sifive.com> + + * config/tc-riscv.c (explicit_mabi): New boolean to indicate if + the -mabi= option is explictly set. + (md_parse_option): Set explicit_mabi to TRUE if -mabi is set. + (riscv_set_abi_by_arch): New function. If the -mabi option isn't + set, then we set the abi according to the architecture string. + Otherwise, check if there are conflicts between architecture + and abi setting. + (riscv_after_parse_args): Move the abi setting to md_assemble nad + riscv_elf_final_processing. + (md_assemble): Call the riscv_set_abi_by_arch when we set the + start_assemble to TRUE. + (riscv_elf_final_processing): Likewise, in case the file without + any instruction. + * testsuite/gas/riscv/mabi-attr-01.s: New testcase. + * testsuite/gas/riscv/mabi-attr-02.s: Likewise. + * testsuite/gas/riscv/mabi-attr-03.s: Likewise. + * testsuite/gas/riscv/mabi-fail-01.d: Likewise. + * testsuite/gas/riscv/mabi-fail-01.l: Likewise. + * testsuite/gas/riscv/mabi-fail-02.d: Likewise. + * testsuite/gas/riscv/mabi-fail-02.l: Likewise. + * testsuite/gas/riscv/mabi-noabi-attr-01a.d: Likewise. + * testsuite/gas/riscv/mabi-noabi-attr-01b.d: Likewise. + * testsuite/gas/riscv/mabi-noabi-attr-02a.d: Likewise. + * testsuite/gas/riscv/mabi-noabi-attr-02b.d: Likewise. + * testsuite/gas/riscv/mabi-noabi-attr-03a.d: Likewise. + * testsuite/gas/riscv/mabi-noabi-attr-03b.d: Likewise. + * testsuite/gas/riscv/mabi-noabi-march-01.d: Likewise. + * testsuite/gas/riscv/mabi-noabi-march-02.d: Likewise. + * testsuite/gas/riscv/mabi-noabi-march-03.d: Likewise. + +2020-11-04 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * testsuite/gas/aarch64/armv8-ras-1_1-invalid.d: New test. + * testsuite/gas/aarch64/armv8-ras-1_1-invalid.l: New test. + * testsuite/gas/aarch64/armv8-ras-1_1-invalid.s: New test. + * testsuite/gas/aarch64/armv8-ras-1_1.d: New test. + * testsuite/gas/aarch64/armv8-ras-1_1.s: New test. + * testsuite/gas/aarch64/illegal-ras-1.d: Remove. + * testsuite/gas/aarch64/illegal-ras-1.l: Remove. + * testsuite/gas/aarch64/illegal-ras-1.s: Remove. + * testsuite/gas/aarch64/illegal-sysreg-2.d: Remove. + * testsuite/gas/aarch64/illegal-sysreg-2.l: Remove. + +2020-11-03 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * NEWS: Update docs. + * config/tc-aarch64.c: Add +ls64 feature to -march flags set. + * testsuite/gas/aarch64/ls64-invalid.d: New test. + * testsuite/gas/aarch64/ls64-invalid.l: New test. + * testsuite/gas/aarch64/ls64-invalid.s: New test. + * testsuite/gas/aarch64/ls64.s: New test. + +2020-11-03 Christian Eggers <ceggers@gmx.de> + + * config/obj-elf (elf_frob_symbol): Fix symbol value calculation + for versioned symbol aliases. + +2020-10-30 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26703 + * config/tc-i386.c (output_insn): Update for + GNU_PROPERTY_X86_ISA_1_BASELINE. + * testsuite/gas/i386/property-1.d: Updated. + * testsuite/gas/i386/property-2.d: Likewise. + * testsuite/gas/i386/property-3.d: Likewise. + * testsuite/gas/i386/property-4.d: Likewise. + * testsuite/gas/i386/property-5.d: Likewise. + * testsuite/gas/i386/property-6.d: Likewise. + * testsuite/gas/i386/property-11.d: Likewise. + * testsuite/gas/i386/property-12.d: Likewise. + * testsuite/gas/i386/x86-64-property-1.d: Likewise. + * testsuite/gas/i386/x86-64-property-2.d: Likewise. + * testsuite/gas/i386/x86-64-property-3.d: Likewise. + * testsuite/gas/i386/x86-64-property-4.d: Likewise. + * testsuite/gas/i386/x86-64-property-5.d: Likewise. + * testsuite/gas/i386/x86-64-property-6.d: Likewise. + * testsuite/gas/i386/x86-64-property-11.d: Likewise. + * testsuite/gas/i386/x86-64-property-12.d: Likewise. + +2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * NEWS: Update docs. + * testsuite/gas/aarch64/system-5.d: Update test with WFIT insn. + * testsuite/gas/aarch64/system-5.s: Update test with WFIT insn. + +2020-10-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * config/tc-aarch64.c (parse_operands): Check for C0-C15 value of DSB + immediate string operand. + * testsuite/gas/aarch64/system-4.d: Update test. + * testsuite/gas/aarch64/system-4.s: Update test. + +2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * NEWS: Update docs. + * config/tc-aarch64.c (parse_csr_operand): New operand parser. + (parse_operands): Call to CSR operand parser. + * testsuite/gas/aarch64/csre_csr-invalid.d: New test. + * testsuite/gas/aarch64/csre_csr-invalid.l: New test. + * testsuite/gas/aarch64/csre_csr-invalid.s: New test. + * testsuite/gas/aarch64/csre_csr.d: New test. + * testsuite/gas/aarch64/csre_csr.s: New test. + +2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * NEWS: Update docs. + * testsuite/gas/aarch64/system-5.d: New test. + * testsuite/gas/aarch64/system-5.s: New test. + +2020-10-26 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26778 + * * dwarf2dbg.c (num_of_auto_assigned): New. + (allocate_filenum): Increment num_of_auto_assigned. + (dwarf2_directive_filename): Clear the slots auto-assigned + before the first .file <NUMBER> directive was seen. + * testsuite/gas/i386/dwarf4-line-1.d: New file. + * testsuite/gas/i386/dwarf4-line-1.s: Likewise. + * testsuite/gas/i386/i386.exp: Run dwarf4-line-1. + +2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (dump_literals): Fix the literal dump + of big vector constant. + +2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com> + + * testsuite/gas/csky/enhance_dsp.s : Change plsl.u16 to plsl.16. + * testsuite/gas/csky/enhance_dsp.d : Change plsl.u16 to plsl.16. + +2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (md_begin): Add version flag in eflag. + +2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (get_operand_value): Add handler for + OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX. + * testsuite/gas/csky/csky_vdsp.d : Fix the disassembling for + vector register. + +2020-10-26 Lili Cui <lili.cui@intel.com> + + * testsuite/gas/i386/avx-vnni.d: Change psuedo prefix from + {vex3} to {vex} + * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise. + +2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * NEWS: Docs update. + * config/tc-aarch64.c (parse_operands): Add + AARCH64_OPND_BARRIER_DSB_NXS handler. + (md_begin): Add content of aarch64_barrier_dsb_nxs_options to + aarch64_barrier_opt_hsh hash. + * testsuite/gas/aarch64/system-4-invalid.d: New test. + * testsuite/gas/aarch64/system-4-invalid.l: New test. + * testsuite/gas/aarch64/system-4-invalid.s: New test. + * testsuite/gas/aarch64/system-4.d: New test. + * testsuite/gas/aarch64/system-4.s: New test. + +2020-10-21 Srinath Parvathaneni <srinath.parvathaneni@arm.com> + + PR target/26763 + * config/tc-arm.c (parse_address_main): Add new MVE addressing mode + check. + * testsuite/gas/arm/mve-vldr-vstr-bad.d: New test. + * testsuite/gas/arm/mve-vldr-vstr-bad.l: Likewise. + * testsuite/gas/arm/mve-vldr-vstr-bad.s: Likewise. + +2020-10-20 Dr. David Alan Gilbert <dgilbert@redhat.com> + + * config/tc-arc.c (emit_insn0): Fix printf format. + +2020-10-20 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> + + * config/tc-i386.c (cpu_arch): Add CPU_ZNVER3_FLAGS flags. + (i386_align_code): Add PROCESSOR_ZNVER cases. + * doc/c-i386.texi: Add znver3, snp, invlpgb and tlbsync. + * gas/i386/i386.exp: Add new znver3 test cases. + * gas/i386/arch-14-znver3.d: New. + * gas/i386/arch-14.d: New. + * gas/i386/arch-14.s: New. + * gas/i386/invlpgb.d: New. + * gas/i386/invlpgb64.d: New. + * gas/i386/invlpgb.s: New. + * gas/i386/snp.d: New. + * gas/i386/snp64.d: New. + * gas/i386/snp.s: New. + * gas/i386/tlbsync.d: New. + * gas/i386/tlbsync.s: New. + * gas/i386/x86-64-arch-4-znver3.d: New. + * gas/i386/x86-64-arch-4.d: New. + * gas/i386/x86-64-arch-4.s: New. + +2020-10-17 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/25878 + PR gas/26740 + * testsuite/gas/i386/dwarf5-line-4.d: New file. + * testsuite/gas/i386/dwarf5-line-4.s: Likewise. + * testsuite/gas/i386/i386.exp: Run dwarf5-line-4. + +2020-10-17 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/25878 + PR gas/26740 + * testsuite/gas/i386/dwarf5-line-3.s: Replace dwarf5-line-2.S + with dwarf5-line-3.S. + * testsuite/gas/i386/dwarf5-line-3.d: Updated. + +2020-10-17 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/25878 + PR gas/26740 + * dwarf2dbg.c (allocate_filename_to_slot): Don't reuse the slot 1 + here. + (dwarf2_where): Restore as_where. + (dwarf2_directive_filename): Clear the slot 1 if it was assigned + to the input file. + * testsuite/gas/i386/dwarf5-line-2.d: New file. + * testsuite/gas/i386/dwarf5-line-2.s: Likewise. + * testsuite/gas/i386/dwarf5-line-3.d: Likewise. + * testsuite/gas/i386/dwarf5-line-3.s: Likewise. + * testsuite/gas/i386/i386.exp: Run dwarf5-line-2 and + dwarf5-line-3. + +gas/ChangeLog: + +2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * NEWS: Docs update. + * config/tc-aarch64.c (armv8.7-a): New arch. + * doc/c-aarch64.texi (-march=armv8.7-a): Update docs. + +2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * testsuite/gas/aarch64/sysreg-6.d: New test. + * testsuite/gas/aarch64/sysreg-6.s: New test. + +2020-10-16 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/25878 + PR gas/26740 + * dwarf2dbg.c (file_entry): Remove auto_assigned. + (assign_file_to_slot): Remove the auto_assign argument. + (allocate_filenum): Updated. + (allocate_filename_to_slot): Reuse the input file entry in the + file table. + (dwarf2_where): Replace as_where with as_where_physical. + * testsuite/gas/i386/dwarf5-line-1.d: New file. + * testsuite/gas/i386/dwarf5-line-1.s: Likewise. + * testsuite/gas/i386/i386.exp: Run dwarf5-line-1. + +2020-10-16 Lili Cui <lili.cui@intel.com> + + * config/tc-i386.c (cpu_flags_match): Move Pseudo Prefix check + to ... + (match_template): Here. + * testsuite/gas/i386/avx-vnni-inval.l: New file. + * testsuite/gas/i386/avx-vnni-inval.s: Likewise. + * testsuite/gas/i386/avx-vnni.d: Delete invalid {vex2} test. + * testsuite/gas/i386/avx-vnni.s: Likewise. + * testsuite/gas/i386/i386.exp: Add AVX VNNI invalid tests. + * testsuite/gas/i386/x86-64-avx-vnni-inval.l: New file. + * testsuite/gas/i386/x86-64-avx-vnni-inval.s: Likewise. + * testsuite/gas/i386/x86-64-avx-vnni.d: Delete invalid {vex2} test. + * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise. + +2020-10-14 H.J. Lu <hongjiu.lu@intel.com> + Lili Cui <lili.cui@intel.com> + + * NEWS: Add Intel AVX VNNI. + * config/tc-i386.c (cpu_arch): Add .avx_vnni and noavx_vnni. + (cpu_flags_match): Support CpuVEX_PREFIX. + * doc/c-i386.texi: Document .avx_vnni, noavx_vnni and how to + encode Intel VNNI instructions with VEX prefix. + * testsuite/gas/i386/avx-vnni.d: New file. + * testsuite/gas/i386/avx-vnni.s: Likewise. + * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise. + * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise. + * testsuite/gas/i386/i386.exp: Run AVX VNNI tests. + +2020-10-14 Lili Cui <lili.cui@intel.com> + + * NEWS: Add Intel HRESET. + * config/tc-i386.c (cpu_arch): Add .hreset. + (cpu_noarch): Likewise. + * doc/c-i386.texi: Document .hreset, nohreset. + * testsuite/gas/i386/i386.exp: Run HRESET tests. + * testsuite/gas/i386/hreset.d: New file. + * testsuite/gas/i386/x86-64-hreset.d: Likewise. + * testsuite/gas/i386/hreset.s: Likewise. + +2020-10-14 Lili Cui <lili.cui@intel.com> + + * NEWS: Add Intel UINTR. + * config/tc-i386.c (cpu_arch): Add .uintr. + (cpu_noarch): Likewise. + * doc/c-i386.texi: Document .uintr and nouintr. + * testsuite/gas/i386/i386.exp: Run UINTR tests. + * testsuite/gas/i386/x86-64-uintr.d: Likewise. + * testsuite/gas/i386/x86-64-uintr.s: Likewise. + +2020-10-14 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (load_insn_p): Check opcodeprefix == 0 for + base_opcode == 0xfc7. + (match_template): Likewise. + (process_suffix): Check opcodeprefix == PREFIX_0XF2 for CRC32. + (check_byte_reg): Likewise. + (output_insn): Don't add the 0xf3 prefix twice for PadLock + instructions. Don't add prefix from non-VEX/EVEX base_opcode. + +2020-10-13 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (build_vex_prefix): Replace vexopcode with + opcodeprefix. + (build_evex_prefix): Likewise. + (is_any_vex_encoding): Don't check vexopcode. + (output_insn): Handle opcodeprefix. + +2020-10-09 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26703 + * config/tc-i386.c (xstate): Add xstate_mask. + (md_assemble): Check i.types[j], instead of i.tm.operand_types[j], + for xstate. Set xstate_mask, instead of xstate_zmm, for RegMask. + (output_insn): Update for GNU_PROPERTY_X86_ISA_1_V[234]. Update + xstate for mask register and VSIB. + * testsuite/gas/i386/i386.exp: Run more GNU_PROPERTY tests. + * testsuite/gas/i386/property-1.s: Updated to the current + GNU_PROPERTY_X86_ISA_1_USED value. + * testsuite/gas/i386/property-2.s: Only keep cmove. + * testsuite/gas/i386/property-3.s: Changed to addsubpd. + * testsuite/gas/i386/property-1.d: Updated. + * testsuite/gas/i386/property-2.d: Likewise. + * testsuite/gas/i386/property-3.d: Likewise. + * testsuite/gas/i386/property-4.d: Likewise. + * testsuite/gas/i386/property-5.d: Likewise. + * testsuite/gas/i386/property-6.d: Likewise. + * testsuite/gas/i386/x86-64-property-1.d: Likewise. + * testsuite/gas/i386/x86-64-property-2.d: Likewise. + * testsuite/gas/i386/x86-64-property-3.d: Likewise. + * testsuite/gas/i386/x86-64-property-4.d: Likewise. + * testsuite/gas/i386/x86-64-property-5.d: Likewise. + * testsuite/gas/i386/x86-64-property-6.d: Likewise. + * testsuite/gas/i386/x86-64-property-7.d: Likewise. + * testsuite/gas/i386/x86-64-property-8.d: Likewise. + * testsuite/gas/i386/x86-64-property-9.d: Likewise. + * testsuite/gas/i386/property-11.d: New file. + * testsuite/gas/i386/property-11.s: Likewise. + * testsuite/gas/i386/property-12.d: Likewise. + * testsuite/gas/i386/property-12.s: Likewise. + * testsuite/gas/i386/property-13.d: Likewise. + * testsuite/gas/i386/property-13.s: Likewise. + * testsuite/gas/i386/x86-64-property-11.d: Likewise. + * testsuite/gas/i386/x86-64-property-12.d: Likewise. + * testsuite/gas/i386/x86-64-property-13.d: Likewise. + * testsuite/gas/i386/x86-64-property-14.d: Likewise. + * testsuite/gas/i386/x86-64-property-14.s: Likewise. + +2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * NEWS: Docs update. + * testsuite/gas/aarch64/brbe-invalid.d: New test. + * testsuite/gas/aarch64/brbe-invalid.l: New test. + * testsuite/gas/aarch64/brbe-invalid.s: New test. + * testsuite/gas/aarch64/brbe.d: New test. + * testsuite/gas/aarch64/brbe.s: New test. + +2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * NEWS: Docs update. + * testsuite/gas/aarch64/csre-invalid.d: New test. + * testsuite/gas/aarch64/csre-invalid.l: New test. + * testsuite/gas/aarch64/csre-invalid.s: New test. + * testsuite/gas/aarch64/csre.d: New test. + * testsuite/gas/aarch64/csre.s: New test. + +2020-10-06 Alex Coplan <alex.coplan@arm.com> + + PR 26699 + * config/tc-aarch64.c (asm_barrier_opt): Delete. + (parse_barrier): Fix bogus type punning. + * testsuite/gas/aarch64/system.d: Update disassembly. + * testsuite/gas/aarch64/system.s: Add isb sy test. + +2020-10-06 Sergey Belyashav <sergey.belyashov@gmail.com> + + PR 26692 + * config/tc-z80.c (md_begin): Ensure that xpressions are empty + before using them. + (unify_indexed): Likewise. + (z80_start_line_hook): Improve hash sign handling when SDCC + compatibility mode enabled. + (md_parse_exp_not_indexed): Improve indirect addressing + detection. + (md_pseudo_table): Accept hd64 as an alias of z810. + +2020-10-06 Alan Modra <amodra@gmail.com> + + * testsuite/gas/elf/sh-link-zero.s: Don't start directives in + first column. Don't use numeric labels. + +2020-10-05 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * config/tc-arm.c: Update Cortex-X1 feature flags. + +2020-10-05 Kamil Rytarowski <n54@gmx.com> + + * configure.tgt (aarch64*-*-netbsd*): Add target. + +2020-10-05 Samanta Navarro <ferivoz@riseup.net> + + * doc/as.texi: Fix spelling mistakes. + * doc/c-wasm32.texi: Likewise. + +2020-10-05 T.K. Chia <u1049321969@caramail.com> + + PR gas/26694 + * NEWS: Updated for i386 lcall and ljmp change. + * config/tc-i386.c (output_interseg_jump): Allow non-absolute + segment operand for immediate lcall and ljmp. + * testsuite/gas/i386/jump.d, + * testsuite/gas/i386/jump.s, + * testsuite/gas/i386/jump16.d, + * testsuite/gas/i386/jump16.e, + * testsuite/gas/i386/jump16.s: Add tests for non-absolute + segment operand for immediate ljmp. + +2020-10-05 H.J. Lu <hongjiu.lu@intel.com> + + PR binutils/26704 + * testsuite/gas/i386/noreg64-data16.d: Expect sysretl instead of + sysret. + * testsuite/gas/i386/noreg64.d: Likewise. + * testsuite/gas/i386/x86-64-intel64.d: Likewise. + * testsuite/gas/i386/x86-64-opcode.d: Likewise. + +2020-10-05 H.J. Lu <hongjiu.lu@intel.com> + + PR binutils/26705 + * testsuite/gas/i386/x86-64-suffix.s: Add "mov %rsp,%rbp" before + sysretq. + * testsuite/gas/i386/x86-64-suffix-intel.d: Updated. + * testsuite/gas/i386/x86-64-suffix.d: Likewise. + +2020-10-05 Nick Clifton <nickc@redhat.com> + + PR 26253 + * config/obj-elf.c (obj_elf_section): Accept a numeric value for + the "o" section flag. Interpret it as a section index. Allow an + index of zero. + * doc/as.texi: Document the new behaviour. + * NEWS: Mention the new feature. Tidy entries. + * testsuite/gas/elf/sh-link-zero.s: New test. + * testsuite/gas/elf/sh-link-zero.d: New test driver. + * testsuite/gas/elf/elf.exp: Run the new test. + * testsuite/gas/elf/section21.l: Updated expected assembler + output. + +2020-10-05 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * config/tc-aarch64.c: Update Cortex-X1 feature flags. + +2020-10-03 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26685 + * config/tc-i386.c (process_suffix): Also check the register + operand for the address size prefix if the memory operand has + no real registers. + * testsuite/gas/i386/enqcmd-16bit.d: New file. + * testsuite/gas/i386/enqcmd-16bit.s: Likewise. + * testsuite/gas/i386/movdir-16bit.d: Likewise. + * testsuite/gas/i386/movdir-16bit.s: Likewise. + * testsuite/gas/i386/enqcmd.s: Add tests with symbol and DISP. + * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. + * testsuite/gas/i386/x86-64-movdir.s: Likewise. + * testsuite/gas/i386/movdir.s: Add tests with symbol and DISP. + Remove the .code16 test. + * testsuite/gas/i386/i386.exp: Run movdir-16bit and enqcmd-16bit. + * testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated. + * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. + * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. + * testsuite/gas/i386/x86-64-movdir.d: Likewise. + * testsuite/gas/i386/enqcmd-intel.d: Likewise. + * testsuite/gas/i386/enqcmd.d: Likewise. + * testsuite/gas/i386/movdir-intel.d: Likewise. + * testsuite/gas/i386/movdir.d: Likewise. + * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. + * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. + * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. + * testsuite/gas/i386/x86-64-movdir.d: Likewise. + +2020-10-02 Nick Clifton <nickc@redhat.com> + + * testsuite/gas/arm/mve-vcvtne-it.d: Allow for padding inserted by + PE based targets. + +2020-10-01 Nick Clifton <nickc@redhat.com> + + * config/obj-elf (elf_pseudo_table): Add attach_to_group. + (obj_elf_attach_to_group): New function. + * doc/as.texi: Document the new directive. + * NEWS: Mention the new feature. + * testsuite/gas/elf/attach-1.s: New test. + * testsuite/gas/elf/attach-1.d: New test driver. + * testsuite/gas/elf/attach-2.s: New test. + * testsuite/gas/elf/attach-2.d: New test driver. + * testsuite/gas/elf/attach-err.s: New test. + * testsuite/gas/elf/attach-err.d: New test driver. + * testsuite/gas/elf/attach-err.err: New test error output. + * testsuite/gas/elf/elf.exp: Run the new tests. + +2020-09-16 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26685 + * config/tc-i386.c (process_suffix): Check the register operand + for the address size prefix if the memory operand is symbol(%rip). + * testsuite/gas/i386/x86-64-enqcmd.s: Add tests with RIP-relative + addressing. + * testsuite/gas/i386/x86-64-movdir.s: Likewise. + * testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated. + * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. + * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. + * testsuite/gas/i386/x86-64-movdir.d: Likewise. + +2020-09-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * config/tc-aarch64.c: Add Cortex-A78 and Cortex-A78AE cores. + * doc/c-aarch64.texi: Update docs. + * NEWS: Update news. + +2020-09-30 Alex Coplan <alex.coplan@arm.com> + + * NEWS: Mention recent Arm processor support. + +2020-09-30 Alex Coplan <alex.coplan@arm.com> + + * config/tc-aarch64.c (aarch64_cpus): Add neoverse-n2. + * doc/c-aarch64.texi: Document support for Neoverse N2. + +2020-09-30 Alan Modra <amodra@gmail.com> + + * config/obj-elf.c (obj_elf_change_section): Rename variable to + avoid shadowing warning. + * symbols.c (symbol_entry_find): Init all symbol_flags fields. + +2020-09-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * config/tc-arm.c: Add cortex-a78 and cortex-a78ae cores. + * doc/c-arm.texi: Update docs. + * NEWS: Update news. + * testsuite/gas/arm/cpu-cortex-a78.d: New test. + * testsuite/gas/arm/cpu-cortex-a78ae.d: New test. + +2020-09-29 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * NEWS: TRBE, ETE, ETMv4 and Cortex-X1 news updates. + +2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * config/tc-arm.c: (arm_cpus): Add Cortex-X1. + * doc/c-arm.texi: Document -mcpu=cortex-x1. + * testsuite/gas/arm/cpu-cortex-x1.d: New test. + +2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * testsuite/gas/aarch64/etm-ro-invalid.d: New test. + * testsuite/gas/aarch64/etm-ro-invalid.l: New test. + * testsuite/gas/aarch64/etm-ro-invalid.s: New test. + * testsuite/gas/aarch64/etm-ro.s: New test. + * testsuite/gas/aarch64/etm-wo-invalid.d: New test. + * testsuite/gas/aarch64/etm-wo-invalid.l: New test. + * testsuite/gas/aarch64/etm-wo-invalid.s: New test. + * testsuite/gas/aarch64/etm-wo.s: New test. + * testsuite/gas/aarch64/etm.s: New test. + * testsuite/gas/aarch64/sysreg.d: system register s2_1_c0_c3_0 + disassembled now to trcstatr. + +2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * config/tc-aarch64.c: (aarch64_cpus): Add Cortex-X1. + * doc/c-aarch64.texi: Document -mcpu=cortex-x1. + +2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * testsuite/gas/aarch64/ete.d: New test. + * testsuite/gas/aarch64/ete.s: New test. + +2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * testsuite/gas/aarch64/trbe-invalid.d: New test. + * testsuite/gas/aarch64/trbe-invalid.l: New test. + * testsuite/gas/aarch64/trbe-invalid.s: New test. + * testsuite/gas/aarch64/trbe.d: New test. + * testsuite/gas/aarch64/trbe.s: New test. + +2020-09-28 Alex Coplan <alex.coplan@arm.com> + + * config/tc-arm.c (arm_cpus): Add FP16 to Neoverse V1. + +2020-09-28 Alex Coplan <alex.coplan@arm.com> + + * config/tc-aarch64.c (aarch64_cpus): Group Neoverse cores together, + add missing F16 bit to Neoverse V1. + +2020-09-26 Alan Modra <amodra@gmail.com> + + * config/tc-csky.c (parse_type_ctrlreg): Don't mask mach_flag + for csky_get_control_regno. + (csky_get_reg_val): Likewise when calling csky_get_general_regno. + +2020-09-24 Jim Wilson <jimw@sifive.com> + + PR 26400 + * config/tc-riscv.c (append_insn): If in absolute section, emit + error before add_relaxed_insn call. + * testsuite/gas/riscv/absolute-sec.d: New. + * testsuite/gas/riscv/absolute-sec.l: New. + * testsuite/gas/riscv/absolute-sec.s: New. + +2020-09-23 Mark Wielaard <mark@klomp.org> + + * testsuite/gas/elf/dwarf-5-cu.d: Adjust expected output. + +2020-09-24 Alex Coplan <alex.coplan@arm.com> + + * config/tc-arm.c (arm_cpus): Add Neoverse V1. + * doc/c-arm.texi: Document Neoverse V1 support. + +2020-09-24 Alex Coplan <alex.coplan@arm.com> + + * config/tc-aarch64.c (aarch64_cpu_option_table): Add Neoverse V1. + * doc/c-aarch64.texi: Document Neoverse V1 support. + +2020-09-24 Alex Coplan <alex.coplan@arm.com> + + * config/tc-arm.c (arm_cpus): Add Neoverse N2. + * doc/c-arm.texi: Document -mcpu=neoverse-n2. + +2020-09-24 Lili Cui <lili.cui@intel.com> + + * NEWS: Add TDX. + * config/tc-i386.c (cpu_arch): Add .tdx. + (cpu_noarch): Likewise. + * doc/c-i386.texi: Document tdx. + * testsuite/gas/i386/i386.exp: Run tdx tests. + * testsuite/gas/i386/tdx.d: Likewise. + * testsuite/gas/i386/tdx.s: Likewise. + * testsuite/gas/i386/x86-64-tdx.d: Likewise. + * testsuite/gas/i386/x86-64-tdx.s: Likewise. + +2020-09-17 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (parse_type_ctrlreg): Use function + csky_get_control_regno to operand. + (csky_get_reg_val): Likewise. + (is_reg_sp_with_bracket): Use function csky_get_reg_val + to parse operand. + (is_reg_sp): Refine. + (is_oimm_within_range): Fix, report error when operand + is not constant. + (parse_type_cpreg): Refine. + (parse_type_cpcreg): Refine. + (get_operand_value): Add handle of OPRND_TYPE_IMM5b_LS. + (md_assemble): Fix no error reporting somtimes when + operands number are not fit. + (csky_addc64): Refine. + (csky_subc64): Refine. + (csky_or64): Refine. + (v1_work_fpu_fo): Refine. + (v1_work_fpu_read): Refine. + (v1_work_fpu_writed): Refine. + (v1_work_fpu_readd): Refine. + (v2_work_addc): New function, strengthen the operands legality + check of addc. + * testsuite/gas/csky/all.d : Use register number format when + disassemble register name by default. + * testsuite/gas/csky/cskyv2_all.d : Likewise. + * testsuite/gas/csky/trust.d: Likewise. + * testsuite/gas/csky/cskyv2_ck860.d : Fix. + * testsuite/gas/csky/trust.s : Fix. + +2020-09-23 Lili Cui <lili.cui@intel.com> + + * NEWS: Add Key Locker. + * config/tc-i386.c (cpu_arch): Add .kl and .wide_kl. + (cpu_noarch): Likewise. + * doc/c-i386.texi: Document kl and wide_kl. + * testsuite/gas/i386/i386.exp: Run keylocker tests. + * testsuite/gas/i386/keylocker-intel.d: New test. + * testsuite/gas/i386/keylocker.d: Likewise. + * testsuite/gas/i386/keylocker.s: Likewise. + * testsuite/gas/i386/x86-64-keylocker-intel.d: Likewise. + * testsuite/gas/i386/x86-64-keylocker.d: Likewise. + * testsuite/gas/i386/x86-64-keylocker.s: Likewise. + * testsuite/gas/i386/x86-64-property-10.d: Likewise. + * testsuite/gas/i386/property-10.d: Likewise. + * testsuite/gas/i386/property-10.s: Likewise. + +2020-09-21 Alan Modra <amodra@gmail.com> + + PR 26569 + * config/tc-riscv.c (append_insn): Don't tie off frags at CALL + relocs. + (riscv_call): Tie them off after the jalr. + (md_apply_fix): Zero fx_size of RELAX fixup. + +2020-09-018 David Faust <david.faust@oracle.com> + + * testsuite/gas/bpf/alu-xbpf.d: New file. + * testsuite/gas/bpf/alu-xbpf.s: Likewise. + * testsuite/gas/bpf/alu32-xbpf.d: Likewise. + * testsuite/gas/bpf/alu32-xbpf.d: Likewise. + * testuiste/gas/bpf/bpf.exp: Run new tests. + +2020-09-18 Tucker <tuckkern+sourceware@gmail.com> + + PR 26556 + * read.c (bss_alloc): Convert size parameter from octets to + bytes. + +2020-09-17 Alan Modra <amodra@gmail.com> + + * testsuite/gas/i386/i386.exp: Return early if not x86. + +2020-09-16 Alan Modra <amodra@gmail.com> + + * config/obj-elf.c (obj_elf_visibility, elf_frob_symbol): Adjust + elf_symbol_from invocation. + * config/tc-aarch64.c (s_variant_pcs): Likewise. + * config/tc-m68hc11.c (s_m68hc11_mark_symbol): Likewise. + * config/tc-ppc.c (ppc_elf_localentry, ppc_force_relocation), + (ppc_fix_adjustable): Likewise. + * config/tc-xgate.c (xgate_frob_symbol): Likewise. + +2020-09-15 H.J. Lu <hongjiu.lu@intel.com> + + * testsuite/gas/cfi/reloc-pe-i386.d: Updated. + * testsuite/gas/i386/x86-64-w64-pcrel.d: Likewise. + +2020-09-15 Alan Modra <amodra@gmail.com> + + PR 26610 + * config/tc-arm.c (move_or_literal_pool): Correct extraction of + bignum. Use unsigned "v" + (is_double_a_single): Make "v" and "mantissa" unsigned. Formatting. + (double_to_single): Likewise. + +2020-09-15 Nick Clifton <nickc@redhat.com> + + * read.c (s_nop): Preserve the input_line_pointer around the call + to md_assemble. + * config/tc-s12z.c (md_assemble): Revert previous delta. + +2020-09-15 David Faust <david.faust@oracle.com> + + * config/tc-bpf.h (md_single_noop_insn): Use 'ja 0' for no-op. + +2020-09-14 Nick Clifton <nickc@redhat.com> + + * read.c (s_nop): New function. Handles the .nop directive. + (potable): Add entry for "nop". + (s_nops): Code tidy. + * read.h (s_nop): Add prototype. + * config/tc-bpf.h (md_single_noop_insn): Define. + * config/tc-mmix.h (md_single_noop_insn): Define. + * config/tc-or1k.h (md_single_noop_insn): Define. + * config/tc-ia64.h (md_single_noop_insn): Define. + * config/tc-s12z.c (md_assemble): Preserve the input line pointer, + rather than corrupting it. + * write.c (relax_segment): Update error message regarding + non-absolute values passed to .fill and .nops. + * NEWS: Mention the new directive. + * doc/as.texi: Document the new directive. + * doc/internals.texi: Document the new internal macros used to + implement the new directive. + * testsuite/gas/all/nop.s: New test. + * testsuite/gas/all/nop.d: New test control file. + * testsuite/gas/all/gas.exp: Run the new test. + * testsuite/gas/elf/dwarf-5-nop-for-line-table.s: New test. + * testsuite/gas/elf/dwarf-5-nop-for-line-table.d: New test + control file. + * testsuite/gas/elf/elf.exp: Run the new test. + * testsuite/gas/i386/space1.l: Adjust expected output. + +2020-09-07 Mark Wielaard <mark@klomp.org> + + * as.texi (-g): Explicitly mention when .debug_info and .debug_line + are generated for the DWARF format. + (Loc): Add that it is an error to both use a .loc directive and + generate a .debug_line yourself. + * dwarf2dbg.c (dwarf2_any_loc_directive_seen): New static variable. + (dwarf2_directive_loc): Set dwarf2_any_loc_directive_seen to TRUE. + (dwarf2_finish): Check dwarf2_any_loc_directive_seen before emitting + an error. Only create .debug_line if it is empty (or doesn't exist). + * testsuite/gas/i386/i386.exp: Add dwarf2-line-{1,2,3,4} when testing + an elf target. + * testsuite/gas/i386/dwarf2-line-{1,2,3,4}.{s,d,l}: New test files. + +2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (md_begin): Enable extend lrw by default for + CK802, CK803 and CK860. + +2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (struct csky_cpu_info): Add new members + isa_flag, features and ver. + (struct csky_cpu_feature): New. + (struct csky_cpu_version): New. + (CSKY_FEATURE_MAX): Define. + (CSKY_CPU_REVERISON_MAX): Define. + (FEATURE_DSP_EXT, FEATURE_DSP, FEATURE_MMU, FEATURE_VDSP, + FEATURE_FLOAT, FEATURE_TRUST, FEATURE_JAVA, FEATURE_SHIELD): + Define, each standard one collection of instructions. + (CSKY_FEATURES_DEF_NULL, CSKY_FEATURES_DEF_e, + CSKY_FEATURES_DEF_t, CSKY_FEATURES_DEF_f, CSKY_FEATURES_DEF_v, + CSKY_FEATURES_DEF_ef, CSKY_FEATURES_DEF_jt, + CSKY_FEATURES_DEF_efht, CSKY_FEATURES_DEF_efv, + CSKY_FEATURES_DEF_eft, CSKY_FEATURES_DEF_d, + CSKY_FEATURES_DEF_df, CSKY_FEATURES_DEF_ft, + CSKY_FEATURES_DEF_tv, CSKY_FEATURES_DEF_fv, + CSKY_FEATURES_DEF_dft, CSKY_FEATURES_DEF_dfv, + CSKY_FEATURES_DEF_ftv, CSKY_FEATURES_DEF_eftv): Define, + the features combination used by cpu. + (CSKY_CPU_REVERISON_r0p0, CSKY_CPU_REVERISON_r1p0, + CSKY_CPU_REVERISON_r2p0, CSKY_CPU_REVERISON_r3p0, + CSKY_CPU_REVERISON_RESERVED, CSKY_CPU_REVERISON_R3): + Define, version information used by cpu. + (csky_cpus): Refine, and add CK804, CK805 and CK800. + (parse_cpu): Refine. + (parse_arch): Refine. + (md_show_usage): Refine. + (md_begin): Refine. + +2020-09-09 Alan Modra <amodra@gmail.com> + + * config/tc-ppc.c (md_assemble): Emit prefix insn by parts when + valueT is smaller than 64 bits. + +2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (CSKYV2_ISA_DSP): CSKY_ISA_DSPE60. + (CSKY_ISA_860): Likewise. + +2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (float_abi): New. + (md_longopts): Add mfloat-abi. + (struct sky_option_value_table): New. + (csky_float_abis): New, the possible values for -mfloat-abi. + (parse_float_abi): New funtion. + (md_show_usage): Show help information for -mfloat-abi. + (set_csky_attribute): Store float-abi value. + +2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (float_work_fpuv3_fmovi): New function, + helper function to encode fpuv3 fmovi instructions. + (float_work_fpuv3_fstore): New function. + (struct literal): Add new member 'offset'. + (csky_cpus): New cpu CK860f. + (enter_literal): Return literal pool pointer instead of offset. + (parse_rt): Adjust the change of enter_literal. + (parse_rtf): Likewise. + (v1_work_lrw): Likewise. + (v1_work_jbsr): Likewise. + (v2_work_lrw): Likewise. + (v2_work_jbsr): Likewise. + (v2_work_jsri): Likewise. + (vdsp_work_vlrw): Likewise. + (is_freglist_legal): Add handler for FPUV3. + (parse_type_freg): Likewise. + (is_imm_within_range): Set e.X_add_number if it is a signed and + negtive number. + (get_operand_value): Add handler for OPRND_TYPE_IMM9b, + OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI + and OPRND_TYPE_DFLOAT_FMOVI. + (float_to_half): Convert float number to harf float. + * testsuite/gas/csky/case-fpuv3-ck860f/ : New folder containing + the test cases for FPUV3, they are divided by instruction + operands format and both have legal cases and illegal cases. + +2020-09-08 Jozef Lawrynowicz <jozef.l@mittosystems.com> + Kuan-Lin Chen <kuanlinchentw@gmail.com> + + * config/tc-msp430.c (msp430_insert_uleb128_fixes): New. + (msp430_md_end): Call msp430_insert_uleb128_fixes. + +2020-09-08 Alex Coplan <alex.coplan@arm.com> + + * config/tc-aarch64.c (aarch64_cpus): Add Cortex-R82. + * doc/c-aarch64.texi: Document -mcpu=cortex-r82. + +2020-09-08 Alex Coplan <alex.coplan@arm.com> + + * config/tc-aarch64.c (parse_sys_reg): Also pass sysreg name to + validation function. + (parse_sys_ins_reg): Likewise. + (print_operands): Pass CPU features to aarch64_print_operand(). + * testsuite/gas/aarch64/v8-r-bad-sysregs.d: New test. + * testsuite/gas/aarch64/v8-r-bad-sysregs.l: Error output. + * testsuite/gas/aarch64/v8-r-bad-sysregs.s: Input. + * testsuite/gas/aarch64/v8-r-sysregs-need-arch.d: New test. + * testsuite/gas/aarch64/v8-r-sysregs-need-arch.l: Error output. + * testsuite/gas/aarch64/v8-r-sysregs.d: New test. + * testsuite/gas/aarch64/v8-r-sysregs.s: Input for previous two tests. + +2020-09-08 Alex Coplan <alex.coplan@arm.com> + + * testsuite/gas/aarch64/dfb.d: New test. + * testsuite/gas/aarch64/dfb.s: Input. + +2020-09-08 Alex Coplan <alex.coplan@arm.com> + + * config/tc-aarch64.c (aarch64_archs): Add armv8-r. + * doc/c-aarch64.texi: Document -march=armv8-r. + +2020-09-07 Mark Wielaard <mark@klomp.org> + + * dwarf2dbg.c (add_line_strp): New function. + (out_dir_and_file_list): Take line_seg and sizeof_offset as + arguments, Use DW_FORM_line_strp for dir and file. Call + add_line_strp and set symbol offset for DWARF2_LINE_VERSION 5. + (out_debug_line): Call out_dir_and_file_list with line_seg and + sizeof_offset. + * testsuite/gas/elf/dwarf-5-file0.d: Expect indirect line + strings. + +2020-09-07 Mark Wielaard <mark@klomp.org> + + * dwarf2dbg.c (DWARF2_RNGLISTS_VERSION): New constant. + (out_debug_ranges): Add ranges_sym argument and set it. + (out_debug_rnglists): New function. + (out_debug_info): Change ranges_seg argument to ranges_sym + and use it to set DW_AT_ranges value. + (dwarf2_finish): Remove ranges_seg, add ranges_sym. For + DWARF2_VERSION 5 call out_debug_rnglists. + +2020-09-07 Mark Wielaard <mark@klomp.org> + + * dwarf2dbg.c (dwarf2_directive_filename): Initialize with_md5 to + FALSE. + * testsuite/gas/elf/dwarf-5-file0.s: Add a random bignum. + +2020-09-01 Mark Wielaard <mark@klomp.org> + + * dwarf2dbg.c (out_debug_abbrev): Use DW_FORM_sec_offset for DWARF + version 4 or higher. + +2020-09-02 Alan Modra <amodra@gmail.com> + + * expr.c (add_to_result, subtract_from_result): Use unsigned + addition and subtraction. + +2020-09-02 Alan Modra <amodra@gmail.com> + + * config/tc-z80.c (is_overflow): Avoid too large shift. + +2020-09-02 Alan Modra <amodra@gmail.com> + + * config/tc-sparc.c (in_signed_range): Use an unsigned type for + sign mask. + +2020-09-02 Alan Modra <amodra@gmail.com> + + * config/tc-nios2.c (md_apply_fix): Avoid too large shift. + +2020-09-02 Alan Modra <amodra@gmail.com> + + * config/tc-mips.c (load_register): Avoid too large shift. + +2020-09-02 Alan Modra <amodra@gmail.com> + + * config/tc-d30v.c (parallel_ok): Use 1UL for left shift expression. + +2020-09-02 Alan Modra <amodra@gmail.com> + + * config/rx-parse.y (rx_intop): Avoid too large shifts. + (rx_intop, rx_uintop, rx_disp3op, rx_disp5op, displacement), + (rtsd_immediate): Use correctly typed unsigned variables. + +2020-09-02 Alan Modra <amodra@gmail.com> + + * config/obj-macho.c (obj_mach_o_zerofill): Correct type of + constant shifted left. + +2020-09-02 Alan Modra <amodra@gmail.com> + + * config/bfin-lex.l: Use an unsigned type for "value". + +2020-09-02 Alan Modra <amodra@gmail.com> + + * config/tc-pdp11.c (md_number_to_chars): Condition nbytes=8 code + on BFD64. + +2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (csky_cpus): Add ck803r3. + (CSKY_ISA_803R3): Define. + (CSKY_ISA_803R2): Refine, use CSKY_ISA_803R1. + +2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com> + + * testsuite/gas/csky/cskyv2_dsp.d : Fix Encode of mulsws. + +2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (struct literal): New member bignum. + (dump_literals): Handle big constant. + (enter_literal): Likewise. + (parse_type_freg): Handle vector register. + +2020-09-01 H.J. Lu <hongjiu.lu@intel.com> + + * doc/as.texi: Document the .tls_common directive. + +2020-09-01 Alan Modra <amodra@gmail.com> + + PR 26420 + PR 26421 + PR 26425 + PR 26427 + * config/tc-arm.c (struct arm_it): Make size, size_req, cond and + uncond_value unsigned. + (parse_vfp_reg_list): Make setmask unsigned, vpr_str_len size_t. + (parse_big_immediate): Cast generic_bignum elements to unsigned. + (encode_thumb32_immediate): Shift left 0xffU. + (double_to_single): Make sign unsigned. Tidy. + (move_or_literal_pool): Cast LITTLE_NUM elements to uint64_t or + valueT. + (vfp_or_neon_is_neon): Adjust inst.uncond_value expression. + (md_assemble): Likewise. + (handle_pred_state): Make cond unsigned. + (thumb32_negate_data_op): Make variables unsigned. + (md_apply_fix): Make value and newval unsigned, adjust uses. + +2020-08-31 Alan Modra <amodra@gmail.com> + + PR 26510 + * config/tc-z8k.c (buffer): Use unsigned char. + (apply_fix): Use unsigned char* pointers. + (build_bytes): Likewise and mask nibbles when packing. + +2020-08-31 Alan Modra <amodra@gmail.com> + + PR 26503 + * config/tc-v850.c (parse_register_list): Shift 1u left. + +2020-08-31 Alan Modra <amodra@gmail.com> + + PR 26502 + * config/tc-tic6x.c (md_apply_fix): Use unsigned variables. + +2020-08-31 Alan Modra <amodra@gmail.com> + + PR 26497 + * config/tc-sh.c (assemble_ppi): Use unsigned variables. + +2020-08-31 Alan Modra <amodra@gmail.com> + + PR 26495 + * config/tc-score.c (s3_apply_fix): Use unsigned variables. + * config/tc-score7.c (s7_apply_fix): Likewise. + +2020-08-31 Alan Modra <amodra@gmail.com> + + PR 26480 + * config/tc-nios2.c (nios2_parse_reglist): Shift 1UL left. + +2020-08-31 Alan Modra <amodra@gmail.com> + + PR 26479 + * config/tc-nios2.c (md_chars_to_number): Cast buf[i] before shifting. + +2020-08-31 Alan Modra <amodra@gmail.com> + + PR 26472 + PR 26473 + PR 26474 + * config/tc-mips.c (operand_reg_mask): Shift 1u left. + (load_register): Shift 0xffffU left. + +2020-08-31 Alan Modra <amodra@gmail.com> + + PR 26471 + * config/tc-metag.c (md_chars_to_number): Make retval unsigned. + +2020-08-31 Alan Modra <amodra@gmail.com> + + PR 26468 + * config/tc-mep.c (md_convert_frag): Use uint32_t for addend and + other variables. + +2020-08-31 Alan Modra <amodra@gmail.com> + + PR 26493 + * config/tc-riscv.c (riscv_ip): Cast X_add_number passed to + VALID_* macros to unsigned. + +2020-08-31 Alan Modra <amodra@gmail.com> + + * config/tc-crx.c: Formatting. + (CRX_PRINT): Wrap params in parentheses. Remove parens from uses + throughout file. + (reset_vars, get_register, get_copregister, get_optype, get_opbits), + (get_opflags, get_number_of_operands, parse_operand, gettrap), + (handle_LoadStor, getconstant, check_range, getreg_image), + (parse_operands, parse_insn, print_operand, print_constant), + (exponent2scale, mask_reg, process_label_constant, set_operand), + (assemble_insn, print_insn): Delete unnecessary forward declaration. + (print_insn): Make static. + (print_constant): Make "constant" unsigned. + (assemble_insn): Tidy REVERSE_MATCH index calc. + * expr.c (generic_bignum_to_int32): Cast elements to valueT. + +2020-08-31 Alan Modra <amodra@gmail.com> + + PR 26509 + * config/tc-z80.c (is_overflow): Use 1UL in mask shift expression. + +2020-08-30 Alan Modra <amodra@gmail.com> + + * config/tc-tic4x.c (tic4x_gen_to_words): Rewrite mantissa + overflow test without UB. Avoid other UB shifts by making them + unsigned. + +2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (csky_error_state): New member 'arg_int'. + (SET_ERROR_NUMBER): Rename to SET_ERROR_STRING. + (SET_ERROR_INTEGER): New. + (err_formats): Add error format for ERROR_FREG_OVER_RANGE and + ERROR_VREG_OVER_RANGE. + (csky_show_error): Pass an integer argument for some error + numbers. + (parse_exp): Call SET_ERROR_STRING instead of SET_ERROR_NUMBER. + (parse_rt): Likewise. + (parse_type_ctrlreg): Likewise. + (csky_get_reg_val): Likewise. + (is_reglist_legal): Likewise. + (is_freglist_legal): Likewise. + (is_reglist_dash_comma_legal): Likewise. + (is_reg_lshift_illegal): Likewise. + (is_psr_bit): Likewise. + (parse_type_cpreg): Likewise. + (parse_type_cpcreg): Likewise. + (parse_type_areg): Likewise. + (parse_type_freg): Likewise. + (parse_ldst_imm): Likewise and call SET_ERROR_INTEGER. + (get_operand_value): Likewise. + (parse_operands_op): Likewise and call is_imm_within_range, + is_imm_within_range_ext and is_oimm_within_range. + (md_assemble): Likewise. + (is_imm_within_range): New. + (is_imm_within_range_ext): Rename from is_imm_over_range. + (is_oimm_within_range): Rename from is_oimm_over_range. + (v2_work_add_sub): Call SET_ERROR_INTEGER. + (csky_rolc): call is_imm_within_range instead of + is_imm_over_range. + +2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (md_begin): Add warning when -mdsp and + -mcpu=ck803ern are both added. + (parse_ldst_imm): Fix error message. + +2020-08-30 Alan Modra <amodra@gmail.com> + + * testsuite/gas/cr16/cbitb_test.d: Update expected output. + * testsuite/gas/cr16/cbitw_test.d: Likewise. + * testsuite/gas/cr16/sbitb_test.d: Likewise. + * testsuite/gas/cr16/sbitw_test.d: Likewise. + * testsuite/gas/cr16/storb_test.d: Likewise. + * testsuite/gas/cr16/storw_test.d: Likewise. + * testsuite/gas/cr16/tbitb_test.d: Likewise. + * testsuite/gas/cr16/tbitw_test.d: Likewise. + +2020-08-30 Alan Modra <amodra@gmail.com> + + PR 26437 + PR 26438 + * config/tc-cr16.c: Include limits.h, formatting. + (CR16_PRINT): Wrap params in parentheses. Remove parens from uses + throughout file. + (getconstant): Handle zero nbits. + (print_operand): Use unsigned variables. Simplify handling of + index regs. + (check_range): Use int32_t variables. Correct range checks. + +2020-08-29 Alan Modra <amodra@gmail.com> + + PR 26481 + * config/tc-pj.c (md_assemble): Don't loop past end of + opcode->arg array. + +2020-08-28 Alan Modra <amodra@gmail.com> + + PR 26460 + * config/tc-ia64.c (parse_operands): Don't access past end of + idesc->operands. + +2020-08-26 Mark Wielaard <mark@klomp.org> + + * as.c (parse_args): Handle bad -gdwarf options. + +2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (md_begin): Set attributes. + (isa_flag): Change type to unsigned 64 bits. + (struct csky_cpu_info): Likewise. + (struct csky_macro_info): Likewise. + (set_csky_attribute): New. + * testsuite/gas/csky/802j.d: Ignore .csky.attributes section. + * testsuite/gas/csky/all.d: Likewise. + * testsuite/gas/csky/bsr1.d: Likewise. + * testsuite/gas/csky/csky_vdsp.d: Likewise. + * testsuite/gas/csky/cskyv2_all.d: Likewise. + * testsuite/gas/csky/cskyv2_ck803r2.d: Likewise. + * testsuite/gas/csky/cskyv2_ck860.d: Likewise. + * testsuite/gas/csky/cskyv2_dsp.d: Likewise. + * testsuite/gas/csky/cskyv2_elrw.d: Likewise. + * testsuite/gas/csky/cskyv2_float.d: Likewise. + * testsuite/gas/csky/enhance_dsp.d: Likewise. + * testsuite/gas/csky/java.d: Likewise. + * testsuite/gas/csky/v1_float.d: Likewise. + * testsuite/gas/csky/v2_float_part1.d: Likewise. + * testsuite/gas/csky/v2_float_part2.d: Likewise. + * testsuite/gas/csky/v2_tls_gd.d: Likewise. + * testsuite/gas/csky/v2_tls_ie.d: Likewise. + * testsuite/gas/csky/v2_tls_ld.d: Likewise. + * testsuite/gas/csky/v2_tls_le.d: Likewise. + * testsuite/gas/elf/elf.exp: Add handler for CSKY. + * testsuite/gas/elf/section2.e-csky: New. + +2020-08-27 Alan Modra <amodra@gmail.com> + + PR 26467 + * cgen.c (weak_operand_overflow_check): Handle opmask for + operand length zero. Use 1UL constant. + +2020-08-26 Alan Modra <amodra@gmail.com> + + PR 26508 + * config/tc-xtensa.c (xg_get_trampoline_chain): Return early + when n_entries is zero. + +2020-08-26 Alan Modra <amodra@gmail.com> + + PR 26448 + * symbols.c: Include limits.h. + (resolve_symbol_value <O_left_shift, O_right_shift>): Do an + unsigned shift. Warn if shift count larger than valueT size. + +2020-08-26 Alan Modra <amodra@gmail.com> + + PR 26447 + * expr.c (expr <O_left_shift>): Do an unsigned shift. + +2020-08-25 Alan Modra <amodra@gmail.com> + +2020-08-26 David Faust <david.faust@oracle.com> + + * config/tc-bpf.c: Add option -mxbpf to select xbpf isa. + * testsuite/gas/bpf/indcall-1.d: New file. + * testsuite/gas/bpf/indcall-1.s: Likewise. + * testsuite/gas/bpf/indcall-bad-1.l: Likewise. + * testsuite/gas/bpf/indcall-bad-1.s: Likewise. + * testsuite/gas/bpf/bpf.exp: Run new tests. + +2020-08-25 Alan Modra <amodra@gmail.com> + + PR 26501 + * config/tc-tic54x.c (tic54x_undefined_symbol): Properly treat + misc_symbol_hash entries without values. + +2020-08-25 Alan Modra <amodra@gmail.com> + + PR 26500 + * config/tc-tic4x.c (tic4x_inst_make): Don't die on terminating + insn with name = "". + +2020-08-25 Alan Modra <amodra@gmail.com> + + PR 26441 + * config/tc-cr16.c (get_b_cc): Return NULL early if op isn't + two or three chars, and don't bother copying. + +2020-08-25 Alan Modra <amodra@gmail.com> + + PR 26426 + * config/tc-arm.c (do_neon_mvn, do_neon_swp): Bail out on + NS_NULL shape. + +2020-08-25 Alan Modra <amodra@gmail.com> + + PR 26410 + * symbols.c (dollar_label_count, dollar_label_max): Make size_t. + (dollar_label_clear): Don't call memset with NULL pointer. + +2020-08-25 Alan Modra <amodra@gmail.com> + + * config/tc-arc.c (declare_register_set): Avoid false positive + format-overflow warning. + * config/tc-epiphany.c (md_assemble): Likewise. + * config/tc-mips.c (md_begin): Likewise. + * config/tc-mmix.c (mmix_md_begin): Likewise. + * config/tc-nds32.c (nds32_elf_append_relax_relocs): Avoid false + positive "may be used uninitialized" warning. + +2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (csky_archs): Add item for CK860, + change ck810 and ck807's arch_flag. + (csky_cpus): Add item for CK860. + (md_begin): Enable DSP for CK810 and CK807 by default. + (md_apply_fix): Fix CKCORE_TLS_IE32 relocation failure. + * testsuite/gas/csky/cskyv2_all.d: Change 'sync 0' to 'sync'. + * testsuite/gas/csky/cskyv2_all.s: Likewise. + * testsuite/gas/csky/cskyv2_ck860.d: New. + * testsuite/gas/csky/cskyv2_ck860.s: New. + * testsuite/gas/csky/enhance_dsp.d: Change plsli.u16 to plsli.16. + * testsuite/gas/csky/enhance_dsp.s: Likewise. + +2020-08-24 Alan Modra <amodra@gmail.com> + + * config/tc-tic54x.c (stag_add_field_symbols): Don't free "name" + in case where it isn't copied. + * config/tc-tic54x.h (LOCAL_LABELS_FB): Undef. + * testsuite/gas/tic54x/field.d: Dump section contents and symbols + rather than disassembling. + * testsuite/gas/tic54x/set.d: Adjust for newer disassembly. + +2020-08-24 Alan Modra <amodra@gmail.com> + + * config/tc-aarch64.c (md_begin): Don't bother checking for + out of memory failure from str_htab_create. + * config/tc-arc.c (arc_insert_opcode, md_begin): Likewise. + (arc_extcorereg, arc_stralloc): Likewise. + * config/tc-arm.c (md_begin): Likewise. + * config/tc-cr16.c (initialise_reg_hash_table, md_begin): Likewise. + * config/tc-cris.c (md_begin): Likewise. + * config/tc-crx.c (md_begin): Likewise. + * config/tc-pdp11.c (md_begin): Likewise. + * config/tc-score.c (s3_build_reg_hsh, s3_begin): Likewise. + * config/tc-score7.c (s7_build_reg_hsh, s7_begin): Likewise. + +2020-08-24 Alan Modra <amodra@gmail.com> + + * config/tc-arm.c (move_or_literal_pool): Avoid false positive + "may be used uninitialised". + (opcode_lookup): Likewise. + +2020-08-24 Alan Modra <amodra@gmail.com> + + PR 26526 + * symbols.c (local_symbol_convert): Clear out xtra. + +2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (CSKY_ISA_803R2): New. + (csky_archs): Add ck803r2 series. + (md_begin): Fix warning about -medsp. + (csky_get_freg_val): Support lowercase of fpu register name. + * testsuite/gas/csky/cskyv2_ck803r2.s: New file. + * testsuite/gas/csky/cskyv2_ck803r2.d: New file. + +2020-08-23 Alan Modra <amodra@gmail.com> + + PR 26513 + * hash.h (htab_insert): Update prototype and comment. + (struct string_tuple): Make "value" a const void*. + (string_tuple_alloc): Likewise. + (str_hash_find, str_hash_find_n): Cast returned value. + (str_hash_insert): Add "replace" parameter, and return slot pointer. + Free alloc'd element when not inserted. + * hash.c (htab_insert): Likewise. Return slot when element exists, + otherwise return NULL. + * read.c (pop_insert): Insert into hash table without first searching. + * config/tc-avr.c (md_begin): Likewise. + * config/tc-msp430.c (md_begin): Likewise. + * config/tc-nds32.c (nds32_init_nds32_pseudo_opcodes): Likewise. + * config/tc-v850.c (md_begin): Likewise. + * macro.c (do_formals, define_macro, macro_expand_body): Likewise. + (delete_macro): Delete from hash table. + * config/tc-tic54x.c (subsym_create_or_replace): Correct logic. + + * symbols.c (local_symbol_make, symbol_table_insert): Allow + replacement of hash table entries. + * config/obj-coff-seh.c (seh_hash_insert): Likewise. + * config/obj-coff.c (tag_insert): Likewise. + * config/tc-iq2000.c (iq2000_add_macro): Likewise. + * config/tc-m68k.c (md_begin): Likewise for aliases. + * config/tc-tic4x.c (tic4x_asg): Likewise. + * config/tc-tic6x.c (md_begin): Likewise. + + * dw2gencfi.c (dwcfi_hash_find_or_make): Disallow replacement of + hash table entries. + * ecoff.c (add_string, get_tag): Likewise. + * macro.c (expand_irp): Likewise. + * config/obj-elf.c (build_additional_section_info): Likewise. + * config/tc-aarch64.c (insert_reg_alias): Likewise. + (checked_hash_insert): Likewise. + * config/tc-alpha.c (get_alpha_reloc_tag, md_begin): Likewise. + * config/tc-arc.c (arc_insert_opcode, declare_register): Likewise. + (declare_addrtype, md_begin, arc_extcorereg): Likewise. + * config/tc-arm.c (insert_reg_alias): Likewise. + (arm_tc_equal_in_insn, md_begin): Likewise. + * config/tc-cr16.c (initialise_reg_hash_table, md_begin): Likewise. + * config/tc-cris.c (md_begin): Likewise. + * config/tc-crx.c (md_begin): Likewise. + * config/tc-csky.c (md_begin): Likewise. + * config/tc-d10v.c (md_begin): Likewise. + * config/tc-dlx.c (md_begin): Likewise. + * config/tc-ft32.c (md_begin): Likewise. + * config/tc-h8300.c (md_begin): Likewise. + * config/tc-hppa.c (md_begin): Likewise. + * config/tc-i386.c (md_begin): Likewise. + * config/tc-ia64.c (dot_rot, dot_entry, declare_register): Likewise. + (md_begin, dot_alias): Likewise. + * config/tc-m68hc11.c (md_begin): Likewise. + * config/tc-m68k.c (md_begin): Likewise. + * config/tc-mcore.c (md_begin): Likewise. + * config/tc-microblaze.c (md_begin): Likewise. + * config/tc-mips.c (md_begin): Likewise. + * config/tc-mmix.c (md_begin): Likewise. + * config/tc-mn10200.c (md_begin): Likewise. + * config/tc-mn10300.c (md_begin): Likewise. + * config/tc-moxie.c (md_begin): Likewise. + * config/tc-nds32.c (nds32_relax_hint, md_begin): Likewise. + * config/tc-nios2.c (md_begin): Likewise. + * config/tc-ns32k.c (md_begin): Likewise. + * config/tc-pdp11.c (md_begin): Likewise. + * config/tc-pj.c (fake_opcode, md_begin): Likewise. + * config/tc-ppc.c (ppc_setup_opcodes): Likewise. + * config/tc-pru.c (md_begin): Likewise. + * config/tc-riscv.c (init_ext_version_hash): Likewise. + (init_opcode_names_hash, hash_reg_name, init_opcode_hash): Likewise. + (riscv_init_csr_hash): Likewise. + * config/tc-s390.c (s390_setup_opcodes, md_begin): Likewise. + * config/tc-score.c (s3_insert_reg): Likewise. + (s3_build_score_ops_hsh, s3_build_dependency_insn_hsh): Likewise. + * config/tc-score7.c (s7_build_score_ops_hsh): Likewise. + (s7_build_dependency_insn_hsh, s7_insert_reg): Likewise. + * config/tc-sh.c (md_begin): Likewise. + * config/tc-sparc.c (md_begin): Likewise. + * config/tc-spu.c (md_begin): Likewise. + * config/tc-tic30.c (md_begin): Likewise. + * config/tc-tic4x.c (tic4x_inst_insert): Likewise. + * config/tc-tic54x.c (stag_add_field_symbols, md_begin): Likewise. + (tic54x_endstruct, tic54x_var, tic54x_macro_info): Likewise. + (subsym_substitute): Likewise. + * config/tc-tilegx.c (md_begin): Likewise. + * config/tc-tilepro.c (md_begin): Likewise. + * config/tc-vax.c (vip_begin): Likewise. + * config/tc-wasm32.c (md_begin): Likewise. + * config/tc-xgate.c (md_begin): Likewise. + * config/tc-z8k.c (md_begin): Likewise. + * testsuite/gas/ppc/dcbt.d, + * testsuite/gas/ppc/dcbt.s: New test. + * testsuite/gas/ppc/ppc.exp: Run it. + + * ecoff.c (add_string): Report fatal error on duplicates. + * config/tc-alpha.c (md_begin): Likewise. + * config/tc-arc.c (arc_insert_opcode, declare_register): Likewise. + (declare_addrtype, md_begin, arc_extcorereg): Likewise. + * config/tc-cr16.c (initialise_reg_hash_table, md_begin): Likewise. + * config/tc-cris.c (md_begin): Likewise. + * config/tc-crx.c (md_begin): Likewise. + * config/tc-dlx.c (md_begin): Likewise. + * config/tc-hppa.c (md_begin): Likewise. + * config/tc-i386.c (md_begin): Likewise. + * config/tc-ia64.c (dot_rot, dot_entry, declare_register): Likewise. + (md_begin): Likewise. + * config/tc-m68k.c (md_begin): Likewise. + * config/tc-mips.c (md_begin): Likewise. + * config/tc-nios2.c (md_begin): Likewise. + * config/tc-ns32k.c (md_begin): Likewise. + * config/tc-ppc.c (ppc_setup_opcodes): Likewise. + * config/tc-pru.c (md_begin): Likewise. + * config/tc-riscv.c (init_ext_version_hash): Likewise. + (init_opcode_names_hash, hash_reg_name, init_opcode_hash): Likewise. + * config/tc-s390.c (s390_setup_opcodes, md_begin): Likewise. + * config/tc-sparc.c (md_begin): Likewise. + * config/tc-tic30.c (md_begin): Likewise. + * config/tc-tic4x.c (tic4x_inst_insert): Likewise. + * config/tc-tilegx.c (md_begin): Likewise. + * config/tc-tilepro.c (md_begin): Likewise. + * config/tc-vax.c (vip_begin): Likewise. + + * config/tc-alpha.c, + * config/tc-arm.c, + * config/tc-avr.c, + * config/tc-cr16.c, + * config/tc-csky.c, + * config/tc-i386.c, + * config/tc-m68hc11.c, + * config/tc-m68k.c, + * config/tc-microblaze.c, + * config/tc-ns32k.c, + * config/tc-pj.c, + * config/tc-ppc.c, + * config/tc-score.c, + * config/tc-score7.c, + * config/tc-tic4x.c, + * config/tc-tic54x.c, + * config/tc-tilegx.c, + * config/tc-tilepro.c, + * config/tc-xgate.c: Formatting. + +2020-08-21 Alan Modra <amodra@gmail.com> + + * symbols.c (struct local_symbol): Add "hash" entry. Reorder fields. + Delete union. Adjust code throughout file. + (struct symbol): Add "hash", "name" and "x" entries. Reorder fields. + Split off some to.. + (struct xsymbol): ..this. New struct. Adjust code throughout file + accessing these fields. + (struct symbol_entry): Delete. + (union symbol_entry): New. + (hash_symbol_entry): Adjust for symbol_entry_t change. + (symbol_entry_find): Likewise. + (eq_symbol_entry): Compare hash values too. + (symbol_entry_alloc): Delete. + (local_symbol_converted_p, local_symbol_mark_converted): Delete. + (local_symbol_get_real_symbol, local_symbol_set_real_symbol): Delete. + (local_hash): Delete. + (abs_symbol_x, dot_symbol_x): New static var. + (symbol_init): New function. + (symbol_create): Rewrite. + (LOCAL_SYMBOL_CHECK): Delete. Replace uses throughout with simple + test of flags.local_symbol. + (local_symbol_make): Adjust for struct local_symbol changes. + (local_symbol_convert): Rewrite. Adjust all callers. + (symbol_table_insert): Simplify. + (symbol_clone): Comment on local sym cloning. Handle split symbol + struct. + (get_real_sym): Delete. Remove all uses. + (symbol_find_exact_noref): Simplify. + (resolve_local_symbol): Don't resolve non-locals. + (S_SET_SEGMENT): Don't special case reg_section. + (S_SET_NAME): Set both name and bsym->name. + (symbol_mark_resolved, symbol_resolved_p): Simplify. + (symbol_symbolS): Update comment. + (symbol_begin): Don't create local_hash. Adjust abs_symbol setup. + (dot_symbol_init): Adjust dot_symbol setup. + (symbol_print_statistics): Delete local_hash stats. + +2020-08-21 Alan Modra <amodra@gmail.com> + + * symbols.c (struct symbol_flags): Rename sy_volatile to volatil, + and remove sy_ from other field names. Update throughout. + (struct symbol): Remove sy_ from field names. Delete unused + TARGET_SYMBOL_FIELDS. Update throughout file. Move after.. + (struct local_symbol): ..here. Remove lsy_ from field names. + Delete unused TC_LOCAL_SYMFIELD_TYPE. Update throughout file. + (local_symbol_resolved_p, local_symbol_mark_resolved): Delete. + Expand uses throughout file. + (local_symbol_get_frag, local_symbol_set_frag): Likewise. + (symbol_new): Move symbol_table_frozen test to.. + (symbol_append): ..here, and.. + (symbol_insert): ..here. + (resolve_symbol_value, symbol_relc_make_expr): White space fixes. + (HANDLE_XADD_OPT1, HANDLE_XADD_OPT2): Likewise. + * config/obj-coff.h (RESOLVE_SYMBOL_REDEFINITION): Update. + +2020-08-21 Alan Modra <amodra@gmail.com> + + * symbols.h (symbol_new, symbol_create, local_symbol_make), + (symbol_temp_new): Arrange params as section, frag, offset. + * symbols.c: Adjust to suit. + * as.c: Likewise. + * cgen.c: Likewise. + * dwarf2dbg.c: Likewise. + * ecoff.c: Likewise. + * expr.c: Likewise. + * itbl-ops.c: Likewise. + * read.c: Likewise. + * stabs.c: Likewise. + * subsegs.c: Likewise. + * config/obj-coff.c: Likewise. + * config/obj-elf.c: Likewise. + * config/obj-macho.c: Likewise. + * config/tc-aarch64.c: Likewise. + * config/tc-alpha.c: Likewise. + * config/tc-arc.c: Likewise. + * config/tc-arm.c: Likewise. + * config/tc-avr.c: Likewise. + * config/tc-cr16.c: Likewise. + * config/tc-cris.c: Likewise. + * config/tc-csky.c: Likewise. + * config/tc-dlx.c: Likewise. + * config/tc-hppa.c: Likewise. + * config/tc-i386.c: Likewise. + * config/tc-ia64.c: Likewise. + * config/tc-m32r.c: Likewise. + * config/tc-m68k.c: Likewise. + * config/tc-mips.c: Likewise. + * config/tc-mmix.c: Likewise. + * config/tc-mn10200.c: Likewise. + * config/tc-mn10300.c: Likewise. + * config/tc-nds32.c: Likewise. + * config/tc-nios2.c: Likewise. + * config/tc-ppc.c: Likewise. + * config/tc-riscv.c: Likewise. + * config/tc-s390.c: Likewise. + * config/tc-sh.c: Likewise. + * config/tc-tic4x.c: Likewise. + * config/tc-tic54x.c: Likewise. + * config/tc-xtensa.c: Likewise. + +2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (csky_insn_info): Add member last_isize. + (md_assemble): Assign value to csky_insn.last_isize. + * testsuite/gas/csky/enhance_dsp.d: Test bloop's two operands form. + * testsuite/gas/csky/enhance_dsp.s: Likewise. + +2020-08-20 Martin Liska <mliska@suse.cz> + + * NEWS: Mention --reduce-memory-overheads and --hash-size arguments + options. + * as.c: Remove the options from help. + * doc/as.texi: Remove options. + * doc/internals.texi: Remove hash from documentation. + * hash.c (struct hash_entry): Remove. + (struct hash_control): Likewise. + (set_gas_hash_table_size): Likewise. + (hash_new_sized): Likewise. + (hash_new): Likewise. + (hash_die): Likewise. + (hash_lookup): Likewise. + (hash_insert): Likewise. + (hash_jam): Likewise. + (hash_replace): Likewise. + (hash_find): Likewise. + (hash_find_n): Likewise. + (hash_delete): Likewise. + (hash_traverse): Likewise. + (hash_print_statistics): Likewise. + (TABLES): Likewise. + (STATBUFSIZE): Likewise. + (main): Likewise. + (what): Likewise. + (destroy): Likewise. + (applicatee): Likewise. + (whattable): Likewise. + * hash.h (struct hash_control): Likewise. + (set_gas_hash_table_size): Likewise. + (hash_new): Likewise. + (hash_new_sized): Likewise. + (hash_die): Likewise. + (hash_insert): Likewise. + (hash_jam): Likewise. + (hash_replace): Likewise. + (hash_find): Likewise. + (hash_find_n): Likewise. + (hash_delete): Likewise. + (hash_traverse): Likewise. + (hash_print_statistics): Likewise. + +2020-08-20 Martin Liska <mliska@suse.cz> + + * config/obj-coff-seh.c (seh_hash_insert): Port to use new + str_htab type. + (seh_hash_find): Likewise. + (seh_hash_find_or_make): Likewise. + * config/obj-coff.c (tag_init): Likewise. + (tag_insert): Likewise. + (tag_find): Likewise. + * config/obj-elf.c (struct group_list): Likewise. + (build_additional_section_info): Likewise. + (free_section_idx): Likewise. + (elf_adjust_symtab): Likewise. + (elf_frob_file_after_relocs): Likewise. + * config/tc-aarch64.c (INSN_SIZE): Likewise. + (parse_reg): Likewise. + (insert_reg_alias): Likewise. + (create_register_alias): Likewise. + (s_unreq): Likewise. + (parse_shift): Likewise. + (parse_pldop): Likewise. + (parse_barrier): Likewise. + (parse_barrier_psb): Likewise. + (parse_bti_operand): Likewise. + (parse_sys_reg): Likewise. + (parse_sys_ins_reg): Likewise. + (lookup_mnemonic): Likewise. + (opcode_lookup): Likewise. + (parse_operands): Likewise. + (checked_hash_insert): Likewise. + (sysreg_hash_insert): Likewise. + (fill_instruction_hash_table): Likewise. + (md_begin): Likewise. + * config/tc-alpha.c (struct alpha_reloc_tag): Likewise. + (get_alpha_reloc_tag): Likewise. + (assemble_tokens_to_insn): Likewise. + (assemble_tokens): Likewise. + (md_begin): Likewise. + * config/tc-arc.c (arc_find_opcode): Likewise. + (arc_insert_opcode): Likewise. + (find_opcode_match): Likewise. + (declare_register): Likewise. + (declare_addrtype): Likewise. + (md_begin): Likewise. + (arc_parse_name): Likewise. + (tc_arc_regname_to_dw2regnum): Likewise. + (arc_extcorereg): Likewise. + * config/tc-arm.c (MVE_BAD_QREG): Likewise. + (arm_reg_parse_multi): Likewise. + (parse_reloc): Likewise. + (insert_reg_alias): Likewise. + (create_register_alias): Likewise. + (s_unreq): Likewise. + (parse_shift): Likewise. + (parse_psr): Likewise. + (parse_cond): Likewise. + (parse_barrier): Likewise. + (do_vfp_nsyn_opcode): Likewise. + (opcode_lookup): Likewise. + (arm_tc_equal_in_insn): Likewise. + (md_begin): Likewise. + * config/tc-avr.c (md_begin): Likewise. + (avr_ldi_expression): Likewise. + (md_assemble): Likewise. + (avr_update_gccisr): Likewise. + (avr_emit_insn): Likewise. + * config/tc-cr16.c (get_register): Likewise. + (get_register_pair): Likewise. + (get_index_register): Likewise. + (get_index_register_pair): Likewise. + (get_pregister): Likewise. + (get_pregisterp): Likewise. + (initialise_reg_hash_table): Likewise. + (md_begin): Likewise. + (cr16_assemble): Likewise. + (md_assemble): Likewise. + * config/tc-cris.c (cris_insn_first_word_frag): Likewise. + (md_begin): Likewise. + (cris_process_instruction): Likewise. + * config/tc-crx.c (get_register): Likewise. + (get_copregister): Likewise. + (md_begin): Likewise. + (md_assemble): Likewise. + * config/tc-csky.c (md_begin): Likewise. + (parse_opcode): Likewise. + (get_operand_value): Likewise. + (v1_work_jbsr): Likewise. + (v2_work_rotlc): Likewise. + (v2_work_bgeni): Likewise. + (v2_work_not): Likewise. + * config/tc-d10v.c (sizeof): Likewise. + (md_begin): Likewise. + (do_assemble): Likewise. + (md_apply_fix): Likewise. + * config/tc-d30v.c (sizeof): Likewise. + (md_begin): Likewise. + (do_assemble): Likewise. + * config/tc-dlx.c (RELOC_DLX_VTENTRY): Likewise. + (md_begin): Likewise. + (machine_ip): Likewise. + * config/tc-ft32.c (md_begin): Likewise. + (md_assemble): Likewise. + * config/tc-h8300.c (md_begin): Likewise. + (md_assemble): Likewise. + * config/tc-hppa.c (pa_ip): Likewise. + (md_begin): Likewise. + * config/tc-i386.c (md_begin): Likewise. + (i386_print_statistics): Likewise. + (parse_insn): Likewise. + (process_operands): Likewise. + (i386_index_check): Likewise. + (parse_real_register): Likewise. + * config/tc-ia64.c (dot_rot): Likewise. + (dot_entry): Likewise. + (declare_register): Likewise. + (md_begin): Likewise. + (ia64_parse_name): Likewise. + (md_assemble): Likewise. + (dot_alias): Likewise. + (do_alias): Likewise. + (ia64_adjust_symtab): Likewise. + (do_secalias): Likewise. + (ia64_frob_file): Likewise. + * config/tc-m68hc11.c (m68hc11_print_statistics): Likewise. + (md_begin): Likewise. + (print_insn_format): Likewise. + (md_assemble): Likewise. + * config/tc-m68k.c (tc_gen_reloc): Likewise. + (m68k_ip): Likewise. + (md_begin): Likewise. + * config/tc-mcore.c (md_begin): Likewise. + (md_assemble): Likewise. + * config/tc-microblaze.c (md_begin): Likewise. + (md_assemble): Likewise. + (md_apply_fix): Likewise. + * config/tc-mips.c (nopic_need_relax): Likewise. + (md_begin): Likewise. + (macro_build): Likewise. + (mips16_macro_build): Likewise. + (mips_lookup_insn): Likewise. + (mips_ip): Likewise. + (mips16_ip): Likewise. + * config/tc-mmix.c (sizeof): Likewise. + (mmix_md_begin): Likewise. + (md_assemble): Likewise. + * config/tc-mn10200.c (md_begin): Likewise. + (md_assemble): Likewise. + * config/tc-mn10300.c (HAVE_AM30): Likewise. + (md_begin): Likewise. + (md_assemble): Likewise. + * config/tc-moxie.c (md_begin): Likewise. + (md_assemble): Likewise. + * config/tc-msp430.c (md_begin): Likewise. + (msp430_operands): Likewise. + (md_assemble): Likewise. + * config/tc-nds32.c (PV_DONT_CARE): Likewise. + (builtin_isreg): Likewise. + (builtin_regnum): Likewise. + (nds32_init_nds32_pseudo_opcodes): Likewise. + (nds32_lookup_pseudo_opcode): Likewise. + (nds32_relax_hint): Likewise. + (md_begin): Likewise. + (nds32_find_reloc_table): Likewise. + (nds32_elf_append_relax_relocs_traverse): Likewise. + (nds32_relax_branch_instructions): Likewise. + (md_convert_frag): Likewise. + (nds32_elf_analysis_relax_hint): Likewise. + (tc_nds32_regname_to_dw2regnum): Likewise. + * config/tc-nios2.c (nios2_opcode_lookup): Likewise. + (nios2_reg_lookup): Likewise. + (nios2_ps_lookup): Likewise. + (md_begin): Likewise. + * config/tc-ns32k.c (struct hash_control): Likewise. + (parse): Likewise. + (md_begin): Likewise. + * config/tc-pdp11.c (md_begin): Likewise. + (md_assemble): Likewise. + * config/tc-pj.c (fake_opcode): Likewise. + (alias): Likewise. + (md_begin): Likewise. + (md_assemble): Likewise. + * config/tc-ppc.c (ppc_setup_opcodes): Likewise. + (md_assemble): Likewise. + * config/tc-pru.c (pru_opcode_lookup): Likewise. + (pru_reg_lookup): Likewise. + (md_begin): Likewise. + (md_end): Likewise. + * config/tc-riscv.c (init_ext_version_hash): Likewise. + (riscv_get_default_ext_version): Likewise. + (riscv_set_arch): Likewise. + (init_opcode_names_hash): Likewise. + (opcode_name_lookup): Likewise. + (enum reg_class): Likewise. + (hash_reg_name): Likewise. + (riscv_init_csr_hash): Likewise. + (reg_csr_lookup_internal): Likewise. + (reg_lookup_internal): Likewise. + (init_opcode_hash): Likewise. + (md_begin): Likewise. + (DECLARE_CSR): Likewise. + (macro_build): Likewise. + (riscv_ip): Likewise. + * config/tc-s390.c (register_name): Likewise. + (s390_setup_opcodes): Likewise. + (md_begin): Likewise. + (md_assemble): Likewise. + (s390_insn): Likewise. + * config/tc-score.c (struct s3_reg_map): Likewise. + (s3_score_reg_parse): Likewise. + (s3_dependency_type_from_insn): Likewise. + (s3_parse_16_32_inst): Likewise. + (s3_parse_48_inst): Likewise. + (s3_insert_reg): Likewise. + (s3_build_reg_hsh): Likewise. + (s3_build_score_ops_hsh): Likewise. + (s3_build_dependency_insn_hsh): Likewise. + (s3_begin): Likewise. + * config/tc-score7.c (struct s7_reg_map): Likewise. + (s7_score_reg_parse): Likewise. + (s7_dependency_type_from_insn): Likewise. + (s7_parse_16_32_inst): Likewise. + (s7_build_score_ops_hsh): Likewise. + (s7_build_dependency_insn_hsh): Likewise. + (s7_insert_reg): Likewise. + (s7_build_reg_hsh): Likewise. + (s7_begin): Likewise. + * config/tc-sh.c (EMPTY): Likewise. + (md_begin): Likewise. + (find_cooked_opcode): Likewise. + * config/tc-sparc.c (md_begin): Likewise. + (sparc_ip): Likewise. + * config/tc-spu.c (md_begin): Likewise. + (md_assemble): Likewise. + * config/tc-tic30.c (md_begin): Likewise. + (tic30_operand): Likewise. + (tic30_parallel_insn): Likewise. + (md_assemble): Likewise. + * config/tc-tic4x.c (TIC4X_ALT_SYNTAX): Likewise. + (tic4x_asg): Likewise. + (tic4x_inst_insert): Likewise. + (tic4x_inst_add): Likewise. + (md_begin): Likewise. + (tic4x_operand_parse): Likewise. + (md_assemble): Likewise. + * config/tc-tic54x.c (MAX_SUBSYM_HASH): Likewise. + (stag_add_field_symbols): Likewise. + (tic54x_endstruct): Likewise. + (tic54x_tag): Likewise. + (tic54x_remove_local_label): Likewise. + (tic54x_clear_local_labels): Likewise. + (tic54x_var): Likewise. + (tic54x_macro_start): Likewise. + (tic54x_macro_info): Likewise. + (tic54x_macro_end): Likewise. + (subsym_isreg): Likewise. + (subsym_structsz): Likewise. + (md_begin): Likewise. + (is_mmreg): Likewise. + (is_type): Likewise. + (encode_condition): Likewise. + (encode_cc3): Likewise. + (encode_cc2): Likewise. + (encode_operand): Likewise. + (tic54x_parse_insn): Likewise. + (tic54x_parse_parallel_insn_firstline): Likewise. + (subsym_create_or_replace): Likewise. + (subsym_lookup): Likewise. + (subsym_substitute): Likewise. + (tic54x_undefined_symbol): Likewise. + * config/tc-tic6x.c (md_begin): Likewise. + (md_assemble): Likewise. + * config/tc-tilegx.c (O_hw2_last_plt): Likewise. + (INSERT_SPECIAL_OP): Likewise. + (md_begin): Likewise. + (tilegx_parse_name): Likewise. + (parse_reg_expression): Likewise. + (md_assemble): Likewise. + * config/tc-tilepro.c (O_tls_ie_load): Likewise. + (INSERT_SPECIAL_OP): Likewise. + (tilepro_parse_name): Likewise. + (parse_reg_expression): Likewise. + (md_assemble): Likewise. + * config/tc-v850.c (md_begin): Likewise. + (md_assemble): Likewise. + * config/tc-vax.c (md_ri_to_chars): Likewise. + (vip_begin): Likewise. + (vip): Likewise. + (main): Likewise. + (md_begin): Likewise. + * config/tc-wasm32.c (md_begin): Likewise. + (md_assemble): Likewise. + * config/tc-xgate.c (xgate_parse_operand): Likewise. + (md_begin): Likewise. + (md_assemble): Likewise. + * config/tc-z8k.c (md_begin): Likewise. + (md_assemble): Likewise. + +2020-08-20 Martin Liska <mliska@suse.cz> + + * dw2gencfi.c (dwcfi_hash_insert): Use htab_t and str_hash_* + functions. + (dwcfi_hash_find): Likewise. + (dwcfi_hash_find_or_make): Likewise. + +2020-08-20 Martin Liska <mliska@suse.cz> + + * ecoff.c (INIT_VARRAY): Use htab_t. + (add_string): Likewise. + (ecoff_read_begin_hook): Use new str_htab_create. + (get_tag): Use htab_t. + (add_file): Likewise. + +2020-08-20 Martin Liska <mliska@suse.cz> + + * hash.h (struct string_tuple): New. + (hash_string_tuple): Likewise. + (eq_string_tuple): Likewise. + (string_tuple_alloc): Likewise. + (str_hash_find): Likewise. + (str_hash_find_n): Likewise. + (str_hash_delete): Likewise. + (str_hash_insert): Likewise. + (str_htab_create): Likewise. + +2020-08-20 Martin Liska <mliska@suse.cz> + + * symbols.c (struct symbol_entry): New. + (hash_symbol_entry): Likewise. + (eq_symbol_entry): Likewise. + (symbol_entry_alloc): Likewise. + (symbol_entry_find): Likewise. + (local_symbol_make): Use htab hash table. + (local_symbol_convert): Likewise. + (symbol_table_insert): Likewise. + (symbol_find_exact_noref): Likewise. + (resolve_local_symbol): Likewise. + (resolve_local_symbol_values): Likewise. + (symbol_begin): Likewise. + (symbol_print_statistics): Likewise. + +2020-08-20 Martin Liska <mliska@suse.cz> + + * read.c (struct po_entry): New. + (hash_po_entry): Likewise. + (eq_po_entry): Likewise. + (po_entry_alloc): Likewise. + (po_entry_find): Likewise. + (pop_insert): Likewise. + (pobegin): Use htab hash table. + (read_a_source_file): Likewise. + (s_macro): Likewise. + (read_print_statistics): Likewise. + * config/tc-m68k.c (m68k_conditional_pseudoop): Add const qualifier. + * config/tc-m68k.h (m68k_conditional_pseudoop): Likewise. + +2020-08-20 Martin Liska <mliska@suse.cz> + + * config/tc-iq2000.c (iq2000_add_macro): Use htab hash table. + * macro.c (struct hash_control): Use htab. + (macro_init): Likewise. + (do_formals): Likewise. + (free_macro): Likewise. + (define_macro): Likewise. + (sub_actual): Likewise. + (macro_expand_body): Likewise. + (macro_expand): Likewise. + (check_macro): Likewise. + (delete_macro): Likewise. + (expand_irp): Likewise. + * macro.h (struct macro_hash_entry): New struct. + (hash_macro_entry): New. + (eq_macro_entry): Likewise. + (macro_entry_alloc): Likewise. + (macro_entry_find): Likewise. + (struct formal_hash_entry): Likewise. + (hash_formal_entry): Likewise. + (eq_formal_entry): Likewise. + (formal_entry_alloc): Likewise. + (formal_entry_find): Likewise. + +2020-08-20 Martin Liska <mliska@suse.cz> + + * as.h: Include hashtab.h. + * hash.c (htab_insert): New. + (htab_print_statistics): Likewise. + * hash.h (htab_insert): Likewise. + (htab_print_statistics): Likewise. + +2020-08-19 Alan Modra <amodra@gmail.com> + + * testsuite/gas/ppc/int128.s: Correct vcmpuq. + * testsuite/gas/ppc/int128.d: Update. + * testsuite/gas/ppc/xvtlsbb.d: Update. + +2020-08-18 Peter Bergner <bergner@linux.ibm.com> + + * testsuite/gas/ppc/vsx4.s: Update test to use new mnemonic. + * testsuite/gas/ppc/vsx4.d: Likewise. + +2020-08-17 Alex Coplan <alex.coplan@arm.com> + + * config/obj-elf.c (obj_elf_change_section): When repurposing an + existing symbol, ensure that we set sy_value as per other (fresh) + section symbols. + * testsuite/gas/elf/elf.exp: Add new test. + * testsuite/gas/elf/section-symbol-redef.d: New test. + * testsuite/gas/elf/section-symbol-redef.s: Input for test. + +2020-08-13 Nick Clifton <nickc@redhat.com> + + PR 26359 + * config/obj-som.c (obj_som_init_stab_section): Do nothing if the + $GDB_DEBUG$ section has already been created. + +2020-08-12 Joe Ramsay <joe.ramsay@.arm.com> + + * config/tc-arm.c (do_neon_cvt_1): Parse vcvtne as vcvt-ne for + NS_FD shape when MVE is present + * testsuite/gas/arm/mve-vcvtne-it-bad.d: New test. + * testsuite/gas/arm/mve-vcvtne-it-bad.l: New test. + * testsuite/gas/arm/mve-vcvtne-it-bad.s: New test. + * testsuite/gas/arm/mve-vcvtne-it.d: New test. + * testsuite/gas/arm/mve-vcvtne-it.s: New test. + +2020-08-12 Alex Coplan <alex.coplan@arm.com> + + * testsuite/gas/aarch64/mpam-bad.d: New test. + * testsuite/gas/aarch64/mpam-bad.l: Error output. + * testsuite/gas/aarch64/mpam-bad.s: Input. + * testsuite/gas/aarch64/mpam.d: New test. + * testsuite/gas/aarch64/mpam.s: Input. + +2020-08-12 Nick Clifton <nickc@redhat.com> + + PR 26346 + * doc/c-riscv.texi (RISC-V-Options): Fix typo in the description + of the -mno-csr-check option. + +2020-08-12 Nick Clifton <nickc@redhat.com> + + * po/ru.po: Updated Russian translation. + +2020-08-10 Alex Coplan <alex.coplan@arm.com> + + * config/tc-aarch64.c (parse_sys_reg): Don't assert when parsing + a long system register. + (parse_sys_ins_reg): Likewise. + (sysreg_hash_insert): New. + (md_begin): Use sysreg_hash_insert() to ensure all system + registers are no longer than the maximum length at startup. + * testsuite/gas/aarch64/invalid-sysreg-assert.d: New test. + * testsuite/gas/aarch64/invalid-sysreg-assert.l: Error output. + * testsuite/gas/aarch64/invalid-sysreg-assert.s: Input. + +2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * config/tc-aarch64.c (parse_sys_reg): Call to + aarch64_sys_ins_reg_supported_p instead of + aarch64_sys_reg_supported_p. + (parse_sys_ins_reg): Add aarch64_sys_reg_deprecated_p check. + * testsuite/gas/aarch64/illegal-sysreg-5.d: New test. + * testsuite/gas/aarch64/illegal-sysreg-5.l: New test. + * testsuite/gas/aarch64/sysreg-5.s: New test. + +2020-08-10 Alan Modra <amodra@gmail.com> + + * testsuite/gas/ppc/power8.d, + * testsuite/gas/ppc/power8.s: Add miso. + * testsuite/gas/ppc/power9.d, + * testsuite/gas/ppc/power8.s: Add exser, msgsndu, msgclru. + +2020-08-10 Alan Modra <amodra@gmail.com> + + * testsuite/gas/ppc/power8.d: Update. + * testsuite/gas/ppc/vsx2.d: Update. + +2020-08-10 Alan Modra <amodra@gmail.com> + + * config/tc-ppc.c (md_assemble): Error for lmw, stmw, lswi, lswx, + stswi, or stswx in little-endian mode. + * testsuite/gas/ppc/476.d, + * testsuite/gas/ppc/476.s: Delete lmw, stmw, lswi, lswx, stswi, stswx. + * testsuite/gas/ppc/a2.d, + * testsuite/gas/ppc/a2.s: Move lmw, stmw, lswi, lswx, stswi, stswx.. + * testsuite/gas/ppc/be.d, + * testsuite/gas/ppc/be.s: ..to here, new big-endian only test. + * testsuite/gas/ppc/le_error.d, + * testsuite/gas/ppc/le_error.l: New little-endian test. + * testsuite/gas/ppc/ppc.exp: Run new tests. + +2020-08-07 H.J. Lu <hongjiu.lu@intel.com> + + * read.c (read_a_source_file): Ignore rest of line on overflow + error. + +2020-08-06 Alex Coplan <alex.coplan@arm.com> + + * read.c (read_a_source_file): Use long for local labels, detect + overflow and raise an error for overly-long labels. + * testsuite/gas/all/gas.exp: Add local-label-overflow test. + * testsuite/gas/all/local-label-overflow.d: New test. + * testsuite/gas/all/local-label-overflow.l: Error output. + * testsuite/gas/all/local-label-overflow.s: Input. + +2020-08-04 Christian Groessler <chris@groessler.org> + + * testsuite/gas/z8k/inout.d: Adapt to correct encoding of + "sout/soutb #imm,reg" + +2020-08-04 H.J. Lu <hongjiu.lu@intel.com> + + * NEWS: Mention {disp16} pseudo prefix. + +2020-08-04 H.J. Lu <hongjiu.lu@intel.com> + + * testsuite/gas/i386/x86-64-pseudos.d: Revert an accidental + change. + +2020-08-04 Mark Wielaard <mark@klomp.org> + + * dwarf2dbg.c (out_debug_abbrev): When DWARF2_VERSION >= 4, use + DW_FORM_udata for DW_AT_high_pc. + (out_debug_info): Use emit_leb128_expr for DW_AT_high_pc, when + DWARF2_VERSION >= 4. + * read.c (emit_leb128_exp): No longer static. + * read.h (emit_leb128_exp): Define. + +2020-08-02 Mark Wielaard <mark@klomp.org> + + * dwarf2dbg.c (out_dir_and_file_list): For DWARF5 emit at + least one directory if there is at least one file. Use dirs[1] + if dirs[0] is not set, or if there is no dirs[1] the current + working directory. Use files[1] filename, when files[0] filename + isn't set. + +2020-08-02 Mark Wielaard <mark@klomp.org> + + * dwarf2dbg.c (out_debug_info): Emit unit type and abbrev offset + for DWARF5. + * testsuite/gas/elf/dwarf-4-cu.d: New file. + * testsuite/gas/elf/dwarf-4-cu.s: Likewise. + * testsuite/gas/elf/dwarf-5-cu.d: Likewise. + * testsuite/gas/elf/dwarf-5-cu.s: Likewise. + * testsuite/gas/elf/elf.exp: Run dwarf-4-cu and dwarf-5-cu. + +2020-08-02 Mark Wielaard <mark@klomp.org> + + * doc/as.texi (--gdwarf-[345]): Fix typo. + +2020-08-03 Jozef Lawrynowicz <jozef.l@mittosystems.com> + + * config/tc-msp430.c (OPTION_MOVE_DATA): Remove. + (md_parse_option): Remove case for OPTION_MOVE_DATA. + (md_longopts): Remove "md" entry. + (md_show_usage): Likewise. + +2020-07-30 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26305 + * config/tc-i386.c (_i386_insn::disp_encoding): Add + disp_encoding_16bit. + (parse_insn): Check Prefix_XXX for pseudo prefixes. Handle + {disp16}. + (build_modrm_byte): Handle {disp16}. + (i386_index_check): Check invalid {disp16} and {disp32} pseudo + prefixes. + * doc/c-i386.texi: Update {disp32} documentation and document + {disp16}. + * testsuite/gas/i386/i386.exp: Run x86-64-inval-pseudo. + * testsuite/gas/i386/inval-pseudo.s: Add {disp32}/{disp16} + tests. + * testsuite/gas/i386/pseudos.s: Add {disp8}/{disp32} vmovaps + tests with 128-byte displacement. Add {disp16} tests. + * testsuite/gas/i386/x86-64-pseudos.s: Add {disp8}/{disp32} + vmovaps test. Add (%r13)/(%r13d) tests. + * testsuite/gas/i386/x86-64-inval-pseudo.l: New file. + * testsuite/gas/i386/x86-64-inval-pseudo.s: Likewise. + * testsuite/gas/i386/inval-pseudo.l: Updated. + * testsuite/gas/i386/pseudos.d: Likewise. + * testsuite/gas/i386/x86-64-pseudos.d: Likewise. + +2020-07-30 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + * Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS. + * Makefile.in, doc/Makefile.in: Regenerate. + * configure: Regenerate. + +2020-07-30 H.J. Lu <hongjiu.lu@intel.com> + + * testsuite/gas/elf/dwarf2-3.d:Pass --gdwarf-3 to assembler. + * testsuite/gas/elf/dwarf2-5.d: Likewise. + * testsuite/gas/i386/dw2-compress-3a.d: Likewise. + * testsuite/gas/i386/dw2-compress-3b.d: Likewise. + * testsuite/gas/i386/dw2-compressed-3a.d: Likewise. + * testsuite/gas/i386/dw2-compressed-3b.d: Likewise. + +2020-07-30 Nick Clifton <nickc@redhat.com> + + * as.c (dwarf_level): Initialise to 3 in case this is not set on + the command line. + +2020-07-29 Maciej W. Rozycki <macro@linux-mips.org> + + * testsuite/gas/mips/global-local-symtab-sort-o32.d: New test. + * testsuite/gas/mips/global-local-symtab-sort-o32t.d: New test. + * testsuite/gas/mips/global-local-symtab-sort-n32.d: New test. + * testsuite/gas/mips/global-local-symtab-sort-n32t.d: New test. + * testsuite/gas/mips/global-local-symtab-sort-n64.d: New test. + * testsuite/gas/mips/global-local-symtab-sort-n64t.d: New test. + * testsuite/gas/mips/mips.exp: Run the new tests. + +2020-07-29 Maciej W. Rozycki <macro@linux-mips.org> + + * testsuite/gas/mips/global-local-symtab-o32.d: New test. + * testsuite/gas/mips/global-local-symtab-o32t.d: New test. + * testsuite/gas/mips/global-local-symtab-n32.d: New test. + * testsuite/gas/mips/global-local-symtab-n32t.d: New test. + * testsuite/gas/mips/global-local-symtab-n64.d: New test. + * testsuite/gas/mips/global-local-symtab.s: New test source. + * testsuite/gas/mips/mips.exp: Run the new tests. + +2020-07-28 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26305 + * config/tc-i386.c (build_modrm_byte): Use disp32/disp16 on + (%bp)/(%ebp)/(%rbp) for {disp32}. + * doc/c-i386.texi: Update {disp32} documentation. + * testsuite/gas/i386/pseudos.s: Add (%bp)/(%ebp) tests. + * testsuite/gas/i386/x86-64-pseudos.s: Add (%ebp)/(%rbp) tests. + * testsuite/gas/i386/pseudos.d: Updated. + * testsuite/gas/i386/x86-64-pseudos.d: Likewise. + +2020-07-27 H.J. Lu <hongjiu.lu@intel.com> + + * doc/as.texi: Replace preceeded with preceded. + +2020-07-22 Maciej W. Rozycki <macro@linux-mips.org> + + * testsuite/gas/mips/jal-svr4pic-irix.d: New file. + * testsuite/gas/mips/mips1@jal-svr4pic-irix.d: New file. + * testsuite/gas/mips/mipsr6@jal-svr4pic-irix.d: New file. + * testsuite/gas/mips/micromips@jal-svr4pic-irix.d: New file. + * testsuite/gas/mips/r3000@jal-svr4pic-irix.d: New file. + * testsuite/gas/mips/jal-svr4pic-local-irix.d: New file. + * testsuite/gas/mips/mips1@jal-svr4pic-local-irix.d: New file. + * testsuite/gas/mips/micromips@jal-svr4pic-local-irix.d: New + file. + * testsuite/gas/mips/r3000@jal-svr4pic-local-irix.d: New file. + * testsuite/gas/mips/jal-svr4pic-noreorder-irix.d: New file. + * testsuite/gas/mips/mips1@jal-svr4pic-noreorder-irix.d: New + file. + * testsuite/gas/mips/mipsr6@jal-svr4pic-noreorder-irix.d: New + file. + * testsuite/gas/mips/micromips@jal-svr4pic-noreorder-irix.d: New + file. + * testsuite/gas/mips/r3000@jal-svr4pic-noreorder-irix.d: New + file. + * testsuite/gas/mips/jal-xgot-irix.d: New file. + * testsuite/gas/mips/jalr2-irix.d: New file. + * testsuite/gas/mips/micromips-branch-relax-insn32-pic-irix.d: + New file. + * testsuite/gas/mips/micromips-branch-relax-pic-irix.d: New + file. + * testsuite/gas/mips/mips-abi32-pic2-irix.d: New file. + * testsuite/gas/mips/jal-svr4pic-local.d: Don't exclude + `*-*-irix*' targets. Add source file designator. + * testsuite/gas/mips/mips1@jal-svr4pic-local.d: Don't exclude + `*-*-irix*' targets. + * testsuite/gas/mips/r3000@jal-svr4pic-local.d: Likewise. + * testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise. + * testsuite/gas/mips/jalr2.d: Add name designator. + * testsuite/gas/mips/mips.exp: Use respective IRIX variants for + tests involving the JALR relocation throughout. + +2020-07-22 Maciej W. Rozycki <macro@linux-mips.org> + + * testsuite/gas/mips/mips.exp: Use a helper variable for + IRIX/non-IRIX test selection. + +2020-07-21 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/evex-no-scale-64.d, + testsuite/gas/i386/addr32.d, + testsuite/gas/i386/x86-64-addr32-intel.d, + testsuite/gas/i386/x86-64-addr32.d: Adjust expectations. + +2020-07-21 Cooper Qu <cooper.qu@linux.alibaba.com> + + * config/tc-csky.c (md_begin): Fix tests of arch and mach flags. + +2020-07-21 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/evex-no-scale-32.d, + testsuite/gas/i386/evex-no-scale-64.d: Add #source and #pass. + * testsuite/gas/i386/evex-no-scale-32.s, + testsuite/gas/i386/evex-no-scale-64.s: Rename / fold into ... + * testsuite/gas/i386/evex-no-scale.s: ... this. Use .struct + instead of .section. + * testsuite/gas/i386/i386.exp: Move above tests out of ELF- + specific section. + +2020-07-21 Maciej W. Rozycki <macro@linux-mips.org> + + * config/tc-mips.c (prev_reloc_op_frag): Remove variable. + (my_getSmallExpression): Adjust accordingly. + +2020-07-20 Jan Beulich <jbeulich@suse.com> + + PR gas/4572 + * config/tc-i386.c (i386_comment_chars): Drop TE_I386AIX from + conditional around it. + (md_begin): Insert backslash into operand_chars[] when slash is + a comment character. + * config/tc-i386-intel.c (i386_operator): Recognize \/, \%, and + \* as operators when / may be a comment character. + * testsuite/gas/i386/svr4.s, testsuite/gas/i386/svr4.d: New. + * testsuite/gas/i386/i386.exp: Run new test. + +2020-07-20 Jan Beulich <jbeulich@suse.com> + + PR gas/4572 + * app.c (last_char): Drop TC_ARM conditional around it. + (struct app_save): Drop TC_ARM conditional around last_char. + (app_push, app_pop): Drop TC_ARM conditional from last_char + accesses. + (do_scrub_chars): Likewise. Drop TC_ARM conditional from + backslash-precedes-comment-character check. + +2020-07-20 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (frag_opcode_byte): New. + (output_branch): Emit error when in absolute section. + (output_jump, output_insn): Use frag_opcode_byte. Handle being + in absolute section. + (output_interseg_jump, output_disp, output_imm): Handle being in + absolute section. + * testsuite/gas/i386/sizing.s, + testsuite/gas/i386/sizing32.d, + testsuite/gas/i386/sizing64.d: New. + * testsuite/gas/i386/i386.exp: Run new tests. + +2020-07-20 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/i386.exp: Include *-*-vxworks alongside + is_elf_format as applicable; merely exclude iamcu tests. + +2020-07-19 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26263 + * config/tc-i386.c (i386_validate_fix): Change PLT32 reloc + against section to PC32 reloc. + * testsuite/gas/i386/relax-5.d: Updated. + * testsuite/gas/i386/x86-64-relax-4.d: Likewise. + +2020-07-15 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26237 + * testsuite/gas/i386/evex-no-scale-64.d: Updated. + * testsuite/gas/i386/addr32.d: Likewise. + * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. + * testsuite/gas/i386/x86-64-addr32.d: Likewise. + +2020-07-15 Nick Clifton <nickc@redhat.com> + + * write.c (create_note_reloc): Add desc2_size parameter. Zero out + the addend field of REL relocations. Store the full addend into + the note for REL relocations. + +2020-07-15 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/x86-64-stack.s: Adjust 32-bit push + immediate. + * testsuite/gas/i386/x86-64-stack-intel.d, + testsuite/gas/i386/x86-64-stack-suffix.d, + testsuite/gas/i386/x86-64-stack.d: Adjust expectations. + +2020-07-15 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/disassem.d, + testsuite/gas/i386/ilp32/x86-64-branch.d, + testsuite/gas/i386/intel.d, testsuite/gas/i386/jump16.d, + testsuite/gas/i386/lfence-load.d, testsuite/gas/i386/noreg16.d, + testsuite/gas/i386/noreg32.d, + testsuite/gas/i386/noreg64-rex64.d, + testsuite/gas/i386/noreg64.d, testsuite/gas/i386/notrack.d, + testsuite/gas/i386/opcode.d, + testsuite/gas/i386/solaris/x86-64-branch-2.d, + testsuite/gas/i386/solaris/x86-64-jump.d, + testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d, + testsuite/gas/i386/solaris/x86-64-nop-3.d, + testsuite/gas/i386/solaris/x86-64-nop-4.d, + testsuite/gas/i386/solaris/x86-64-nop-5.d, + testsuite/gas/i386/solaris/x86-64-relax-2.d, + testsuite/gas/i386/solaris/x86-64-relax-3.d, + testsuite/gas/i386/x86-64-align-branch-1a.d, + testsuite/gas/i386/x86-64-align-branch-1b.d, + testsuite/gas/i386/x86-64-align-branch-1c.d, + testsuite/gas/i386/x86-64-align-branch-1d.d, + testsuite/gas/i386/x86-64-align-branch-1e.d, + testsuite/gas/i386/x86-64-align-branch-1f.d, + testsuite/gas/i386/x86-64-align-branch-1g.d, + testsuite/gas/i386/x86-64-align-branch-1h.d, + testsuite/gas/i386/x86-64-align-branch-1i.d, + testsuite/gas/i386/x86-64-align-branch-2a.d, + testsuite/gas/i386/x86-64-align-branch-2b.d, + testsuite/gas/i386/x86-64-align-branch-2c.d, + testsuite/gas/i386/x86-64-align-branch-3.d, + testsuite/gas/i386/x86-64-align-branch-4a.d, + testsuite/gas/i386/x86-64-align-branch-4b.d, + testsuite/gas/i386/x86-64-align-branch-5.d, + testsuite/gas/i386/x86-64-align-branch-6.d, + testsuite/gas/i386/x86-64-branch-2.d, + testsuite/gas/i386/x86-64-branch-3.d, + testsuite/gas/i386/x86-64-branch.d, + testsuite/gas/i386/x86-64-disassem.d, + testsuite/gas/i386/x86-64-disp32.d, + testsuite/gas/i386/x86-64-gotpcrel-no-relax.d, + testsuite/gas/i386/x86-64-gotpcrel.d, + testsuite/gas/i386/x86-64-ifunc.d, + testsuite/gas/i386/x86-64-jump.d, + testsuite/gas/i386/x86-64-lfence-byte.d, + testsuite/gas/i386/x86-64-lfence-indbr-a.d, + testsuite/gas/i386/x86-64-lfence-indbr-b.d, + testsuite/gas/i386/x86-64-lfence-indbr-c.d, + testsuite/gas/i386/x86-64-lfence-load.d, + testsuite/gas/i386/x86-64-lfence-ret-a.d, + testsuite/gas/i386/x86-64-lfence-ret-b.d, + testsuite/gas/i386/x86-64-lfence-ret-c.d, + testsuite/gas/i386/x86-64-lfence-ret-d.d, + testsuite/gas/i386/x86-64-lfence-ret-e.d, + testsuite/gas/i386/x86-64-mpx-add-bnd-prefix.d, + testsuite/gas/i386/x86-64-mpx-branch-1.d, + testsuite/gas/i386/x86-64-mpx.d, + testsuite/gas/i386/x86-64-nop-3.d, + testsuite/gas/i386/x86-64-nop-4.d, + testsuite/gas/i386/x86-64-nop-5.d, + testsuite/gas/i386/x86-64-nops-7.d, + testsuite/gas/i386/x86-64-notrack.d, + testsuite/gas/i386/x86-64-opcode.d, + testsuite/gas/i386/x86-64-relax-2.d, + testsuite/gas/i386/x86-64-relax-3.d, + testsuite/gas/i386/x86-64-relax-4.d, + testsuite/gas/i386/x86-64-rtm.d, + testsuite/gas/i386/x86-64-stack.d, + testsuite/gas/i386/x86-64-unique.d, + testsuite/gas/i386/x86_64-intel.d: Adjust expectations. + +2020-07-14 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26237 + * testsuite/gas/i386/addr32.s: Add tests for 32-bit wrapped around + address. + * testsuite/gas/i386/x86-64-addr32.s: Likewise. + * testsuite/gas/i386/addr32.d: Updated. + * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. + * testsuite/gas/i386/x86-64-addr32.d: Likewise. + * testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise. + * testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise. + +2020-07-14 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/intel.s: Use dr<N> instead of db<N>. + * testsuite/gas/i386/intel-intel.d: Disambiguate name. + * testsuite/gas/i386/intel.d, + testsuite/gas/i386/opcode-intel.d: Adjust expectations. + +2020-07-14 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/prefix.d: Adjust expectations. + +2020-07-14 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/x86-64-avx-intel.d, + testsuite/gas/i386/x86-64-sse4_2-intel.d: Adjust expectations. + +2020-07-14 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/movbe-suffix.d, + testsuite/gas/i386/x86-64-movbe-suffix.d: New. + * testsuite/gas/i386/i386.exp: Run new tests. + +2020-07-14 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/crc32-suffix.d, + testsuite/gas/i386/x86-64-crc32-suffix.d: New. + * testsuite/gas/i386/i386.exp: Run new tests. + * testsuite/gas/i386/arch-10-bdver1.d, + testsuite/gas/i386/arch-10-bdver2.d, + testsuite/gas/i386/arch-10-bdver3.d, + testsuite/gas/i386/arch-10-bdver4.d, + testsuite/gas/i386/arch-10-btver1.d, + testsuite/gas/i386/arch-10-btver2.d, + testsuite/gas/i386/arch-10-lzcnt.d, + testsuite/gas/i386/arch-10-prefetchw.d, + testsuite/gas/i386/arch-10.d, testsuite/gas/i386/arch-2.d, + testsuite/gas/i386/arch-3.d, testsuite/gas/i386/arch-5.d, + testsuite/gas/i386/arch-6.d, testsuite/gas/i386/crc32.d, + testsuite/gas/i386/sse-noavx.d, testsuite/gas/i386/sse4_2.d, + testsuite/gas/i386/x86-64-arch-2-bdver1.d, + testsuite/gas/i386/x86-64-arch-2-bdver2.d, + testsuite/gas/i386/x86-64-arch-2-bdver3.d, + testsuite/gas/i386/x86-64-arch-2-bdver4.d, + testsuite/gas/i386/x86-64-arch-2-btver1.d, + testsuite/gas/i386/x86-64-arch-2-btver2.d, + testsuite/gas/i386/x86-64-arch-2-lzcnt.d, + testsuite/gas/i386/x86-64-arch-2-prefetchw.d, + testsuite/gas/i386/x86-64-arch-2.d, + testsuite/gas/i386/x86-64-crc32.d, + testsuite/gas/i386/x86-64-pseudos.d, + testsuite/gas/i386/x86-64-sse-noavx.d, + testsuite/gas/i386/x86-64-sse4_2.d: Adjust expectations. + +2020-07-14 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/x86-64-pseudos.s: Add empty-REX tests for + ModR/M-encoded byte register cases. + * testsuite/gas/i386/x86-64-pseudos.d, + testsuite/gas/i386/x86-64-reg-intel.d, + testsuite/gas/i386/x86-64-reg.d: Adjust expectations. + +2020-07-14 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/x86-64-pseudos.s: Add empty-REX tests for + not-ModR/M-encoded byte register cases. + * testsuite/gas/i386/x86-64-pseudos.d: Adjust expectations. + +2020-07-14 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/ilp32/x86-64-arch-1.d, + testsuite/gas/i386/ilp32/x86-64-arch-2.d, + testsuite/gas/i386/ilp32/x86-64-avx-intel.d, + testsuite/gas/i386/ilp32/x86-64-avx.d, + testsuite/gas/i386/ilp32/x86-64-crc32-intel.d, + testsuite/gas/i386/ilp32/x86-64-crc32.d, + testsuite/gas/i386/ilp32/x86-64-gotpcrel.d, + testsuite/gas/i386/ilp32/x86-64-ifunc.d, + testsuite/gas/i386/ilp32/x86-64-reg-intel.d, + testsuite/gas/i386/ilp32/x86-64-reg.d, + testsuite/gas/i386/ilp32/x86-64-rep-suffix.d, + testsuite/gas/i386/ilp32/x86-64-sse4_2-intel.d, + testsuite/gas/i386/ilp32/x86-64-sse4_2.d, + testsuite/gas/i386/ilp32/x86-64-stack-intel.d, + testsuite/gas/i386/ilp32/x86-64-stack-suffix.d, + testsuite/gas/i386/ilp32/x86-64-stack.d: Reference parent dir + dump expectations. + +2020-07-13 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (offset_in_range): Remove 32-bit sign + extension. + +2020-07-13 Nick Clifton <nickc@redhat.com> + + * po/fr.po: Updated French translation. + +2020-07-13 Alan Modra <amodra@gmail.com> + + * testsuite/gas/elf/dwarf2-7.d: Remove most xfails. + * testsuite/gas/elf/dwarf2-12.d: Likewise. + * testsuite/gas/elf/dwarf2-13.d: Likewise. + * testsuite/gas/elf/dwarf2-14.d: Likewise. + +2020-07-11 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (output_insn): Check i.xstate to set + GNU_PROPERTY_X86_FEATURE_2_TMM. + * testsuite/gas/i386/i386.exp: Run x86-64-property-7, + x86-64-property-8 and x86-64-property-9. + * testsuite/gas/i386/x86-64-property-7.d: New file. + * testsuite/gas/i386/x86-64-property-7.s: Likewise. + * testsuite/gas/i386/x86-64-property-8.d: Likewise. + * testsuite/gas/i386/x86-64-property-8.s: Likewise. + * testsuite/gas/i386/x86-64-property-9.d: Likewise. + * testsuite/gas/i386/x86-64-property-9.s: Likewise. + +2020-07-10 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (_i386_insn): Remove has_regmmx, has_regxmm, + has_regymm, has_regzmm and has_regtmm. Add xstate. + (md_assemble): Set i.xstate from operand types in instruction + template. + (build_modrm_byte): Updated. + (output_insn): Check i.xstate. + * testsuite/gas/i386/i386.exp: Run property-6 and + x86-64-property-6. + * testsuite/gas/i386/property-6.d: New file. + * testsuite/gas/i386/property-6.s: Updated. + * testsuite/gas/i386/x86-64-property-6.d: Likewise. + +2020-07-10 H.J. Lu <hongjiu.lu@intel.com> + + * testsuite/gas/i386/property-5.d: Correct test name. + +2020-07-10 Lili Cui <lili.cui@intel.com> + + * NEWS: Mention support for Intel AMX instructions. + * config/tc-i386.c (i386_error): Add invalid_sib_address. + (cpu_arch): Add .amx_int8, .amx_bf16 and .amx_tile. + (cpu_noarch): Add noamx_int8, noamx_bf16 and noamx_tile. + (match_simd_size): Add tmmword check. + (operand_type_match): Add tmmword. + (type_names): Add rTMM. + (i386_error): Add invalid_tmm_register_set. + (check_VecOperands): Handle invalid_sib_address and + invalid_tmm_register_set. + (match_template): Handle invalid_sib_address. + (build_modrm_byte): Handle non-vector SIB and zmmword. + (i386_index_check): Disallow RegIP for non-vector SIB. + (check_register): Handle zmmword. + * doc/c-i386.texi: Document amx_int8, amx_bf16 and amx_tile. + * testsuite/gas/i386/i386.exp: Add AMX new tests. + * testsuite/gas/i386/intel-regs.d: Add tmm. + * testsuite/gas/i386/intel-regs.s: Add tmm. + * testsuite/gas/i386/x86-64-amx-intel.d: New. + * testsuite/gas/i386/x86-64-amx-inval.l: New. + * testsuite/gas/i386/x86-64-amx-inval.s: New. + * testsuite/gas/i386/x86-64-amx.d: New. + * testsuite/gas/i386/x86-64-amx.s: New. + * testsuite/gas/i386/x86-64-amx-bad.d: New. + * testsuite/gas/i386/x86-64-amx-bad.s: New. + +2020-07-10 Tom de Vries <tdevries@suse.de> + + * testsuite/gas/elf/dwarf2-11.d: Update expected output from + readelf's line table decoding. + * testsuite/gas/elf/dwarf2-12.d: Likewise. + * testsuite/gas/elf/dwarf2-13.d: Likewise. + * testsuite/gas/elf/dwarf2-14.d: Likewise. + * testsuite/gas/elf/dwarf2-15.d: Likewise. + * testsuite/gas/elf/dwarf2-16.d: Likewise. + * testsuite/gas/elf/dwarf2-17.d: Likewise. + * testsuite/gas/elf/dwarf2-18.d: Likewise. + * testsuite/gas/elf/dwarf2-19.d: Likewise. + * testsuite/gas/elf/dwarf2-5.d: Likewise. + * testsuite/gas/elf/dwarf2-6.d: Likewise. + * testsuite/gas/elf/dwarf2-7.d: Likewise. + +2020-07-09 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (output_insn): Set YMM/ZMM features for + VEX/EVEX vector instructions. + * testsuite/gas/i386/property-4.d: New file. + * testsuite/gas/i386/property-4.s: Likewise. + * testsuite/gas/i386/property-5.d: Likewise. + * testsuite/gas/i386/property-5.s: Likewise. + * testsuite/gas/i386/x86-64-property-4.d: Likewise. + * testsuite/gas/i386/x86-64-property-5.d: Likewise. + +2020-07-09 H.J. Lu <hongjiu.lu@intel.com> + + * NEWS: Mention --enable-x86-used-note. + * configure.ac: Configure with --enable-x86-used-note by default + for Linux/x86. + * configure: Regenerated. + +2020-07-09 Alan Modra <amodra@gmail.com> + + * config/obj-coff.h: Remove TE_PE support. + * config/tc-ppc.c: Likewise. + * config/tc-ppc.h: Likewise. + * configure.tgt: Remove powerpc PE and powerpc lynxos. + * testsuite/gas/cfi/cfi.exp (cfi-common-6): Remove powerpc PE + condition. + * testsuite/gas/macros/macros.exp: Don't xfail powerpc PE. + +2020-07-08 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/fma4-lig.d, testsuite/gas/i386/xop-lig.d: + New. + * testsuite/gas/i386/i386.exp: Run new tests. + +2020-07-07 Claudiu Zissulescu <claziss@synopsys.com> + + * config/tc-arc.c (find_opcode_match): Add error messages. + * testsuite/gas/arc/add_s-err.s: Update test. + * testsuite/gas/arc/asm-errors.err: Likewise. + * testsuite/gas/arc/cpu-em-err.s: Likewise. + * testsuite/gas/arc/hregs-err.s: Likewise. + * testsuite/gas/arc/warn.s: Likewise. + +2020-07-07 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26212 + * doc/c-i386.texi: Remove an incorrect AVX2 entry. + +2020-07-07 Alan Modra <amodra@gmail.com> + + * testsuite/gas/all/gas.exp: Use is_xcoff_format. + * testsuite/gas/ppc/ppc.exp: Likewise. + * testsuite/gas/all/weakref1l.d: Likewise. + +2020-07-07 Nick Clifton <nickc@redhat.com> + + * testsuite/gas/arm/cde-missing-fp.l: Fix spelling mistake in + expected output. + +2020-07-06 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/x86-64-avx512bw-wig1.d, + testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d, + testsuite/gas/i386/x86-64-evex-wig1.d, + testsuite/gas/i386/x86-64-evex-wig1-intel.d: Adjust + expectations. + +2020-07-06 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/avx512f-opts.s: Add EVEX movq tests. + * testsuite/gas/i386/x86-64-avx512f-opts.s: Add blank line. + * testsuite/gas/i386/avx512f-opts-intel.d, + testsuite/gas/i386/avx512f-opts.d + testsuite/gas/i386/x86-64-avx512f-opts-intel.d + testsuite/gas/i386/x86-64-avx512f-opts.d: Adjust expectations. + +2020-07-06 Yuri Chornoivan <yurchor@ukr.net> + + PR 26204 + * config/tc-arm.c: Fix spelling mistake. + * config/tc-riscv.c: Likewise. + * config/tc-z80.c: Likewise. + * po/gas.pot: Regenerate. + +2020-07-06 Nick Clifton <nickc@redhat.com> + + * po/uk.po: Updated Ukranian translation. + +2020-07-04 Nick Clifton <nickc@redhat.com> + + * configure: Regenerate. + * po/gas.pot: Regenerate. + +2020-07-04 Nick Clifton <nickc@redhat.com> + + * version.m4: Change version number to 2.35.50. + * configure: Regenerate. + * po/bfd.pot: Regenerate. + +2020-07-04 Nick Clifton <nickc@redhat.com> + + Binutils 2.35 branch created. + +2020-07-03 Alan Modra <amodra@gmail.com> + + PR 26028 + * testsuite/gas/ia64/unwind-ilp32.d: Add -T to readelf options. + +2020-07-02 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (build_modrm_byte): Check vexswapsources to + swap two source operands. + +2020-07-02 Nick Clifton <nickc@redhat.com> + + * testsuite/gas/all/fill-1.d: Skip for MeP targets. + +2020-07-02 Alex Coplan <alex.coplan@arm.com> + + * config/tc-aarch64.c (reg_name_p): Fix cast so that we don't + segfault on negative chars. + * testsuite/gas/aarch64/reglike-label-unicode-segv.d: New test. + * testsuite/gas/aarch64/reglike-label-unicode-segv.s: Input. + +2020-07-02 Nick Clifton <nickc@redhat.com> + + PR 26028 + * testsuite/gas/ia64/group-2.d: Add -T option to readelf + command line. + * testsuite/gas/ia64/unwind.d: Likewise. + * testsuite/gas/mmix/bspec-1.d: Likewise. + * testsuite/gas/mmix/bspec-2.d: Likewise. + * testsuite/gas/mmix/comment-1.d: Likewise. + * testsuite/gas/tic6x/scomm-directive-4.d: Likewise. + +2020-07-01 Alan Modra <amodra@gmail.com> + + * config/tc-xc16x.c (md_apply_fix): Add FIXME. + +2020-07-01 Alan Modra <amodra@gmail.com> + + * testsuite/gas/all/eqv-dot.d: xfail targets that set linkrelax + in data sections, and mep. + +2020-06-30 H.J. Lu <hongjiu.lu@intel.com> + + * NEWS: Mention x86 NaCl target support removal. + * config/tc-i386.c: Remove x86 NaCl target support. + * config/tc-i386.h: Likewise. + * configure.tgt: Likewise. + * testsuite/gas/i386/i386.exp: Likewise. + * testsuite/gas/i386/iamcu-1.d: Likewise. + * testsuite/gas/i386/iamcu-2.d: Likewise. + * testsuite/gas/i386/iamcu-3.d: Likewise. + * testsuite/gas/i386/iamcu-4.d: Likewise. + * testsuite/gas/i386/iamcu-5.d: Likewise. + * testsuite/gas/i386/k1om.d: Likewise. + * testsuite/gas/i386/l1om.d: Likewise. + +2020-06-30 Nelson Chu <nelson.chu@sifive.com> + + * config/tc-riscv.c (riscv_csr_class_check): Removed. Move the + checking into riscv_csr_address. + (riscv_csr_version_check): Likewise. + (riscv_csr_address): New function. Return the suitable CSR address + after checking the ISA dependency and versions. Issue warnings if + we find any conflict and -mcsr-check is set. CSR_CLASS_F and + CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the + priv spec versions for them. + (reg_csr_lookup_internal): Call riscv_csr_address to find the + suitable CSR address. + * testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11. + * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise. + * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise. + * testsuite/gas/riscv/priv-reg-fail-fext.l: We don't care the + priv spec warnings here. These warnings are added by accident. + Remove them and only focus on the ISA dependency warnings. + * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. + * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. + * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since + dscratch0 and dscratch1 are regarded as the unprivileged CSR rather + than the privileged ones. + * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise. + * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. + * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. + * testsuite/gas/riscv/priv-reg.s: Likewise. Add missing debug CSR. + * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise. + * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise. + * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise. + * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise. + * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. + * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. + +2020-06-29 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (build_vex_prefix): Support VEX base opcode + length > 1. + (md_assemble): Don't process ImmExt without operands. + +2020-06-29 Hans-Peter Nilsson <hp@bitrange.com> + + PR gas/25331 + * config/tc-mmix.c (md_assemble) <fixup for + BFD_RELOC_MMIX_BASE_PLUS_OFFSET>: This fixup affects 1 byte, not 8. + Also, set its fx_no_overflow. + (md_convert_frag) <case ENCODE_RELAX (STATE_PUSHJSTUB, STATE_ZERO)>: + Similarly this fixup affects 4 bytes, not 8 and needs its + fx_no_overflow set. + * config/tc-mmix.h (TC_FX_SIZE_SLACK): Don't define. + * testsuite/gas/mmix/pr25331.d, testsuite/gas/mmix/pr25331.s: New test. + +2020-06-29 Alan Modra <amodra@gmail.com> + + * config/tc-s12z.c: Use C style comments. + * config/tc-z80.c: Likewise. + * config/tc-xtensa.c (emit_ld_r_n): Remove commented out code. + +2020-06-26 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (md_assemble): Process ImmExt without + operands. + +2020-06-26 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (check_VecOperands): Replace vecsib with sib. + Replace VecSIB128, VecSIB256 and VecSIB512 with VECSIB128, + VECSIB256 and VECSIB512, respectively. + (build_modrm_byte): Replace vecsib with sib. + +2020-06-26 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/nop-1-suffix.d: New. + * testsuite/gas/i386/i386.exp: Run new test. + +2020-06-26 Pat Bernardi <bernardi@adacore.com> + + * config/tc-m68k.c (m68k_elf_gnu_attribute): New function. + (md_pseudo_table): Handle "gnu_attribute". + * doc/as.texi: Document GNU attribute for M68K. + +2020-06-25 Nick Clifton <nickc@redhat.com> + + PR 26141 + * config/tc-arm.c (arm_force_relocation): Force resolution of + BFD_RELOC_THUMB_PCREL_BRANCH12 relocations. + * testsuite/gas/arm/plt-1.d: Adjust expected disassembly. + +2020-06-25 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (md_assemble): Move call to process_immext() + ... + (process_operands): ... here. + +2020-06-25 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (process_suffix): Skip ambiguous operand size + diagnostic when there is a sizing prefix. Switch to word/dword/ + qword encoding when there is a sizing prefix and no (explicit or + derived) suffix. + (update_imm): Handle presence of a sizing prefix. + * testsuite/gas/i386/noreg16-data32.d, + testsuite/gas/i386/noreg32-data16.d, + testsuite/gas/i386/noreg32-data16.e, + testsuite/gas/i386/noreg64-data16.d, + testsuite/gas/i386/noreg64-data16.e, + testsuite/gas/i386/noreg64-rex64.d: New. + * testsuite/gas/i386/i386.exp: Run new tests. + * testsuite/gas/i386/noreg32.s, testsuite/gas/i386/noreg64.s: + Introduce and use pfx* macros. + * testsuite/gas/i386/noreg16.s: Likewise. Replace 32-bit + addressing. + * testsuite/gas/i386/noreg16.d: Adjust expectations. + +2020-06-25 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/avx-16bit.d, + testsuite/gas/i386/avx-scalar.d, testsuite/gas/i386/avx.d, + testsuite/gas/i386/avx512f-16bit.d, + testsuite/gas/i386/avx512f.d, + testsuite/gas/i386/evex-lig256.d, + testsuite/gas/i386/evex-lig512.d + testsuite/gas/i386/evex-wig1.d, testsuite/gas/i386/katmai.d, + testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d, + testsuite/gas/i386/ptwrite.d, testsuite/gas/i386/simd.d, + testsuite/gas/i386/sse2-16bit.d, + testsuite/gas/i386/sse2.d, testsuite/gas/i386/sse2avx.d: Adjust + expectations. + +2020-06-25 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (md_assemble): Also reject explicit REX + prefixes with VEX and alike encoded insns. Zap consumed bits + from i.rex. + (output_insn): Don't ignore REX prefix for VEX and alike + encodings; abort() instead if encountered. + * testsuite/gas/i386/x86-64-pseudos.s: Move REX-with-VEX cases + ... + * testsuite/gas/i386/x86-64-pseudos-bad.s: ... here. + * testsuite/gas/i386/x86-64-pseudos.d, + testsuite/gas/i386/x86-64-pseudos-bad.l: Adjust expectations. + +2020-06-25 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (process_operands): Translate explicit REX + prefix into i.rex for SSE2AVX templates. + (set_rex_vrex): New helper. + (build_modrm_byte): Use it. + * testsuite/gas/i386/x86-64-sse2avx.s: Add cases with explict + REX prefixes. + * testsuite/gas/i386/x86-64-sse2avx.d: Adjust expectations. + +2020-06-25 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (cpu_flags_match): Only match SSE2AVX + templates when there's no data size prefix. + (md_assemble): Reject data size prefix also for legacy encoded + SIMD templates. + * testsuite/gas/i386/prefix32.s, testsuite/gas/i386/prefix64.s: + Uncomment previously not working line. + * testsuite/gas/i386/sse2avx.s: Add ldmxcsr/stmxcsr cases with + data16 prefix. + * testsuite/gas/i386/prefix32.l, testsuite/gas/i386/prefix64.l, + testsuite/gas/i386/sse2avx.d: Adjust expectations. + +2020-06-25 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (build_evex_prefix): Drop early setting of + vec_length. + +2020-06-23 Nelson Chu <nelson.chu@sifive.com> + + * config/tc-riscv.c (explicit_priv_attr): Rename explicit_csr to + explicit_priv_attr. It used to indicate CSR or priv instructions are + explictly used. + (riscv_is_priv_insn): Return True if it is a privileged instruction. + (riscv_ip): Call riscv_is_priv_insn to check whether the instruction + is privileged or not. If it is, then set explicit_priv_attr to TRUE. + (riscv_write_out_attrs): Clarification of when to generate the elf + priv spec attributes. + * testsuite/gas/riscv/attribute-11.s: Add comments. + * testsuite/gas/riscv/attribute-14.s: New testcase. Use symbol + `priv_insn_<n>` to decide which priv instruction is expected to used. + (<n> is a to e.) + * testsuite/gas/riscv/attribute-14a.d: Likewise. + * testsuite/gas/riscv/attribute-14b.d: Likewise. + * testsuite/gas/riscv/attribute-14c.d: Likewise. + * testsuite/gas/riscv/attribute-14d.d: Likewise. + * testsuite/gas/riscv/attribute-14e.d: Likewise. + +2020-06-22 Nelson Chu <nelson.chu@sifive.com> + + * config/tc-riscv.c (buf_size, buf): Remove the unused variables. + (riscv_set_default_priv_spec): Get the priv spec version from the + priv spec attributes by riscv_get_priv_spec_class_from_numbers. + +2020-06-20 Alan Modra <amodra@gmail.com> + + * configure.tgt: Set bfd_gas for all SH targets. + +2020-06-18 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/arch-13.s: Add alternative VMGEXIT case. + * testsuite/gas/i386/arch-13.d: Extend -march=. Adjust + expectations. + +2020-06-16 Lili Cui <lili.cui@intel.com> + + * config/tc-i386.c (cpu_arch): Correct noavx512_vp2intersect + cpu_arch to CPU_ANY_VP2INTERSECT_FLAGS. + * doc/c-i386.texi: Add avx512_vp2intersect. + +2020-06-16 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (md_assemble): Drop SSE4a from SSE check + conditional. + * testsuite/gas/i386/sse-check.s: Adjust comment. + * testsuite/gas/i386/sse-check-error.l, + testsuite/gas/i386/sse-check-warn.e, + testsuite/gas/i386/x86-64-sse-check-error.l: Adjust + expectations. + +2020-06-16 Alan Modra <amodra@gmail.com> + + * config/tc-tic30.h: Remove OBJ_AOUT support. + * configure.tgt: Delete tic30-*-*aout* entry. + +2020-06-15 Max Filippov <jcmvbkbc@gmail.com> + + * config/tc-xtensa.c (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New + macros. + (elf32xtensa_abi): New declaration. + (option_abi_windowed, option_abi_call0): New enum constants. + (md_longopts): Add entries for --abi-windowed and --abi-call0. + (md_parse_option): Add handlers for --abi-windowed and + --abi-call0. + (xtensa_add_config_info): Use xtensa_abi_choice instead of + XSHAL_ABI to format ABI tag. + * doc/as.texi (Target Xtensa options): Add --abi-windowed and + --abi-call0 to the list of options. + * doc/c-xtensa.texi: Add description for options --abi-windowed + and --abi-call0. + * testsuite/gas/xtensa/abi-call0.d: New test definition. + * testsuite/gas/xtensa/abi-windowed.d: New test definition. + * testsuite/gas/xtensa/abi.s: New test source. + +2020-06-14 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26115 + * testsuite/gas/i386/tsxldtrk.d: Replace xsuspldtrk with + xsusldtrk. + * testsuite/gas/i386/tsxldtrk.s: Likewise. + * testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise. + * testsuite/gas/i386/x86-64-tsxldtrk.s: Likewise. + +2020-06-12 Nelson Chu <nelson.chu@sifive.com> + + * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Removed. + * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise. + * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise. + +2020-06-09 Seth Girvan <snth@snthhacks.com> + + * doc/c-avr.texi: Improve wording. + +2020-06-09 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/x86-64-pseudos-bad.s, + testsuite/gas/i386/x86-64-pseudos-bad.l: New. + +2020-06-09 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/prefix.s: Add bogus prefix-with-VEX/EVEX + encoding tests. + * testsuite/gas/i386/prefix.d: Adjust expectations. + +2020-06-09 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/prefix.s: Add bogus REP / EVEX.W prefix + with VEX/EVEX encoding tests. + * testsuite/gas/i386/prefix.d: Adjust expectations. + +2020-06-09 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (process_suffix): Restrict defaulting to 'q' + suffix. + * testsuite/gas/i386/noreg64.s: Add lcall/ljmp cases. + * testsuite/gas/i386/noreg64.d: Adjust expectations. + * testsuite/gas/i386/noreg-intel64.d, + testsuite/gas/i386/noreg-intel64.l, + testsuite/gas/i386/noreg-intel64.s: New. + * testsuite/gas/i386/i386.exp: Run new tests. + +2020-06-09 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (vex_encoding_error): New enumerator. + (VEX_check_operands): Rename to VEX_check_encoding. Check + for vex_encoding_error. Move Imm4 handling ... + (check_VecOperands): ... here. + (match_template): Call VEX_check_encoding when there are no + operands. Split construct calling check_VecOperands and + VEX_check_encoding (when there are operands). + (check_register): Don't blindly set vex_encoding_evex. + * testsuite/gas/i386/pseudos-bad.s, + testsuite/gas/i386/pseudos-bad.l: New. + * testsuite/gas/i386/i386.exp: Run new test. + * testsuite/gas/i386/xmmhi64.s: Drop {vex2}. + +2020-06-08 Alex Coplan <alex.coplan@arm.com> + + * config/tc-arm.c (insns): Add dfb. + * testsuite/gas/arm/dfb.d: New test. + * testsuite/gas/arm/dfb.s: Input for test. + +2020-06-08 Nick Clifton <nickc@redhat.com> + + * testsuite/gas/cfi/cfi-i386-2.d: Skip for PE based targets. + +2020-06-08 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (pi): Add checks for RegMask and RegBND. + +2020-06-08 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (check_byte_reg): Drop dead conditional + around as_bad(). + +2020-06-08 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (check_register): Split RegTR handling, to + fail recognition also in 64-bit mode as well as with i586 or + i686 explicitly enabled. + * testsuite/gas/i386/x86_64.s: Add insns referencing tr<N>. + * testsuite/gas/i386/x86_64-intel.d, + testsuite/gas/i386/x86_64.d: Adjust expectations. + +2020-06-08 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/cfi/cfi-i386-2.d: Adjust expectations. + * testsuite/gas/cfi/cfi.exp: Run this test. + +2020-06-08 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (parse_real_register): Add allow_pseudo_reg + check to %st(N) parsing logic. + * testsuite/gas/cfi/cfi-i386.s: Set "generic32" arch. + +2020-06-08 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (bad_reg): New. + (check_VecOperations, i386_att_operand, i386_parse_name): Check + for it. + (check_register): New, broken out from ... + (parse_real_register): ... here. Call it. + (parse_register): Call it, and error upon failure. + * testsuite/gas/i386/equ-bad.s, testsuite/gas/i386/equ-bad.l, + testsuite/gas/i386/x86-64-equ-bad.s, + testsuite/gas/i386/x86-64-equ-bad.l: New. + * testsuite/gas/i386/i386.exp: Run new tests. + +2020-06-06 Alan Modra <amodra@gmail.com> + + * config/tc-ppc.c (md_show_usage): Mention -mpower10 and -mpwr10. + * doc/c-ppc.texi: Likewise. + +2020-06-06 Alan Modra <amodra@gmail.com> + + * config/tc-ppc.c: Update throughout for reloc renaming. + +2020-06-05 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/tc-bpf.c (md_apply_fix): Avoid GCC 10 warning + stringop-overflow. + +2020-06-05 Nelson Chu <nelson.chu@sifive.com> + + * config/tc-riscv.c (explicit_csr): New static boolean. + Used to indicate CSR are explictly used. + (riscv_ip): Set explicit_csr to TRUE if any CSR is used. + (riscv_write_out_attrs): If we already have set elf priv + attributes, then generate them. Otherwise, don't generate + them when no CSR are used. + * testsuite/gas/riscv/attribute-01.d: Remove the priv attributes. + * testsuite/gas/riscv/attribute-02.d: Likewise. + * testsuite/gas/riscv/attribute-03.d: Likewise. + * testsuite/gas/riscv/attribute-04.d: Likewise. + * testsuite/gas/riscv/attribute-05.d: Likewise. + * testsuite/gas/riscv/attribute-06.d: Likewise. + * testsuite/gas/riscv/attribute-07.d: Likewise. + * testsuite/gas/riscv/attribute-08.d: Likewise. + * testsuite/gas/riscv/attribute-09.d: Likewise. + * testsuite/gas/riscv/attribute-10.d: Likewise. + * testsuite/gas/riscv/attribute-unknown.d: Likewise. + * testsuite/gas/riscv/attribute-11.s: New testcase. + * testsuite/gas/riscv/attribute-11.d: New testcase. The CSR is + used, so we should output the ELF priv attributes. + * testsuite/gas/riscv/attribute-12.d: New testcase. The CSR is + used, so output the priv attributes according to the -mpriv-spec. + * testsuite/gas/riscv/attribute-13.d: New testcase. The CSR isn't + used, so ignore the -mpriv-spec setting. + +2020-06-04 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-ip2k. (ip2k_apply_fix): Pass endianness to + cgen_get_insn_value. + * config/tc-xstormy16.c (xstormy16_md_apply_fix): Pass + endianness to cgen_get_insn_value and cgen_put_insn_value. + +2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/tc-bpf.c (md_apply_fix): Simplify and avoid using + cgen_put_insn_value. + +2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to + bpf_cgen_cpu_open. + (md_assemble): Remove no longer needed hack. + +2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> + + * cgen.c (gas_cgen_finish_insn): Pass the endianness to + cgen_put_insn_value. + (gas_cgen_md_apply_fix): Likewise. + (gas_cgen_md_apply_fix): Likewise. + * config/tc-bpf.c (md_apply_fix): Pass data endianness to + cgen_put_insn_value. + * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to + cgen_put_insn_value. + +2020-06-04 Alan Modra <amodra@gmail.com> + + * testsuite/config/default.exp: Remove global directive outside + proc body. + * testsuite/gas/mep/complex-relocs.exp: Likewise. + * testsuite/gas/microblaze/relax_size.exp: Likewise. + * testsuite/gas/microblaze/reloc_sym.exp: Likewise. + * testsuite/gas/mt/relocs.exp: Likewise. + * testsuite/gas/rx/rx.exp: Likewise. + +2020-06-03 Stephen Casner <casner@acm.org> + + * doc/c-riscv.texi (RISC-V-Options): Fix non-ASCII apostrophe. + +2020-06-02 Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> + Jim Wilson <jimw@sifive.com> + + PR 26051 + * doc/c-riscv.texi (RISC-V-Formats): Add missing I format using + simm12(rs1). Correct S format to use simm12(rs1). Drop SB and B + formats using simm12(rs1). Correct SB and B to use rs1 and rs2. + Move B before SB. Move J before UJ. + +2020-06-01 Alex Coplan <alex.coplan@arm.com> + + * write.c (relax_segment): Fix handling of negative offset when + relaxing an rs_org frag. + * testsuite/gas/aarch64/org-neg.d: New test. + * testsuite/gas/aarch64/org-neg.l: Error output for test. + * testsuite/gas/aarch64/org-neg.s: Input for test. + * testsuite/gas/arm/org-neg.d: New test. + * testsuite/gas/arm/org-neg.l: Error output for test. + * testsuite/gas/arm/org-neg.s: Input for test. + +2020-05-28 Stephen Casner <casner@acm.org> + + Fix unexpected failures in gas testsuite for pdp11-aout target. + These are caused by the PDP11's mix of little-endian octets in + shorts but shorts in big endian order for long or quad. + + * config/tc-pdp11.c (md_number_to_chars): Implement .quad + * testsuite/gas/all/gas.exp: Select alternate test scripts for + pdp11, skip octa test completely. + * testsuite/gas/all/eqv-dot-pdp11.s: Identical to eqv-dot.s + * testsuite/gas/all/eqv-dot-pdp11.d: Match different octet order. + * testsuite/gas/all/cond-pdp11.l: Match different octet order. + +2020-05-28 Alex Coplan <alex.coplan@arm.com> + + * frags.c (frag_grow): Fix comment. + +2020-05-27 Stephen Casner <casner@acm.org> + + PR gas/26001 + * config/tc-pdp11.c (parse_reg): Distinguish register names from + symbols that begin with a register name. + * testsuite/gas/pdp11/pdp11.exp: Add test of such symbols. + * testsuite/gas/pdp11/pr26001.s: Likewise. + * testsuite/gas/pdp11/pr26001.d: Likewise. + +2020-05-27 Simon Cook <simon.cook@embecosm.com> + + * config/tc-riscv.c (riscv_init_csr_hash): NULL initilize next + pointer when creating struct riscv_csr_extra. + +2020-05-26 H.J. Lu <hongjiu.lu@intel.com> + + * testsuite/gas/i386/align-branch-9.d: Updated for PECOFF. + * testsuite/gas/i386/inval-avx512f.s: Add .p2align for PECOFF. + * testsuite/gas/i386/inval-avx512f.l: Updated. + +2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> + + * testsuite/gas/s390/zarch-z13.d: Add regexp checks for vector + load/store instruction variants with alignment hints. + * testsuite/gas/s390/zarch-z13.s: Emit new vector load/store + instruction variants with alignment hints. + +2020-05-26 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26044 + * config/tc-xgate.c (md_apply_fix): Check BFD_RELOC_XGATE_PCREL_X + instead of R_XGATE_PCREL_X. + (xgate_parse_operand): Replace R_XGATE_PCREL_X with + BFD_RELOC_XGATE_PCREL_X. + +2020-05-26 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26044 + * config/tc-visium.c (md_convert_frag): Replace fragP->fr_literal + with &fragP->fr_literal[0]. + +2020-05-26 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26044 + * config/tc-vax.c (md_estimate_size_before_relax): Replace + fragP->fr_literal with &fragP->fr_literal[0]. + (md_convert_frag): Likewise. + +2020-05-26 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26044 + * config/tc-v850.c (md_convert_frag): Replace fragP->fr_literal + with &fragP->fr_literal[0]. + +2020-05-26 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26044 + * config/tc-crx.c (getreg_image): Change argument type to int. + (md_convert_frag): Replace fragP->fr_literal with + &fragP->fr_literal[0]. + +2020-05-26 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26044 + * onfig/tc-score.c (s3_do_macro_bcmp): Replace overlapping + sprintf with memmove. + +2020-05-25 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-mcore.c (md_convert_frag): Replace fragP->fr_literal + with &fragP->fr_literal[0]. + +2020-05-25 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/26041 + * config/tc-cr16.c (md_assemble): Use memmove to concatenate + 2 overlapping strings. + +2020-05-25 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-cr16.c (md_convert_frag): Replace fragP->fr_literal + with &fragP->fr_literal[0]. + +2020-05-25 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-csky.c (md_convert_frag): Replace fragp->fr_literal + with &fragp->fr_literal[0]. + * config/tc-microblaze.c (md_apply_fix): Likewise. + * config/tc-sh.c (md_convert_frag): Likewise. + +2020-05-24 Jim Wilson <jimw@sifive.com> + + PR 26025 + * config/tc-riscv.c (riscv_pre_output_hook): Change s type from const + asection to segT. New locals seg and subseg. Call subseg_set before + fix_new_exp. Call subseg_set after loop to restore original values. + +2020-05-21 Alan Modra <amodra@gmail.com> + + * atof-generic.c: Replace "if (x) free (x)" with "free (x)" + throughout. + * config/obj-elf.c: Likewise. + * config/tc-aarch64.c: Likewise. + * config/tc-arm.c: Likewise. + * config/tc-m68k.c: Likewise. + * config/tc-nios2.c: Likewise. + * config/tc-tic30.c: Likewise. + * ecoff.c: Likewise. + * read.c: Likewise. + * stabs.c: Likewise. + * symbols.c: Likewise. + * testsuite/gas/all/test-gen.c: Likewise. + +2020-05-20 Nelson Chu <nelson.chu@sifive.com> + + * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated. + * config/tc-riscv.c (default_arch_with_ext, default_isa_spec): + Static variables which are used to set the ISA extensions. You can + use -march (or ELF build attributes) and -misa-spec to set them, + respectively. + (ext_version_hash): The hash table used to handle the extensions + with versions. + (init_ext_version_hash): Initialize the ext_version_hash according + to riscv_ext_version_table. + (riscv_get_default_ext_version): The callback function of + riscv_parse_subset_t. According to the choosed ISA spec, + get the default version for the specific extension. + (riscv_set_arch): Set the callback function. + (enum options, struct option md_longopts): Add new option -misa-spec. + (md_parse_option): Do not call riscv_set_arch for -march. We will + call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class + to set default_isa_spec class. + (riscv_after_parse_args): Call init_ext_version_hash to initialize the + ext_version_hash, and then call riscv_set_arch to set the architecture + with versions according to default_arch_with_ext. + * testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for + x extensions. + * testsuite/gas/riscv/attribute-03.d: Likewise. + * testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we + already set it's version to 2p1 by march, so no need to use the default + 2p2 version. For m-ext, we do not set the version by -march and ELF arch + attribute, so set the default 2p0 to it. For zicsr, it is not defined in + ISA spec 2p2, so set 0p0 to it. + * testsuite/gas/riscv/attribute-10.d: New testcase. The version of + zicsr is 2p0 according to ISA spec 20191213. + * config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT) + (DEFAULT_RISCV_ISA_SPEC): Default configure option settings. + You can set them by configure options --with-arch and + --with-isa-spec, respectively. + (riscv_set_default_isa_spec): New function used to set the + default ISA spec. + (md_parse_option): Call riscv_set_default_isa_spec rather than + call riscv_get_isa_spec_class directly. + (riscv_after_parse_args): If the -isa-spec is not set, then we + set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by + calling riscv_set_default_isa_spec. + * testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since + the --with-isa-spec may be set to different ISA spec. + * testsuite/gas/riscv/attribute-02.d: Likewise. + * testsuite/gas/riscv/attribute-03.d: Likewise. + * testsuite/gas/riscv/attribute-04.d: Likewise. + * testsuite/gas/riscv/attribute-05.d: Likewise. + * testsuite/gas/riscv/attribute-06.d: Likewise. + * testsuite/gas/riscv/attribute-07.d: Likewise. + * configure.ac: Add configure options, --with-arch and + --with-isa-spec. + * configure: Regenerated. + * config.in: Regenerated. + * config/tc-riscv.c (default_priv_spec): Static variable which is + used to check if the CSR is valid for the chosen privilege spec. You + can use -mpriv-spec to set it. + (enum reg_class): We now get the CSR address from csr_extra_hash rather + than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX. + (riscv_init_csr_hashes): Only need to initialize one hash table + csr_extra_hash. + (riscv_csr_class_check): Change the return type to void. Don't check + the ISA dependency if -mcsr-check isn't set. + (riscv_csr_version_check): New function. Check and find the CSR address + from csr_extra_hash, according to default_priv_spec. Report warning + for the invalid CSR if -mcsr-check is set. + (reg_csr_lookup_internal): Updated. + (reg_lookup_internal): Likewise. + (md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed. + (enum options, struct option md_longopts): Add new GAS option -mpriv-spec. + (md_parse_option): Call riscv_set_default_priv_version to set + default_priv_spec. + (riscv_after_parse_args): If -mpriv-spec isn't set, then set the default + privilege spec to the newest one. + (enum riscv_csr_class, struct riscv_csr_extra): Move them to + include/opcode/riscv.h. + * testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want + to check the ISA dependency for CSR, so fix the spec version by adding + -mpriv-spec=1.11. + * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some + version warnings for the test case. + * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise. + * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. + * testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise. + * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise. + * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. + * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case. + Check whether the CSR is valid when privilege version 1.9 is choosed. + * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise. + * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case. + Check whether the CSR is valid when privilege version 1.9.1 is choosed. + * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise. + * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case. + Check whether the CSR is valid when privilege version 1.10 is choosed. + * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. + * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case. + Check whether the CSR is valid when privilege version 1.11 is choosed. + * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. + * config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option + setting. You can set it by configure option --with-priv-spec. + (riscv_set_default_priv_spec): New function used to set the default + privilege spec. + (md_parse_option): Call riscv_set_default_priv_spec rather than + call riscv_get_priv_spec_class directly. + (riscv_after_parse_args): If -mpriv-spec isn't set, then we set the + default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by + calling riscv_set_default_priv_spec. + * testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since + the --with-priv-spec may be set to different privilege spec. + * testsuite/gas/riscv/priv-reg.d: Likewise. + * configure.ac: Add configure option --with-priv-spec. + * configure: Regenerated. + * config.in: Regenerated. + * config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to + explicit_attr. Set it to TRUE if any ELF attribute is found. + (riscv_set_default_priv_spec): Try to set the default_priv_spec if + the priv attributes are set. + (md_assemble): Set the default_priv_spec according to the priv + attributes when we start to assemble instruction. + (riscv_write_out_attrs): Rename riscv_write_out_arch_attr to + riscv_write_out_attrs. Update the arch and priv attributes. If we + don't set the corresponding ELF attributes, then try to output the + default ones. + (riscv_set_public_attributes): If any ELF attribute or -march-attr + options is set (explicit_attr is TRUE), then call riscv_write_out_attrs + to update the arch and priv attributes. + (s_riscv_attribute): Make sure all arch and priv attributes are set + before any instruction. + * testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any + ELF attribute or -march-attr is set. If the priv attributes are not + set, then try to update them by the default setting (-mpriv-spec or + --with-priv-spec). + * testsuite/gas/riscv/attribute-02.d: Likewise. + * testsuite/gas/riscv/attribute-03.d: Likewise. + * testsuite/gas/riscv/attribute-04.d: Likewise. + * testsuite/gas/riscv/attribute-06.d: Likewise. + * testsuite/gas/riscv/attribute-07.d: Likewise. + * testsuite/gas/riscv/attribute-08.d: Likewise. + * testsuite/gas/riscv/attribute-09.d: Likewise. + * testsuite/gas/riscv/attribute-10.d: Likewise. + * testsuite/gas/riscv/attribute-unknown.d: Likewise. + * testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec + set by priv attributes must be supported. + * testsuite/gas/riscv/attribute-05.s: Likewise. + * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated + priv attributes according to the -mpriv-spec option. + * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise. + * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise. + * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise. + * testsuite/gas/riscv/priv-reg.d: Removed. + * testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the + CSR according to the priv spec 1.9. + * testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the + CSR according to the priv spec 1.9.1. + * testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the + CSR according to the priv spec 1.10. + * testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the + CSR according to the priv spec 1.11. + * config/tc-riscv.c (md_show_usage): Add descriptions about + the new GAS options. + * doc/c-riscv.texi: Likewise. + +2020-05-19 Peter Bergner <bergner@linux.ibm.com> + + * testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests. + * testsuite/gas/ppc/power9.d: Likewise. + * testsuite/gas/ppc/power10.s <dcbf, dcbfps, dcbstps, hwsync, lwsync, + pause_short, phwsync, plwsync, ptesync, stcisync, stncisync, stsync, + sync, wait, waitrsv>: Add tests. + * testsuite/gas/ppc/power10.d: Likewise. + +2020-05-19 Alexander Fedotov <alfedotov@gmail.com> + + PR 25992 + * config/tc-arm.c : Add arm_ext_v8r feature. + (it_fsm_post_encode): Check arm_ext_v8r feature. + (get_aeabi_cpu_arch_from_fset): Check arm_ext_v8r feature. + +2020-05-19 Alan Modra <amodra@gmail.com> + + * write.c (write_contents): Use bfd_get_filename rather than + accessing bfd->filename directly. Use bfd_section_name rather + than accessing section->name directly. + +2020-05-19 Alan Modra <amodra@gmail.com> + + * symbols.c (local_symbol_make): Init all of lsy_flags. + +2020-05-18 Alan Modra <amodra@gmail.com> + + * symbols.c (resolve_symbol_value): Invoke LOCAL_SYMBOL_CHECK + before looking at add_symbol->sy_flags. + +2020-05-18 Hongtao Liu <hongtao.liu@intel.com> + + * config/tc-i386.c: Not handle lret/iret. + * testsuite/gas/i386/lfence-ret-a.d: Adjust testcase. + * testsuite/gas/i386/lfence-ret-b.d: Ditto. + * testsuite/gas/i386/lfence-ret-c.d: Ditto. + * testsuite/gas/i386/lfence-ret-d.d: Ditto. + * testsuite/gas/i386/lfence-ret.s: Ditto. + * testsuite/gas/i386/x86-64-lfence-ret-a.d: Ditto. + * testsuite/gas/i386/x86-64-lfence-ret-b.d: Ditto. + * testsuite/gas/i386/x86-64-lfence-ret-c.d: Ditto. + * testsuite/gas/i386/x86-64-lfence-ret-d.d: Ditto. + * testsuite/gas/i386/x86-64-lfence-ret-e.d: Ditto. + * testsuite/gas/i386/x86-64-lfence-ret.s: Ditto. + * testsuite/gas/i386/x86-64-lfence-ret.e: Deleted. + +2020-05-15 Alan Modra <amodra@gmail.com> + Alex Coplan <alex.coplan@arm.com> + + * symbols.c (struct local_symbol): Update comment. + (resolve_symbol_value): For resolved symbols equated to other + symbols, verify that the referenced symbol is not a local_symbol + before accessing sy_value. Don't leave symbol loops during + finalize_syms resolution. + * testsuite/gas/all/assign-bad-recursive.d: New test. + * testsuite/gas/all/assign-bad-recursive.l: Error output for test. + * testsuite/gas/all/assign-bad-recursive.s: Assembly for test. + * testsuite/gas/all/gas.exp: Run it. + +2020-05-14 Nick Clifton <nickc@redhat.com> + + * po/sv.po: Updated Swedish translation. + +2020-05-11 Alan Modra <amodra@gmail.com> + + * testsuite/gas/ppc/scalarquad.d, + * testsuite/gas/ppc/scalarquad.s: New test. + * testsuite/gas/ppc/ppc.exp: Run it. + +2020-05-11 Alan Modra <amodra@gmail.com> + + * testsuite/gas/ppc/rightmost.d, + * testsuite/gas/ppc/rightmost.s: New test. + * testsuite/gas/ppc/ppc.exp: Run it. + +2020-05-11 Alan Modra <amodra@gmail.com> + + * testsuite/gas/ppc/xvtlsbb.d, + * testsuite/gas/ppc/xvtlsbb.s: New test. + * testsuite/gas/ppc/ppc.exp: Run it. + +2020-05-11 Alan Modra <amodra@gmail.com> + + * testsuite/gas/ppc/stringop.d, + * testsuite/gas/ppc/stringop.s: New test. + * testsuite/gas/ppc/ppc.exp: Run it. + +2020-05-11 Peter Bergner <bergner@linux.ibm.com> + + * testsuite/gas/ppc/set_bool.d, + * testsuite/gas/ppc/set_bool.s: New test. + * testsuite/gas/ppc/ppc.exp: Run it. + +2020-05-11 Alan Modra <amodra@gmail.com> + + * testsuite/gas/ppc/bitmanip.d, + * testsuite/gas/ppc/bitmanip.s: New test. + * testsuite/gas/ppc/ppc.exp: Run it. + +2020-05-11 Alan Modra <amodra@gmail.com> + + * testsuite/gas/ppc/genpcv.d, + * testsuite/gas/ppc/genpcv.s: New test. + * testsuite/gas/ppc/ppc.exp: Run it. + +2020-05-11 Alan Modra <amodra@gmail.com> + + * testsuite/gas/ppc/maskmanip.d, + * testsuite/gas/ppc/maskmanip.s: New test. + * testsuite/gas/ppc/ppc.exp: Run it. + +2020-05-11 Alan Modra <amodra@gmail.com> + Peter Bergner <bergner@linux.ibm.com> + + * config/tc-ppc.c (pre_defined_registers): Add accumulators. + (md_assemble): Check acc specified in correct operand. + * testsuite/gas/ppc/outerprod.d, + * testsuite/gas/ppc/outerprod.s, + * testsuite/gas/ppc/vsx4.d, + * testsuite/gas/ppc/vsx4.s: New tests. + * testsuite/gas/ppc/ppc.exp: Run them. + +2020-05-11 Alan Modra <amodra@gmail.com> + + * testsuite/gas/ppc/simd_perm.d, + * testsuite/gas/ppc/simd_perm.s: New test. + * testsuite/gas/ppc/ppc.exp: Run it. + +2020-05-11 Alan Modra <amodra@gmail.com> + + * testsuite/gas/ppc/int128.d, + * testsuite/gas/ppc/int128.s: New test. + * testsuite/gas/ppc/ppc.exp: Run it. + +2020-05-11 Alan Modra <amodra@gmail.com> + + * testsuite/gas/ppc/vsx_32byte.d, + * testsuite/gas/ppc/vsx_32byte.s: New test. + * testsuite/gas/ppc/ppc.exp: Run it. + +2020-05-11 Alan Modra <amodra@gmail.com> + + * testsuite/gas/ppc/vec_mul.s, + * testsuite/gas/ppc/vec_mul.d: New test. + * testsuite/gas/ppc/ppc.exp: Run it. + +2020-05-11 Peter Bergner <bergner@linux.ibm.com> + + * testsuite/gas/ppc/byte_rev.d, + * testsuite/gas/ppc/byte_rev.s: New test. + * testsuite/gas/ppc/ppc.exp: Run it. + +2020-05-11 Peter Bergner <bergner@linux.ibm.com> + + * testsuite/gas/ppc/power10.d: Add paste. tests. + * testsuite/gas/ppc/power10.s: Likewise. + +2020-05-11 Peter Bergner <bergner@linux.ibm.com> + + * testsuite/gas/ppc/power10.s: New test. + * testsuite/gas/ppc/power10.d: Likewise. + * testsuite/gas/ppc/ppc.exp: Run it. + +2020-05-11 Alan Modra <amodra@gmail.com> + + * config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10 + renaming. + * testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in + place of -mfuture/-Mfuture. + * testsuite/gas/ppc/prefix-pcrel.d: Likewise. + * testsuite/gas/ppc/prefix-reloc.d: Likewise. + +2020-05-06 Nick Clifton <nickc@redhat.com> + + * po/sv.po: Updated Swedish translation. + +2020-05-06 Nick Clifton <nickc@redhat.com> + + PR 25927 + * doc/as.texi (Preprocessing): Replace cross reference to not + existant document with a URL to the equivalent page in the GCC + manual. + +2020-05-05 Nick Clifton <nickc@redhat.com> + + * dwarf2dbg.c (out_dir_and_file_list): Add comments describing the + construction of a DWARF-5 directory name table. + * testsuite/gas/elf/pr25917.d: Update expected output. + +2020-05-05 Gunther Nikl <gnikl@justmail.de> + + * config/tc-rx.c (elf_flags): Initialize for non-linux targets. + (md_parse_option): Remove initialization of elf_flags. + +2020-05-04 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR gas/25863 + * config/tc-arm.c (do_mve_vmull): Fix scalar and NEON parsing of vmul. + * testsuite/gas/arm/mve-scalar-vmult-it.d: New test. + * testsuite/gas/arm/mve-scalar-vmult-it.s: New test. + +2020-05-04 Nick Clifton <nickc@redhat.com> + + PR 25917 + * dwarf2dbg.c (out_dir_and_file_list): Check for the directory + table's existence before looking at its entries. + Also do not emit a default directory entry if there are no + directories in use. + + * testsuite/gas/elf/pr25917.s: New test source file. + * testsuite/gas/elf/pr25917.d: New test driver. + * testsuite/gas/elf/elf.exp (run_elf_list_test): Run the new test. + +2020-04-30 Alex Coplan <alex.coplan@arm.com> + + * config/tc-aarch64.c (fix_insn): Implement for + AARCH64_OPND_UNDEFINED. + (parse_operands): Implement for AARCH64_OPND_UNDEFINED. + * testsuite/gas/aarch64/udf.s: New. + * testsuite/gas/aarch64/udf.d: New. + * testsuite/gas/aarch64/udf-invalid.s: New. + * testsuite/gas/aarch64/udf-invalid.l: New. + * testsuite/gas/aarch64/udf-invalid.d: New. + +2020-04-30 Yoshinori Sato <ysato@users.sourceforge.jp> + + * config/tc-rx.c (elf_flags): Reset default value. + (md_parse_option): For rx-elf Initialize elf_flags with RX_ABI. + +2020-04-29 Max Filippov <jcmvbkbc@gmail.com> + + * config/tc-xtensa.c (XTENSA_MARCH_EARLIEST): Define macro as 0 + if it's not defined. + (microarch_earliest): New static variable. + (xg_translate_idioms): Translate "simcall" to "simcall 0" when + simcall opcode has mandatory parameter. + (xg_init_global_config): Initialize microarch_earliest. + +2020-04-29 Nick Clifton <nickc@redhat.com> + + PR 22699 + * config/tc-sh.c (build_Mytes): Change operand type IMM0_8 to + IMM0_8S and add support for IMM0_8U. + * testsuite/gas/sh/sh4a.s: Add test of a logical insn using an + unsigned 8-bit immediate. + * testsuite/gas/sh/sh4a.d: Extended expected disassembly. + * testsuite/gas/sh/sh4al-dsp.d: Update expected disassembly. + +2020-04-27 Tamar Christina <tamar.christina@arm.com> + + * NEWS: Add news entry for big-obj. + * config/tc-i386.c (i386_target_format): Support new format. + * doc/c-i386.texi: Add i386 support. + * testsuite/gas/pe/big-obj.d: Rename test to not be x64 specific. + * testsuite/gas/pe/pe.exp (big-obj): Make test run on i386 as well. + +2020-04-27 Nick Clifton <nickc@redhat.com> + + PR 25878 + * dwarf2dbg.c (struct file_entry): Add auto_assigned field. + (assign_file_to_slot): New function. Fills in an entry in the + files table. + (allocate_filenum): Use new function. + (allocate_filename_to_slot): Use new function. If the specified + slot entry is already in use, but was chosen automatically then + reassign the automatic entry. + +2020-04-26 Hongtao Liu <hongtao.liu@intel.com + + * config/tc-i386.c (lfence_before_ret_shl): New member. + (load_insn_p): implict load for POP/POPA/POPF/XLATB, no load + for Anysize insns. + (insert_after_load): Issue warning for REP CMPS/SCAS. + (insert_before_before): Handle iret, Handle + -mlfence-before-ret=shl, Adjust operand size of or/not/shl to ret's, + (md_parse_option): Change -mlfence-before-ret=[none|not|or] to + -mlfence-before-ret=[none/not/or/shl/yes]. + Enable -mlfence-before-ret=shl when + -mlfence-beofre-indirect-branch=all and no explict -mlfence-before-ret option. + (md_show_usage): Ditto. + * doc/c-i386.texi: Ditto. + * testsuite/gas/i386/i386.exp: Add new testcases. + * testsuite/gas/i386/lfence-load-b.d: New. + * testsuite/gas/i386/lfence-load-b.e: New. + * testsuite/gas/i386/lfence-load.d: Modified. + * testsuite/gas/i386/lfence-load.e: New. + * testsuite/gas/i386/lfence-load.s: Modified. + * testsuite/gas/i386/lfence-ret-a.d: Modified. + * testsuite/gas/i386/lfence-ret-b.d: Modified. + * testsuite/gas/i386/lfence-ret-c.d: New. + * testsuite/gas/i386/lfence-ret-d.d: New. + * testsuite/gas/i386/lfence-ret.s: Modified. + * testsuite/gas/i386/x86-64-lfence-load-b.d: New. + * testsuite/gas/i386/x86-64-lfence-load.d: Modified. + * testsuite/gas/i386/x86-64-lfence-load.s: Modified. + * testsuite/gas/i386/x86-64-lfence-ret-a.d: Modified. + * testsuite/gas/i386/x86-64-lfence-ret-b.d: Modified. + * testsuite/gas/i386/x86-64-lfence-ret-c.d: New. + * testsuite/gas/i386/x86-64-lfence-ret-d.d: New + * testsuite/gas/i386/x86-64-lfence-ret-e.d: New. + * testsuite/gas/i386/x86-64-lfence-ret.e: New. + * testsuite/gas/i386/x86-64-lfence-ret.s: New. + +2020-04-22 Max Filippov <jcmvbkbc@gmail.com> + + PR ld/25861 + * config/tc-xtensa.c (md_apply_fix): Replace + BFD_RELOC_XTENSA_DIFF{8,16,32} generation with + BFD_RELOC_XTENSA_PDIFF{8,16,32} and + BFD_RELOC_XTENSA_NDIFF{8,16,32} generation. + * testsuite/gas/xtensa/loc.d: Replace BFD_RELOC_XTENSA_DIFF16 + with BFD_RELOC_XTENSA_PDIFF16 in the expected output. + +2020-04-22 Alan Modra <amodra@gmail.com> + + * config/obj-elf.c (elf_frob_symbol): Unconditionally remove + symbol for ".symver .. remove". + * doc/as.texi (.symver): Update. + * testsuite/gas/symver/symver11.s: Make foo weak. + * testsuite/gas/symver/symver11.d: Expect an error. + * testsuite/gas/symver/symver7.d: Allow other random symbols. + +2020-04-21 H.J. Lu <hongjiu.lu@intel.com> + + * testsuite/gas/symver/symver11.s: Add ".balign 8". + +2020-04-21 Andreas Schwab <schwab@linux-m68k.org> + + PR 25848 + * testsuite/gas/m68k/operands.s: Add tests for cmpi. + * testsuite/gas/m68k/operands.d: Update. + * testsuite/gas/m68k/op68000.d: Update for new error messages. + +2020-04-21 Tamar Christina <tamar.christina@arm.com> + + PR binutils/24753 + * testsuite/gas/arm/pr24753.d: New test. + * testsuite/gas/arm/pr24753.s: New test. + +2020-04-21 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/23840 + PR gas/25295 + * NEWS: Mention .symver extension. + * config/obj-elf.c (obj_elf_find_and_add_versioned_name): New + function. + (obj_elf_symver): Call obj_elf_find_and_add_versioned_name to + add a version name. Add local, hidden and remove visibility + support. + (elf_frob_symbol): Handle the list of version names. Update the + original symbol to local, hidden or remove it from the symbol + table. + (elf_frob_file_before_adjust): Handle the list of version names. + * config/obj-elf.h (elf_visibility): New. + (elf_versioned_name_list): Likewise. + (elf_obj_sy): Change local to bitfield. Add rename, bad_version + and visibility. Change versioned_name pointer to struct + elf_versioned_name_list. + * doc/as.texi: Update .symver directive. + * testsuite/gas/symver/symver.exp: Run all *.d tests. Add more + error checking tests. + * testsuite/gas/symver/symver6.d: New file. + * testsuite/gas/symver/symver7.d: Likewise. + * testsuite/gas/symver/symver7.s: Likewise. + * testsuite/gas/symver/symver8.d: Likewise. + * testsuite/gas/symver/symver8.s: Likewise. + * testsuite/gas/symver/symver9.s: Likewise. + * testsuite/gas/symver/symver9a.d: Likewise. + * testsuite/gas/symver/symver9b.d: Likewise. + * testsuite/gas/symver/symver10.s: Likewise. + * testsuite/gas/symver/symver10a.d: Likewise. + * testsuite/gas/symver/symver10b.d: Likewise. + * testsuite/gas/symver/symver11.d: Likewise. + * testsuite/gas/symver/symver11.s: Likewise. + * testsuite/gas/symver/symver12.d: Likewise. + * testsuite/gas/symver/symver12.s: Likewise. + * testsuite/gas/symver/symver13.d: Likewise. + * testsuite/gas/symver/symver13.s: Likewise. + * testsuite/gas/symver/symver14.d: Likewise. + * testsuite/gas/symver/symver14.l: Likewise. + * testsuite/gas/symver/symver15.d: Likewise. + * testsuite/gas/symver/symver15.l: Likewise. + * testsuite/gas/symver/symver6.l: Removed. + * testsuite/gas/symver/symver6.s: Updated. + +2020-04-20 Sudakshina Das <sudi.das@arm.com> + + * config/tc-aarch64.c (parse_barrier_psb): Update error messages + to include TSB. + * testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests. + * testsuite/gas/aarch64/system-2.s: Add new tsb tests. + * testsuite/gas/aarch64/system.d: Update. + +2020-04-20 Sudakshina Das <sudi.das@arm.com> + + * testsuite/gas/aarch64/bti.d: Update -march option. + * testsuite/gas/aarch64/illegal-bti.d: Remove. + * testsuite/gas/aarch64/illegal-bti.l: Remove. + * testsuite/gas/aarch64/illegal-ras-1.l: Remove esb. + * testsuite/gas/aarch64/illegal-ras-1.s: Remove esb. + +2020-04-17 Alan Modra <amodra@gmail.com> + + * config/tc-bfin.h (TC_EQUAL_IN_INSN): Allow assignment to dot. + +2020-04-16 Gagan Singh Sidhu <broly@mac.com> + Nick Clifton <nickc@redhat.com> + + PR 25803 + * config/obj-elf.c (obj_elf_type): Reject ifunc symbols on MIPS + targets. + * testsuite/gas/elf/elf.exp: Add MIPS targets to the list to skip + for the type-2 test. + * testsuite/gas/elf/type-noifunc.e: Update to allow for MIPS + targets running this test. + +2020-02-16 David Faust <david.faust@oracle.com> + + * testsuite/gas/bpf/bpf.exp: Run jump32 tests. + * testsuite/gas/bpf/jump32.s: New file. + * testsuite/gas/bpf/jump32.d: Likewise. + +2020-04-08 H.J. Lu <hongjiu.lu@intel.com> + + * doc/c-i386.texi: Correct -mlfence-before-indirect-branch= + documentation. + +2020-04-08 Gunther Nikl <gnikl@justmail.de> + + * config/tc-moxie.h (MD_PCREL_FROM_SECTION): Delete define. + (md_pcrel_from): Remove prototytpe. + * config/tc-m32c.h (MD_PCREL_FROM_SECTION): Delete duplicate + define. + (md_pcrel_from_section): Remove duplicate prototype. + * tc.h (md_pcrel_from_section): Add prototype. + * config/tc-aarch64.h (md_pcrel_from_section): Remove prototype. + * config/tc-arc.h (md_pcrel_from_section): Likewise. + * config/tc-arm.h (md_pcrel_from_section): Likewise. + * config/tc-avr.h (md_pcrel_from_section): Likewise. + * config/tc-bfin.h (md_pcrel_from_section): Likewise. + * config/tc-bpf.h (md_pcrel_from_section): Likewise. + * config/tc-csky.h (md_pcrel_from_section): Likewise. + * config/tc-d10v.h (md_pcrel_from_section): Likewise. + * config/tc-d30v.h (md_pcrel_from_section): Likewise. + * config/tc-epiphany.h (md_pcrel_from_section): Likewise. + * config/tc-fr30.h (md_pcrel_from_section): Likewise. + * config/tc-frv.h (md_pcrel_from_section): Likewise. + * config/tc-iq2000.h (md_pcrel_from_section): Likewise. + * config/tc-lm32.h (md_pcrel_from_section): Likewise. + * config/tc-m32c.h (md_pcrel_from_section): Likewise. + * config/tc-m32r.h (md_pcrel_from_section): Likewise. + * config/tc-mcore.h (md_pcrel_from_section): Likewise. + * config/tc-mep.h (md_pcrel_from_section): Likewise. + * config/tc-metag.h (md_pcrel_from_section): Likewise. + * config/tc-microblaze.h (md_pcrel_from_section): Likewise. + * config/tc-mmix.h (md_pcrel_from_section): Likewise. + * config/tc-moxie.h (md_pcrel_from_section): Likewise. + * config/tc-msp430.h (md_pcrel_from_section): Likewise. + * config/tc-mt.h (md_pcrel_from_section): Likewise. + * config/tc-or1k.h (md_pcrel_from_section): Likewise. + * config/tc-ppc.h (md_pcrel_from_section): Likewise. + * config/tc-rl78.h (md_pcrel_from_section): Likewise. + * config/tc-rx.h (md_pcrel_from_section): Likewise. + * config/tc-s390.h (md_pcrel_from_section): Likewise. + * config/tc-sh.h (md_pcrel_from_section): Likewise. + * config/tc-xc16x.h (md_pcrel_from_section): Likewise. + * config/tc-xstormy16.h (md_pcrel_from_section): Likewise. + * config/tc-microblaze.h (md_begin, md_assemble, md_undefined_symbol, + md_show_usage, md_convert_frag, md_operand, md_number_to_chars, + md_estimate_size_before_relax, md_section_align, tc_gen_reloc, + md_apply_fix3): Delete prototypes. + +2020-04-07 H.J. Lu <hongjiu.lu@intel.com> + + * NEWS: Mention support for Intel SERIALIZE and TSXLDTRK + instructions. + +2020-04-07 H.J. Lu <hongjiu.lu@intel.com> + + * doc/c-z80.texi: Fix @xref warnings. + +2020-04-07 Lili Cui <lili.cui@intel.com> + + * config/tc-i386.c (cpu_arch): Add .TSXLDTRK. + (cpu_noarch): Likewise. + * doc/c-i386.texi: Document TSXLDTRK. + * testsuite/gas/i386/i386.exp: Run TSXLDTRK tests. + * testsuite/gas/i386/tsxldtrk.d: Likewise. + * testsuite/gas/i386/tsxldtrk.s: Likewise. + * testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise. + +2020-04-02 Lili Cui <lili.cui@intel.com> + + * config/tc-i386.c (cpu_arch): Add .serialize. + (cpu_noarch): Likewise. + * doc/c-i386.texi: Document serialize. + * testsuite/gas/i386/i386.exp: Run serialize tests + * testsuite/gas/i386/serialize.d: Likewise. + * testsuite/gas/i386/x86-64-serialize.d: Likewise. + * testsuite/gas/i386/serialize.s: Likewise. + +2020-04-02 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + * testsuite/gas/elf/section12a.d: Use notarget instead of xfail. + * testsuite/gas/elf/section12b.d: Likewise. + * testsuite/gas/elf/section16a.d: Likewise. + * testsuite/gas/elf/section16b.d: Likewise. + +2020-04-02 Gunther Nikl <gnikl@justmail.de> + + * config/tc-m68k.c (m68k_ip): Fix range check for index register + with a suppressed address register. + +2020-04-01 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/25756 + * config/tc-i386.h (TC_FORCE_RELOCATION_ABS): New. + * testsuite/gas/i386/localpic.s: Add a test for relocation + against local absolute symbol. + * testsuite/gas/i386/x86-64-localpic.s: Likewise. + * testsuite/gas/i386/localpic.d: Updated. + * testsuite/gas/i386/x86-64-localpic.d: Likewise. + * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. + +2020-04-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + PR gas/25732 + * testsuite/gas/i386/solaris/x86-64-branch-2.d: New file. + * testsuite/gas/i386/solaris/x86-64-branch-3.d: New file. + * testsuite/gas/i386/solaris/x86-64-jump.d: Incorporate changes to + testsuite/gas/i386/x86-64-jump.d. + * testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d: + Incorporate changes to + gas/testsuite/gas/i386/x86-64-mpx-branch-1.d. + * testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d : Incorporate + changes to testsuite/gas/i386/x86-64-mpx-branch-2.d. + * testsuite/gas/i386/x86-64-branch-2.d: Skip on *-*-solaris*. + * testsuite/gas/i386/x86-64-branch-3.d: Likewise. + +2020-03-31 Maciej W. Rozycki <macro@linux-mips.org> + + PR 25611 + PR 25614 + * dwarf2dbg.c: Do not include "bignum.h". + +2020-03-30 Nelson Chu <nelson.chu@sifive.com> + + * testsuite/gas/riscv/alias-csr.d: Move this to priv-reg-pseudo. + * testsuite/gas/riscv/alias-csr.s: Likewise. + * testsuite/gas/riscv/no-aliases-csr.d: Move this + to priv-reg-pseudo-noalias. + * testsuite/gas/riscv/bad-csr.d: Rename to priv-reg-fail-nonexistent. + * testsuite/gas/riscv/bad-csr.l: Likewise. + * testsuite/gas/riscv/bad-csr.s: Likewise. + * testsuite/gas/riscv/satp.d: Removed. Already included in priv-reg. + * testsuite/gas/riscv/satp.s: Likewise. + * testsuite/gas/riscv/priv-reg-pseudo.d: New testcase for all pseudo + csr instruction, including alias-csr testcase. + * testsuite/gas/riscv/priv-reg-pseudo.s: Likewise. + * testsuite/gas/riscv/priv-reg-pseudo-noalias.d: New testcase for all + pseudo instruction with objdump -Mno-aliases. + * testsuite/gas/riscv/priv-reg-fail-nonexistent.d: New testcase. + * testsuite/gas/riscv/priv-reg-fail-nonexistent.l: Likewise. + * testsuite/gas/riscv/priv-reg-fail-nonexistent.s: Likewise. + * testsuite/gas/riscv/priv-reg.d: Update CSR to 1.11. + * testsuite/gas/riscv/priv-reg.s: Likewise. + * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. + * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. + * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. + +2020-03-25 J.W. Jagersma <jwjagersma@gmail.com> + + * config/obj-coff.c (obj_coff_section): Set the bss flag on + sections with the "b" attribute. + +2020-03-22 Alan Modra <amodra@gmail.com> + + * testsuite/gas/s12z/truncated.d: Update expected output. + +2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com> + + PR 25690 + * config/tc-z80.c (md_pseudo_table): Add xdef anf xref pseudo ops. + * doc/c-z80.texi: Update documentation. + +2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com> + + PR 25641 + PR 25668 + PR 25633 + Fix disassembling ED+A4/AC/B4/BC opcodes. + Fix assembling lines containing colonless label and instruction + with first operand inside parentheses. + Fix registration of unsupported by target CPU registers. + * config/tc-z80.c: See above. + * config/tc-z80.h: See above. + * testsuite/gas/z80/colonless.d: Update test. + * testsuite/gas/z80/colonless.s: Likewise. + * testsuite/gas/z80/ez80_adl_all.d: Likewise. + * testsuite/gas/z80/ez80_unsup_regs.d: Likewise. + * testsuite/gas/z80/ez80_z80_all.d: Likewise. + * testsuite/gas/z80/gbz80_unsup_regs.d: Likewise. + * testsuite/gas/z80/r800_unsup_regs.d: Likewise. + * testsuite/gas/z80/unsup_regs.s: Likewise. + * testsuite/gas/z80/z180_unsup_regs.d: Likewise. + * testsuite/gas/z80/z80.exp: Likewise. + * testsuite/gas/z80/z80_strict_unsup_regs.d: Likewise. + * testsuite/gas/z80/z80_unsup_regs.d: Likewise. + * testsuite/gas/z80/z80n_unsup_regs.d: Likewise. + +2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR 25660 + * config/tc-arm.c (operand_parse_code): Add OP_RNSDMQR and OP_oRNSDMQ. + (parse_operands): Handle new operand codes. + (do_neon_dyadic_long): Make shape check accept the scalar variants. + (asm_opcode_insns): Fix operand codes for vaddl and vsubl. + * testsuite/gas/arm/mve-vaddsub-it.s: New test. + * testsuite/gas/arm/mve-vaddsub-it.d: New test. + * testsuite/gas/arm/mve-vaddsub-it-bad.s: New test. + * testsuite/gas/arm/mve-vaddsub-it-bad.l: New test. + * testsuite/gas/arm/mve-vaddsub-it-bad.d: New test. + * testsuite/gas/arm/nomve-vaddsub-it.d: New test. + +2020-03-11 H.J. Lu <hongjiu.lu@intel.com> + + * NEWS: Mention x86 assembler options for CVE-2020-0551. + +2020-03-11 H.J. Lu <hongjiu.lu@intel.com> + + * testsuite/gas/i386/i386.exp: Run new tests. + * testsuite/gas/i386/lfence-byte.d: New file. + * testsuite/gas/i386/lfence-byte.e: Likewise. + * testsuite/gas/i386/lfence-byte.s: Likewise. + * testsuite/gas/i386/lfence-indbr-a.d: Likewise. + * testsuite/gas/i386/lfence-indbr-b.d: Likewise. + * testsuite/gas/i386/lfence-indbr-c.d: Likewise. + * testsuite/gas/i386/lfence-indbr.e: Likewise. + * testsuite/gas/i386/lfence-indbr.s: Likewise. + * testsuite/gas/i386/lfence-load.d: Likewise. + * testsuite/gas/i386/lfence-load.s: Likewise. + * testsuite/gas/i386/lfence-ret-a.d: Likewise. + * testsuite/gas/i386/lfence-ret-b.d: Likewise. + * testsuite/gas/i386/lfence-ret.s: Likewise. + * testsuite/gas/i386/x86-64-lfence-byte.d: Likewise. + * testsuite/gas/i386/x86-64-lfence-byte.e: Likewise. + * testsuite/gas/i386/x86-64-lfence-byte.s: Likewise. + * testsuite/gas/i386/x86-64-lfence-indbr-a.d: Likewise. + * testsuite/gas/i386/x86-64-lfence-indbr-b.d: Likewise. + * testsuite/gas/i386/x86-64-lfence-indbr-c.d: Likewise. + * testsuite/gas/i386/x86-64-lfence-indbr.e: Likewise. + * testsuite/gas/i386/x86-64-lfence-indbr.s: Likewise. + * testsuite/gas/i386/x86-64-lfence-load.d: Likewise. + * testsuite/gas/i386/x86-64-lfence-load.s: Likewise. + * testsuite/gas/i386/x86-64-lfence-ret-a.d: Likewise. + * testsuite/gas/i386/x86-64-lfence-ret-b.d: Likewise. + +2020-03-11 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (lfence_after_load): New. + (lfence_before_indirect_branch_kind): New. + (lfence_before_indirect_branch): New. + (lfence_before_ret_kind): New. + (lfence_before_ret): New. + (last_insn): New. + (load_insn_p): New. + (insert_lfence_after): New. + (insert_lfence_before): New. + (md_assemble): Call insert_lfence_before and insert_lfence_after. + Set last_insn. + (OPTION_MLFENCE_AFTER_LOAD): New. + (OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH): New. + (OPTION_MLFENCE_BEFORE_RET): New. + (md_longopts): Add -mlfence-after-load=, + -mlfence-before-indirect-branch= and -mlfence-before-ret=. + (md_parse_option): Handle -mlfence-after-load=, + -mlfence-before-indirect-branch= and -mlfence-before-ret=. + (md_show_usage): Display -mlfence-after-load=, + -mlfence-before-indirect-branch= and -mlfence-before-ret=. + (i386_cons_align): New. + * config/tc-i386.h (i386_cons_align): New. + (md_cons_align): New. + * doc/c-i386.texi: Document -mlfence-after-load=, + -mlfence-before-indirect-branch= and -mlfence-before-ret=. + +2020-03-11 Nick Clifton <nickc@redhat.com> + + PR 25611 + PR 25614 + * dwarf2dbg.c (DWARF2_FILE_TIME_NAME): Default to -1. + (DWARF2_FILE_SIZE_NAME): Default to -1. + (DWARF2_LINE_VERSION): Default to the current dwarf level or 3, + whichever is higher. + (DWARF2_LINE_MAX_OPS_PER_INSN): Provide a default value of 1. + (NUM_MD5_BYTES): Define. + (struct file entry): Add md5 field. + (get_filenum): Delete and replace with... + (get_basename): New function. + (get_directory_table_entry): New function. + (allocate_filenum): New function. + (allocate_filename_to_slot): New function. + (dwarf2_where): Use new functions. + (dwarf2_directive_filename): Add support for extended .file + pseudo-op. + (dwarf2_directive_loc): Allow the use of file number zero with + DWARF 5 or higher. + (out_file_list): Rename to... + (out_dir_and_file_list): Add DWARF 5 support. + (out_debug_line): Emit extra values into the section header for + DWARF 5. + (out_debug_str): Allow for file 0 to be used with DWARF 5. + * doc/as.texi (.file): Update the description of this pseudo-op. + * testsuite/gas/elf-dwarf-5-file0.s: Add more lines. + * testsuite/gas/elf-dwarf-5-file0.d: Update expected dump output. + * testsuite/gas/lns/lns-diag-1.l: Update expected error message. + * NEWS: Mention the new feature. + +2020-03-10 Alan Modra <amodra@gmail.com> + + * config/tc-csky.c (get_operand_value): Rewrite 1 << 31 expressions + to avoid signed overflow. + * config/tc-mcore.c (md_assemble): Likewise. + * config/tc-mips.c (gpr_read_mask, gpr_write_mask): Likewise. + * config/tc-nds32.c (SET_ADDEND): Likewise. + * config/tc-nios2.c (nios2_assemble_arg_R): Likewise. + +2020-03-09 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/avx.s: Add long-form VCMP[PS][SD] pseudos. + * testsuite/gas/i386/avx.d, testsuite/gas/i386/avx-16bit.d, + testsuite/gas/i386/avx-intel.d: Adjust expectations. + +2020-03-07 Alan Modra <amodra@gmail.com> + + * testsuite/gas/elf/dwarf-5-file0.s: Don't start directives in + first column. + +2020-03-06 Nick Clifton <nickc@redhat.com> + + PR 25614 + * dwarf2dbg.c (dwarf2_directive_filename): Allow a file number of + 0 if the dwarf_level is 5 or more. Complain if a filename follows + a file 0. + * testsuite/gas/elf/dwarf-5-file0.s: New test. + * testsuite/gas/elf/dwarf-5-file0.d: New test driver. + * testsuite/gas/elf/elf.exp: Run the new test. + + PR 25612 + * config/tc-ia64.h (DWARF2_VERISION): Fix typo. + * doc/as.texi: Fix another typo. + +2020-03-06 Nick Clifton <nickc@redhat.com> + + PR 25612 + * as.c (dwarf_level): Define. + (show_usage): Add --gdwarf-3, --gdwarf-4 and --gdwarf-5. + (parse_args): Add support for the new options. + as.h (dwarf_level): Prototype. + * dwarf2dbg.c (DWARF2_VERSION): Use dwarf_level as default version + value. + * config/tc-ia64.h (DWARF2_VERISION): Update definition. + (DWARF2_LINE_VERSION): Remove definition. + * doc/as.texi: Document the new options. + +2020-03-06 Nick Clifton <nickc@redhat.com> + + PR 25572 + * as.c (main): Allow matching input and outputs when they are + not regular files. + +2020-03-06 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (match_mem_size): Generalize broadcast special + casing. + (check_VecOperands): Zap xmmword/ymmword/zmmword when more than + one of byte/word/dword/qword is set alongside a SIMD register in + a template's operand. + +2020-03-06 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (match_template): Extend code in logic + rejecting certain suffixes in certain modes to also cover mask + register use and VecSIB. Drop special casing of broadcast. Skip + immediates in the check. + +2020-03-06 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (match_template): Fold duplicate code in + logic rejecting certain suffixes in certain modes. Drop + pointless "else". + +2020-03-06 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (process_suffix): Exlucde !vexw insns + alongside !norex64 ones. + * testsuite/gas/i386/x86-64-avx512bw.s: Test VPEXTR* and VPINSR* + with both 32- and 64-bit GPR operands. + * testsuite/gas/i386/x86-64-avx512f.s: Test VEXTRACTPS with both + 32- and 64-bit GPR operands. + * testsuite/gas/i386/x86-64-avx512bw-intel.d, + testsuite/gas/i386/x86-64-avx512bw.d, + testsuite/gas/i386/x86-64-avx512f-intel.d, + testsuite/gas/i386/x86-64-avx512f.d: Adjust expectations. + +2020-03-06 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (md_assemble): Drop use of rex64. + (process_suffix): For REX.W for 64-bit CRC32. + +2020-03-06 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (i386_addressing_mode): For 32-bit + addressing for MPX insns without base/index. + * testsuite/gas/i386/mpx-16bit.s, + * testsuite/gas/i386/mpx-16bit.d: New. + * testsuite/gas/i386/i386.exp: Run new test. + +2020-03-06 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/adx.s, testsuite/gas/i386/cet.s, + testsuite/gas/i386/ept.s, testsuite/gas/i386/fsgs.s, + testsuite/gas/i386/invpcid.s, testsuite/gas/i386/movdir.s, + testsuite/gas/i386/ptwrite.s, testsuite/gas/i386/vmx.s, + * testsuite/gas/i386/code16.s: Add CR, DR, and TR access cases + as well as a BSWAP one. + * testsuite/gas/i386/rdpid.s: Add 16-bit case. + * testsuite/gas/i386/sse2-16bit.s: Cover more insns. + * testsuite/gas/i386/adx-intel.d, testsuite/gas/i386/adx.d, + testsuite/gas/i386/cet-intel.d, testsuite/gas/i386/cet.d, + testsuite/gas/i386/code16.d, testsuite/gas/i386/ept-intel.d, + testsuite/gas/i386/ept.d, testsuite/gas/i386/fsgs-intel.d, + testsuite/gas/i386/fsgs.d, testsuite/gas/i386/invpcid-intel.d, + testsuite/gas/i386/invpcid.d, testsuite/gas/i386/movdir-intel.d, + testsuite/gas/i386/movdir.d, testsuite/gas/i386/ptwrite-intel.d, + testsuite/gas/i386/ptwrite.d, testsuite/gas/i386/rdpid-intel.d, + testsuite/gas/i386/rdpid.d, testsuite/gas/i386/sse2-16bit.d, + testsuite/gas/i386/vmx.d: Adjust expectations. + +2020-03-06 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (md_assemble): Also exclude tpause and umwait + from having their operands swapped. + * testsuite/gas/i386/waitpkg.s, + testsuite/gas/i386/x86-64-waitpkg.s: Add tpause and umwait + 3-operand cases as well as testing of 16-bit code generation. + * testsuite/gas/i386/waitpkg.d, + testsuite/gas/i386/waitpkg-intel.d, + testsuite/gas/i386/x86-64-waitpkg.d, + testsuite/gas/i386/x86-64-waitpkg-intel.d: Adjust expectations. + +2020-03-04 Nelson Chu <nelson.chu@sifive.com> + + * config/tc-riscv.c (percent_op_utype): Support the modifier + %got_pcrel_hi. + * doc/c-riscv.texi: Add documentation. + * testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new + modifier %got_pcrel_hi. + * testsuite/gas/riscv/no-relax-reloc.s: Likewise. + * testsuite/gas/riscv/relax-reloc.d: Likewise. + * testsuite/gas/riscv/relax-reloc.s: Likewise. + + * doc/c-riscv.texi (relocation modifiers): Add documentation. + (RISC-V-Formats): Update the section name from "Instruction Formats" + to "RISC-V Instruction Formats". + +2020-03-04 Alexandre Oliva <oliva@adacore.com> + + * config/tc-arm.c (md_apply_fix): Warn if a PC-relative load is + detected in a section which does not have at least 4 byte + alignment. + * testsuite/gas/arm/armv8-ar-it-bad.s: Add alignment directive. + * testsuite/gas/arm/ldr-t.s: Likewise. + * testsuite/gas/arm/sp-pc-usage-t.s: Likewise. + * testsuite/gas/arm/sp-pc-usage-t.d: Finish test at end of + disassembly, ignoring any NOPs that may have been inserted because + of section alignment. + * testsuite/gas/arm/ldr-t.d: Likewise. + +2020-03-04 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (cpu_arch): Add .sev_es entry. + * doc/c-i386.texi: Mention sev_es. + * testsuite/gas/i386/arch-13.s: Add SEV-ES case. + * testsuite/gas/i386/arch-13.d: Extend -march=. Adjust + expectations. + * testsuite/gas/i386/arch-13-znver1.d, + testsuite/gas/i386/arch-13-znver2.d: Extend -march=. + +2020-03-03 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (match_template): Replace ignoresize and + defaultsize with mnemonicsize. + (process_suffix): Likewise. + +2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com> + + PR 25627 + * config/tc-z80.c (emit_ld_rr_m): Fix invalid compilation of + instruction LD IY,(HL). + * testsuite/gas/z80/ez80_adl_all.d: Update expected disassembly. + * testsuite/gas/z80/ez80_adl_all.s: Add tests of the instruction. + * testsuite/gas/z80/ez80_z80_all.d: Update expected disassembly. + * testsuite/gas/z80/ez80_z80_all.s: Add tests of the instruction. + +2020-03-03 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/25622 + * testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and + x86-64-default-suffix-avx. + * testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss, + vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries. + * testsuite/gas/i386/noreg64.d: Updated. + * testsuite/gas/i386/noreg64.l: Likewise. + * testsuite/gas/i386/x86-64-default-suffix-avx.d: New file. + * testsuite/gas/i386/x86-64-default-suffix.d: Likewise. + * testsuite/gas/i386/x86-64-default-suffix.s: Likewise. + +2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com> + + PR 25604 + * config/tc-z80.c (contains_register): Prevent an illegal memory + access when checking an expression for a register name. + +2020-03-03 Alan Modra <amodra@gmail.com> + + * config/obj-coff.h: Remove vestiges of coff-m68k and pe-mips + support. + +2020-03-02 Alan Modra <amodra@gmail.com> + + * config/tc-m32r.c (md_begin): Set SEC_SMALL_DATA on .scommon section. + * config/tc-mips.c (s_change_sec): Set SEC_SMALL_DATA for .sdata + and .sbss sections. + * config/tc-score.c: Delete !BFD_ASSEMBLER code throughout. + (s3_s_change_sec): Set SEC_SMALL_DATA for .sbss section. + (s3_s_score_lcomm): Likewise. + * config/tc-score7.c: Similarly. + * read.c (bss_alloc): Set SEC_SMALL_DATA for .sbss section. + +2020-02-28 YunQiang Su <syq@debian.org> + + PR gas/25539 + * config/tc-mips.c (fix_loongson3_llsc): Compare label value + to handle multi-labels. + (has_label_name): New. + +2020-02-26 Matthew Malcomson <matthew.malcomson@arm.com> + + * config/tc-arm.c (enum pred_instruction_type): Remove + NEUTRAL_IT_NO_VPT_INSN predication type. + (cxn_handle_predication): Modify to require condition suffixes. + (handle_pred_state): Remove NEUTRAL_IT_NO_VPT_INSN cases. + * testsuite/gas/arm/cde-scalar.s: Update test. + * testsuite/gas/arm/cde-warnings.l: Update test. + * testsuite/gas/arm/cde-warnings.s: Update test. + +2020-02-26 Alan Modra <amodra@gmail.com> + + * config/tc-arm.c (reg_expected_msgs[REG_TYPE_RNB]): Don't use + N_() on empty string. + +2020-02-26 Alan Modra <amodra@gmail.com> + + * read.c (read_a_source_file): Call strncpy with length one + less than size of original_case_string. + +2020-02-26 Alan Modra <amodra@gmail.com> + + * config/obj-elf.c: Indent labels correctly. + * config/obj-macho.c: Likewise. + * config/tc-aarch64.c: Likewise. + * config/tc-alpha.c: Likewise. + * config/tc-arm.c: Likewise. + * config/tc-cr16.c: Likewise. + * config/tc-crx.c: Likewise. + * config/tc-frv.c: Likewise. + * config/tc-i386-intel.c: Likewise. + * config/tc-i386.c: Likewise. + * config/tc-ia64.c: Likewise. + * config/tc-mn10200.c: Likewise. + * config/tc-mn10300.c: Likewise. + * config/tc-nds32.c: Likewise. + * config/tc-riscv.c: Likewise. + * config/tc-s12z.c: Likewise. + * config/tc-xtensa.c: Likewise. + * config/tc-z80.c: Likewise. + * read.c: Likewise. + * symbols.c: Likewise. + * write.c: Likewise. + +2020-02-20 Nelson Chu <nelson.chu@sifive.com> + + * config/tc-riscv.c (riscv_ip): New boolean insn_with_csr to indicate + we are assembling instruction with CSR. Call riscv_csr_read_only_check + after parsing all arguments. + (enum csr_insn_type): New enum is used to classify the CSR instruction. + (riscv_csr_insn_type, riscv_csr_read_only_check): New functions. These + are used to check if we write a read-only CSR by the CSR instruction. + * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: New testcase. Test + all CSR for the read-only CSR checking. + * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise. + * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. + * testsuite/gas/riscv/priv-reg-fail-read-only-02.s: New testcase. Test + all CSR instructions for the read-only CSR checking. + * testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise. + * testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise. + + * config/tc-riscv.c (struct riscv_set_options): New field csr_check. + (riscv_opts): Initialize it. + (reg_lookup_internal): Check the `riscv_opts.csr_check` + before doing the CSR checking. + (enum options): Add OPTION_CSR_CHECK and OPTION_NO_CSR_CHECK. + (md_longopts): Add mcsr-check and mno-csr-check. + (md_parse_option): Handle new enum option values. + (s_riscv_option): Handle new long options. + * doc/c-riscv.texi: Add description for the new .option and assembler + options. + * testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsr-check` to enable + the CSR checking. + * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise. + + * config/tc-riscv.c (csr_extra_hash): New. + (enum riscv_csr_class): New enum. Used to decide + whether or not this CSR is legal in the current ISA string. + (struct riscv_csr_extra): New structure to hold all extra information + of CSR. + (riscv_init_csr_hashes): New. According to the DECLARE_CSR and + DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash. + Call hash_reg_name to insert CSR address into reg_names_hash. + (reg_csr_lookup_internal, riscv_csr_class_check): New functions. + Decide whether the CSR is valid according to the csr_extra_hash. + (reg_lookup_internal): Call reg_csr_lookup_internal for CSRs. + (init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is + not a boolean. This is same as riscv_init_csr_hash, so keep the + consistent usage. + (md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR. + * testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option. + * testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option. + * testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source + file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the + f-ext CSR are not allowed. + * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. + * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The + source file is `priv-reg.s`, and the ISA is rv64if, so the + rv32-only CSR are not allowed. + * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. + +2020-02-21 Alan Modra <amodra@gmail.com> + + * config/tc-pdp11.c (md_apply_fix): Handle BFD_RELOC_32. + (tc_gen_reloc): Only give a BAD_CASE assertion on pcrel relocs. + +2020-02-21 Alan Modra <amodra@gmail.com> + + PR 25569 + * config/obj-aout.c (obj_aout_frob_file_before_fix): Don't loop + on section size adjustment, instead perform another write if + exec header size is larger than section size. + +2020-02-19 Nelson Chu <nelson.chu@sifive.com> + + * doc/c-riscv.texi: Add the doc entries for -march-attr/ + -mno-arch-attr command line options. + +2020-02-19 Nelson Chu <nelson.chu@sifive.com> + + * testsuite/gas/riscv/c-add-addi.d: New testcase. + * testsuite/gas/riscv/c-add-addi.s: Likewise. + +2020-02-19 Sergey Belyashov <sergey.belyashov@gmail.com> + + PR 25576 + * config/tc-z80.c (md_parse_option): Do not use an underscore + prefix for local labels in SDCC compatability mode. + (z80_start_line_hook): Remove SDCC dollar label support. + * testsuite/gas/z80/sdcc.d: Update expected disassembly. + * testsuite/gas/z80/sdcc.s: Likewise. + +2020-02-19 Sergey Belyashov <sergey.belyashov@gmail.com> + + PR 25517 + * config/tc-z80.c: Add -march option. + * doc/as.texi: Update Z80 documentation. + * doc/c-z80.texi: Likewise. + * testsuite/gas/z80/ez80_adl_all.d: Update command line. + * testsuite/gas/z80/ez80_adl_suf.d: Likewise. + * testsuite/gas/z80/ez80_pref_dis.d: Likewise. + * testsuite/gas/z80/ez80_z80_all.d: Likewise. + * testsuite/gas/z80/ez80_z80_suf.d: Likewise. + * testsuite/gas/z80/gbz80_all.d: Likewise. + * testsuite/gas/z80/r800_extra.d: Likewise. + * testsuite/gas/z80/r800_ii8.d: Likewise. + * testsuite/gas/z80/r800_z80_doc.d: Likewise. + * testsuite/gas/z80/sdcc.d: Likewise. + * testsuite/gas/z80/z180.d: Likewise. + * testsuite/gas/z80/z180_z80_doc.d: Likewise. + * testsuite/gas/z80/z80_doc.d: Likewise. + * testsuite/gas/z80/z80_ii8.d: Likewise. + * testsuite/gas/z80/z80_in_f_c.d: Likewise. + * testsuite/gas/z80/z80_op_ii_ld.d: Likewise. + * testsuite/gas/z80/z80_out_c_0.d: Likewise. + * testsuite/gas/z80/z80_sli.d: Likewise. + * testsuite/gas/z80/z80n_all.d: Likewise. + * testsuite/gas/z80/z80n_reloc.d: Likewise. + +2020-02-19 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (output_insn): Mark cvtpi2ps and cvtpi2pd + with GNU_PROPERTY_X86_FEATURE_2_MMX. + * testsuite/gas/i386/i386.exp: Run property-3 and + x86-64-property-3. + * testsuite/gas/i386/property-3.d: New file. + * testsuite/gas/i386/property-3.s: Likewise. + * testsuite/gas/i386/x86-64-property-3.d: Likewise. + +2020-02-17 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (cpu_arch): Add .popcnt. + * doc/c-i386.texi: Remove abm and .abm. Add popcnt and .popcnt. + Add a tab before @samp{.sse4a}. + +2020-02-17 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (process_suffix): Don't try to guess a suffix + for AddrPrefixOpReg templates. Combine the two pieces of + addrprefixopreg handling. Reject 16-bit address reg in 64-bit + mode. + +2020-02-17 Jan Beulich <jbeulich@suse.com> + + PR gas/14439 + * config/tc-i386.c (md_assemble): Also suppress operand + swapping for MONITOR{,X} and MWAIT{,X}. + * testsuite/gas/i386/sse3.s, testsuite/gas/i386/x86-64-sse3.s: + Add Intel syntax monitor/mwait tests. + * testsuite/gas/i386/sse3.d, testsuite/gas/i386/x86-64-sse3.d: + Adjust expectations. + *testsuite/gas/i386/sse3-intel.d, + testsuite/gas/i386/x86-64-sse3-intel.d: New. + * testsuite/gas/i386/i386.exp: Run new tests. + +2020-02-17 Jan Beulich <jbeulich@suse.com> + + PR gas/6518 + * config/tc-i386.c (process_suffix): Re-work Intel-syntax + [XYZ]MMWord memory operand ambiguity recognition logic (largely + re-indentation). + * testsuite/gas/i386/avx512dq-inval.s: Add vcvtqq2ps/vcvtuqq2ps + cases. + * testsuite/gas/i386/inval-avx512f.s: Also test vcvtneps2bf16. + * testsuite/gas/i386/avx512dq-inval.l, + testsuite/gas/i386/inval-avx.l, + testsuite/gas/i386/inval-avx512f.l: Adjust expectations. + * testsuite/gas/i386/avx512vl-ambig.s, + testsuite/gas/i386/avx512vl-ambig.l: New. + * testsuite/gas/i386/i386.exp: Run new test. + +2020-02-16 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a. Restore + nosse4. + * doc/c-i386.texi: Document sse4a and nosse4a. + +2020-02-14 H.J. Lu <hongjiu.lu@intel.com> + + * doc/c-i386.texi: Remove the old movsx and movzx documentation + for AT&T syntax. + +2020-02-14 Jan Beulich <jbeulich@suse.com> + + PR gas/25438 + * config/tc-i386.c (md_assemble): Move movsx/movzx special + casing ... + (process_suffix): ... here. Consider just the first operand + initially. + (check_long_reg): Drop opcode 0x63 special case again. + * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s, + testsuite/gas/i386/ilp32/x86-64.s, testsuite/gas/i386/x86_64.s: + Move ambiguous operand size tests ... + * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, + testsuite/gas/i386/noreg64.s: ... here. + * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d + testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d, + testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, + testsuite/gas/i386/movx16.l, testsuite/gas/i386/movx32.l, + testsuite/gas/i386/movx64.l, testsuite/gas/i386/noreg16.d, + testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d, + testsuite/gas/i386/x86-64-movsxd.d, + testsuite/gas/i386/x86-64-movsxd-intel.d, + testsuite/gas/i386/x86_64.d, testsuite/gas/i386/x86_64-intel.d: + Adjust expectations. + * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l, + testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l, + testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New. + * testsuite/gas/i386/i386.exp: Run new tests. + +2020-02-14 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (process_operands): Also skip segment + override prefix emission if it matches an already present one. + * testsuite/gas/i386/prefix32.s: Add double segment override + cases. + * testsuite/gas/i386/prefix32.l: Adjust expectations. + +2020-02-14 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (process_operands): Drop ineffectual segment + overrides when optimizing. + * testsuite/gas/i386/lea-optimize.d: New. + * testsuite/gas/i386/i386.exp: Run new test. + +2020-02-14 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (process_operands): Also check insn prefix + for ineffectual segment override warning. Don't cover possible + VEX/EVEX encoded insns there. + * testsuite/gas/i386/lea.s, testsuite/gas/i386/lea.d, + testsuite/gas/i386/lea.e: New. + * testsuite/gas/i386/i386.exp: Run new test. + +2020-02-14 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/25438 + * doc/c-i386.texi: Document movsx, movsxd and movzx for AT&T + syntax. + +2020-02-13 Fangrui Song <maskray@google.com> + H.J. Lu <hongjiu.lu@intel.com> + + PR gas/25551 + * config/tc-i386.c (tc_i386_fix_adjustable): Don't check + BFD_RELOC_386_PLT32 nor BFD_RELOC_X86_64_PLT32. + * testsuite/gas/i386/i386.exp: Run relax-5 and x86-64-relax-4. + * testsuite/gas/i386/relax-5.d: New file. + * testsuite/gas/i386/relax-5.s: Likewise. + * testsuite/gas/i386/x86-64-relax-4.d: Likewise. + * testsuite/gas/i386/x86-64-relax-4.s: Likewise. + +2020-02-13 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (cpu_noarch): Use CPU_ANY_SSE4_FLAGS in + "nosse4" entry. + +2020-02-12 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (avx512): New (at file scope), moved from + (check_VecOperands): ... here. + (process_suffix): Add [XYZ]MMword operand size handling. + * testsuite/gas/i386/avx512dq-inval.s: Add VFPCLASS tests. + * testsuite/gas/i386/noavx512-2.s: Add Intel syntax VFPCLASS + tests. + * testsuite/gas/i386/avx512dq-inval.l, + testsuite/gas/i386/noavx512-2.l: Adjust expectations. + +2020-02-12 Jan Beulich <jbeulich@suse.com> + + PR gas/24546 + * config/tc-i386.c (match_template): Apply AMD64 check to 64-bit + code only. + * config/tc-i386-intel.c (i386_intel_operand): Also handle + CALL/JMP in O_tbyte_ptr case. + * doc/c-i386.texi: Mention far call and full pointer load ISA + differences. + * testsuite/gas/i386/x86-64-branch-3.s, + testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases. + * testsuite/gas/i386/x86-64-branch-3.d, + testsuite/gas/i386/x86-64-intel64.d: Adjust expectations. + * testsuite/gas/i386/x86-64-branch-5.l, + testsuite/gas/i386/x86-64-branch-5.s: New. + * testsuite/gas/i386/i386.exp: Run new test. + +2020-02-12 Jan Beulich <jbeulich@suse.com> + + PR gas/25438 + * config/tc-i386.c (REGISTER_WARNINGS): Delete. + (check_byte_reg): Skip only source operand of CRC32. Drop Non- + 64-bit-only warning. + (check_word_reg): Consistently error on mismatching register + size and suffix. + * testsuite/gas/i386/general.s: Replace dword GPR with word one + for movw. Replace suffix / GPR for orb. + * testsuite/gas/i386/inval.s: Add tests for movw with dword and + byte GPRs as well as ones for inb/outb with a word accumulator. + * testsuite/gas/i386/general.l, testsuite/gas/i386/intelbad.l, + testsuite/gas/i386/inval.l: Adjust expectations. + +2020-02-12 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (operand_type_register_match): Also fall + through initial two if()-s when the template allows for a GPR + operand. Adjust comment. + +2020-02-11 Jan Beulich <jbeulich@suse.com> + + (struct _i386_insn): New field "short_form". + (optimize_encoding): Drop setting of shortform field. + (process_suffix): Set i.short_form. Replace shortform use. + (process_operands): Replace shortform use. + +2020-02-11 Matthew Malcomson <matthew.malcomson@arm.com> + + * config/tc-arm.c (vcx_handle_register_arguments): Remove `for` + loop initial declaration. + +2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> + + * config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for + instructions that can have 5 arguments. + (enum operand_parse_code): Add new operands. + (parse_operands): Account for new operands. + (S5): New macro. + (enum neon_shape_el): Introduce P suffixes for coprocessor. + (neon_select_shape): Account for P suffix. + (LOW1): Move macro to global position. + (HI4): Move macro to global position. + (vcx_assign_vec_d): New. + (vcx_assign_vec_m): New. + (vcx_assign_vec_n): New. + (enum vcx_reg_type): New. + (vcx_get_reg_type): New. + (vcx_size_pos): New. + (vcx_vec_pos): New. + (vcx_handle_shape): New. + (vcx_ensure_register_in_range): New. + (vcx_handle_register_arguments): New. + (vcx_handle_insn_block): New. + (vcx_handle_common_checks): New. + (do_vcx1): New. + (do_vcx2): New. + (do_vcx3): New. + * testsuite/gas/arm/cde-missing-fp.d: New test. + * testsuite/gas/arm/cde-missing-fp.l: New test. + * testsuite/gas/arm/cde-missing-mve.d: New test. + * testsuite/gas/arm/cde-missing-mve.l: New test. + * testsuite/gas/arm/cde-mve-or-neon.d: New test. + * testsuite/gas/arm/cde-mve-or-neon.s: New test. + * testsuite/gas/arm/cde-mve.s: New test. + * testsuite/gas/arm/cde-warnings.l: + * testsuite/gas/arm/cde-warnings.s: + * testsuite/gas/arm/cde.d: + * testsuite/gas/arm/cde.s: + +2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> + Matthew Malcomson <matthew.malcomson@arm.com> + + * config/tc-arm.c (arm_ext_cde*): New feature sets for each + CDE coprocessor that can be enabled. + (enum pred_instruction_type): New pred type. + (BAD_NO_VPT): New error message. + (BAD_CDE): New error message. + (BAD_CDE_COPROC): New error message. + (enum operand_parse_code): Add new immediate operands. + (parse_operands): Account for new immediate operands. + (check_cde_operand): New. + (cde_coproc_enabled): New. + (cde_coproc_pos): New. + (cde_handle_coproc): New. + (cxn_handle_predication): New. + (do_custom_instruction_1): New. + (do_custom_instruction_2): New. + (do_custom_instruction_3): New. + (do_cx1): New. + (do_cx1a): New. + (do_cx1d): New. + (do_cx1da): New. + (do_cx2): New. + (do_cx2a): New. + (do_cx2d): New. + (do_cx2da): New. + (do_cx3): New. + (do_cx3a): New. + (do_cx3d): New. + (do_cx3da): New. + (handle_pred_state): Define new IT block behaviour. + (insns): Add newn CX*{,d}{,a} instructions. + (CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table): + Define new cdecp extension strings. + * doc/c-arm.texi: Document new cdecp extension arguments. + * testsuite/gas/arm/cde-scalar.d: New test. + * testsuite/gas/arm/cde-scalar.s: New test. + * testsuite/gas/arm/cde-warnings.d: New test. + * testsuite/gas/arm/cde-warnings.l: New test. + * testsuite/gas/arm/cde-warnings.s: New test. + * testsuite/gas/arm/cde.d: New test. + * testsuite/gas/arm/cde.s: New test. + +2020-02-10 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/25516 + * config/tc-i386.c (intel64): Renamed to ... + (isa64): This. + (match_template): Accept Intel64 only instruction by default. + (i386_displacement): Updated. + (md_parse_option): Updated. + * c-i386.texi: Update -mamd64/-mintel64 documentation. + * testsuite/gas/i386/i386.exp: Run x86-64-sysenter. Pass + -mamd64 to x86-64-sysenter-amd. + * testsuite/gas/i386/x86-64-sysenter.d: New file. + +2020-02-10 Alan Modra <amodra@gmail.com> + + * config/obj-elf.c (obj_elf_change_section): Error for section + type, attr or entsize changes in assembly. + * testsuite/gas/elf/elf.exp: Pass -Z to gas for section5 test. + * testsuite/gas/elf/section5.l: Update. + +2020-02-10 Alan Modra <amodra@gmail.com> + + * output-file.c (output_file_close): Do a normal close when + flag_always_generate_output. + * write.c (write_object_file): Don't stop output when + flag_always_generate_output. + +2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com> + + PR 25469 + * config/tc-z80.c: Add -gbz80 command line option to generate code + for the GameBoy Z80. Add support for generating DWARF. + * config/tc-z80.h: Add support for DWARF debug information + generation. + * doc/c-z80.texi: Document new command line option. + * testsuite/gas/z80/gbz80_all.d: New file. + * testsuite/gas/z80/gbz80_all.s: New file. + * testsuite/gas/z80/z80.exp: Run the new tests. + * testsuite/gas/z80/z80n_all.d: New file. + * testsuite/gas/z80/z80n_all.s: New file. + * testsuite/gas/z80/z80n_reloc.d: New file. + +2020-02-06 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/25381 + * config/obj-elf.c (get_section): Also check + linked_to_symbol_name. + (obj_elf_change_section): Also set map_head.linked_to_symbol_name. + (obj_elf_parse_section_letters): Handle the 'o' flag. + (build_group_lists): Renamed to ... + (build_additional_section_info): This. Set elf_linked_to_section + from map_head.linked_to_symbol_name. + (elf_adjust_symtab): Updated. + * config/obj-elf.h (elf_section_match): Add linked_to_symbol_name. + * doc/as.texi: Document the 'o' flag. + * testsuite/gas/elf/elf.exp: Run PR gas/25381 tests. + * testsuite/gas/elf/section18.d: New file. + * testsuite/gas/elf/section18.s: Likewise. + * testsuite/gas/elf/section19.d: Likewise. + * testsuite/gas/elf/section19.s: Likewise. + * testsuite/gas/elf/section20.d: Likewise. + * testsuite/gas/elf/section20.s: Likewise. + * testsuite/gas/elf/section21.d: Likewise. + * testsuite/gas/elf/section21.l: Likewise. + * testsuite/gas/elf/section21.s: Likewise. + +2020-02-06 H.J. Lu <hongjiu.lu@intel.com> + + * NEWS: Mention x86 assembler options to align branches for + binutils 2.34. + +2020-02-06 H.J. Lu <hongjiu.lu@intel.com> + + * testsuite/gas/i386/i386.exp: Run unique and x86-64-unique + only for ELF targets. + * testsuite/gas/i386/unique.d: Don't xfail. + * testsuite/gas/i386/x86-64-unique.d: Likewise. + +2020-02-06 Alan Modra <amodra@gmail.com> + + * testsuite/gas/i386/unique.d: xfail for non-elf targets. + * testsuite/gas/i386/x86-64-unique.d: Likewise. + +2020-02-06 Alan Modra <amodra@gmail.com> + + * testsuite/gas/elf/section12a.d: Use supports_gnu_osabi in + xfail, and rename test. + * testsuite/gas/elf/section12b.d: Likewise. + * testsuite/gas/elf/section16a.d: Likewise. + * testsuite/gas/elf/section16b.d: Likewise. + +2020-02-02 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/25380 + * config/obj-elf.c (section_match): Removed. + (get_section): Also match SEC_ASSEMBLER_SECTION_ID and + section_id. + (obj_elf_change_section): Replace info and group_name arguments + with match_p. Also update the section ID and flags from match_p. + (obj_elf_section): Handle "unique,N". Update call to + obj_elf_change_section. + * config/obj-elf.h (elf_section_match): New. + (obj_elf_change_section): Updated. + * config/tc-arm.c (start_unwind_section): Update call to + obj_elf_change_section. + * config/tc-ia64.c (obj_elf_vms_common): Likewise. + * config/tc-microblaze.c (microblaze_s_data): Likewise. + (microblaze_s_sdata): Likewise. + (microblaze_s_rdata): Likewise. + (microblaze_s_bss): Likewise. + * config/tc-mips.c (s_change_section): Likewise. + * config/tc-msp430.c (msp430_profiler): Likewise. + * config/tc-rx.c (parse_rx_section): Likewise. + * config/tc-tic6x.c (tic6x_start_unwind_section): Likewise. + * doc/as.texi: Document "unique,N" in .section directive. + * testsuite/gas/elf/elf.exp: Run "unique,N" tests. + * testsuite/gas/elf/section15.d: New file. + * testsuite/gas/elf/section15.s: Likewise. + * testsuite/gas/elf/section16.s: Likewise. + * testsuite/gas/elf/section16a.d: Likewise. + * testsuite/gas/elf/section16b.d: Likewise. + * testsuite/gas/elf/section17.d: Likewise. + * testsuite/gas/elf/section17.l: Likewise. + * testsuite/gas/elf/section17.s: Likewise. + * testsuite/gas/i386/unique.d: Likewise. + * testsuite/gas/i386/unique.s: Likewise. + * testsuite/gas/i386/x86-64-unique.d: Likewise. + * testsuite/gas/i386/i386.exp: Run unique and x86-64-unique. + +2020-02-02 H.J. Lu <hongjiu.lu@intel.com> + + * testsuite/gas/elf/section13.s: Replace @nobits with %nobits. + +2020-02-01 Anthony Green <green@moxielogic.com> + + * config/tc-moxie.c (md_begin): Don't force big-endian mode. + +2020-01-31 Sandra Loosemore <sandra@codesourcery.com> + + * config/tc-nios2.c (nios2_cons): Handle %gotoff as well as + %tls_ldo. + +2020-01-31 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR gas/25472 + * config/tc-arm.c (armv8m_main_ext_table): Refactored +dsp adding. + (armv8_1m_main_ext_table): Refactored +dsp adding and enabled dsp for + +mve. + * testsuite/gas/arm/mve_dsp.d: New test. + +2020-01-31 Nick Clifton <nickc@redhat.com> + + * config/tc-s390.c (s390_elf_suffix): Return ELF_SUFFIX_NONE + rather than BFD_RELOC_NONE. + +2020-01-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com> + + * config/tc-arm.c (fldmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2" + to support VLDMIA instruction for MVE. + (fldmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VLDMDB + instruction for MVE. + (fstmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMIA + instruction for MVE. + (fstmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMDB + instruction for MVE. + * testsuite/gas/arm/mve-ldst.d: New test. + * testsuite/gas/arm/mve-ldst.s: Likewise. + +2020-01-31 Nick Clifton <nickc@redhat.com> + + * po/fr.po: Updated French translation. + * po/ru.po: Updated Russian translation. + +2020-01-31 Richard Sandiford <richard.sandiford@arm.com> + + * testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than + .s for the movprfx. + * testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly. + * testsuite/gas/aarch64/sve-movprfx_28.d, + * testsuite/gas/aarch64/sve-movprfx_28.l, + * testsuite/gas/aarch64/sve-movprfx_28.s: New test. + +2020-01-30 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (output_disp): Tighten base_opcode check. + * testsuite/gas/i386/got.s: Add LSL, MOVLPS, and BNDCN cases. + * testsuite/gas/i386/got-no-relax.d, testsuite/gas/i386/got.d: + Adjust expectations. + +2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> + + * testsuite/gas/bpf/alu.d: Update expected opcode for `neg'. + * testsuite/gas/bpf/alu-be.d: Likewise. + * testsuite/gas/bpf/alu32.d: Likewise for `neg32'. + * testsuite/gas/bpf/alu32-be.d: Likewise. + +2020-01-30 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/x86-64-branch-2.s, + testsuite/gas/i386/x86-64-branch-4.s, + testsuite/gas/i386/x86-64-branch.s: Add RETW cases. + * testsuite/gas/i386/ilp32/x86-64-branch.d, + testsuite/gas/i386/x86-64-branch-2.d, + testsuite/gas/i386/x86-64-branch-4.l, + testsuite/gas/i386/x86-64-branch.d: Adjust expectations. + +2020-01-30 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (process_suffix): . + testsuite/gas/i386/noreg64.s: Add IRET and LRET cases. + testsuite/gas/i386/x86-64-opcode.s: Add suffix to IRET and LRET. + Add LRETQ case. + testsuite/gas/i386/x86-64-suffix.s: Drop IRET case without + suffix. + testsuite/gas/i386/x86_64.s: Add RETF cases. + * testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, + testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.l, + testsuite/gas/i386/x86-64-opcode.d, + testsuite/gas/i386/x86-64-suffix-intel.d, + testsuite/gas/i386/x86-64-suffix.d, + testsuite/gas/i386/x86_64-intel.d + testsuite/gas/i386/x86_64.d: Adjust expectations. + * testsuite/gas/i386/x86-64-suffix.e, + testsuite/gas/i386/x86_64.e: New. + +2020-01-30 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (process_suffix): Redo and move FLDENV et al + special case. + +2020-01-27 H.J. Lu <hongjiu.lu@intel.com> + + PR binutils/25445 + * config/tc-i386.c (check_long_reg): Also convert to QWORD for + movsxd. + * doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA + differences. Document movslq and movsxd. + * testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests. + * testsuite/gas/i386/x86-64-movsxd-intel.d: New file. + * testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise. + * testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise. + * testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise. + * testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise. + * testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise. + * testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise. + * testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise. + * testsuite/gas/i386/x86-64-movsxd.d: Likewise. + * testsuite/gas/i386/x86-64-movsxd.s: Likewise. + +2020-01-27 Alan Modra <amodra@gmail.com> + + * testsuite/gas/all/gas.exp: Replace case statements with switch + statements. + * testsuite/gas/elf/elf.exp: Likewise. + * testsuite/gas/macros/macros.exp: Likewise. + * testsuite/lib/gas-defs.exp: Likewise. + +2020-01-27 Tamar Christina <tamar.christina@arm.com> + + PR 25403 + * testsuite/gas/aarch64/armv8_4-a.d: Add cfinv. + * testsuite/gas/aarch64/armv8_4-a.s: Likewise. + +2020-01-22 Maxim Blinov <maxim.blinov@embecosm.com> + + * testsuite/gas/riscv/march-ok-s.d: sx is no longer valid and + s exts must be known, so rename *ok* to *fail*. + * testsuite/gas/riscv/march-ok-sx.d: Likewise. + * testsuite/gas/riscv/march-ok-s-with-version: Likewise. + * testsuite/gas/riscv/march-fail-s.l: Expected error messages for + above change. + * testsuite/gas/riscv/march-fail-sx.l: Likewise. + * testsuite/gas/riscv/march-fail-sx-with-version.l: Likewise. + +2020-01-22 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/25438 + * config/tc-i386.c (check_long_reg): Always disallow double word + suffix in mnemonic with word general register. + * testsuite/gas/i386/general.s: Replace word general register + with double word general register for movl. + * testsuite/gas/i386/inval.s: Add tests for movl with word general + register. + * testsuite/gas/i386/general.l: Updated. + * testsuite/gas/i386/inval.l: Likewise. + +2020-01-22 Alan Modra <amodra@gmail.com> + + * config/tc-ppc.c (parse_tls_arg): Handle tls arg for + __tls_get_addr_desc and __tls_get_addr_opt. + +2020-01-21 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/inval-crc32.s, + testsuite/gas/i386/x86-64-inval-crc32.s: Add alignment directive. + * testsuite/gas/i386/inval-crc32.l, + testsuite/gas/i386/x86-64-inval-crc32.l: Adjust expectations. + +2020-01-21 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (process_suffix): Merge CRC32 handling into + generic code path. Deal with No_lSuf being set in a template. + * testsuite/gas/i386/inval-crc32.l, + testsuite/gas/i386/x86-64-inval-crc32.l: Expect warning(s) + instead of error(s) when operand size is ambiguous. + * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, + testsuite/gas/i386/noreg64.s: Add CRC32 tests. + * testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg16.l, + testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg32.l, + testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.l: + Adjust expectations. + +2020-01-21 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (process_suffix): Drop SYSRET special case + and an intel_syntax check. Re-write lack-of-suffix processing + logic. + * doc/c-i386.texi: Document operand size defaults for suffix- + less AT&T syntax insns. + * testsuite/gas/i386/bundle.s, testsuite/gas/i386/lock-1.s, + testsuite/gas/i386/opcode.s, testsuite/gas/i386/sse3.s, + testsuite/gas/i386/x86-64-avx-scalar.s, + testsuite/gas/i386/x86-64-avx.s, + testsuite/gas/i386/x86-64-bundle.s, + testsuite/gas/i386/x86-64-intel64.s, + testsuite/gas/i386/x86-64-lock-1.s, + testsuite/gas/i386/x86-64-opcode.s, + testsuite/gas/i386/x86-64-sse2avx.s, + testsuite/gas/i386/x86-64-sse3.s: Add missing suffixes. + * testsuite/gas/i386/nops.s, testsuite/gas/i386/sse-noavx.s, + testsuite/gas/i386/x86-64-nops.s, + testsuite/gas/i386/x86-64-ptwrite.s, + testsuite/gas/i386/x86-64-simd.s, + testsuite/gas/i386/x86-64-sse-noavx.s, + testsuite/gas/i386/x86-64-suffix.s: Drop bogus suffix-less + insns. + * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, + testsuite/gas/i386/noreg64.s: Add further tests. + * testsuite/gas/i386/ilp32/x86-64-nops.d, + testsuite/gas/i386/nops.d, testsuite/gas/i386/noreg16.d, + testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d, + testsuite/gas/i386/sse-noavx.d, + testsuite/gas/i386/x86-64-intel64.d, + testsuite/gas/i386/x86-64-nops.d, + testsuite/gas/i386/x86-64-opcode.d, + testsuite/gas/i386/x86-64-ptwrite-intel.d, + testsuite/gas/i386/x86-64-ptwrite.d, + testsuite/gas/i386/x86-64-simd-intel.d, + testsuite/gas/i386/x86-64-simd-suffix.d, + testsuite/gas/i386/x86-64-simd.d, + testsuite/gas/i386/x86-64-sse-noavx.d + testsuite/gas/i386/x86-64-suffix.d, + testsuite/gas/i386/x86-64-suffix-intel.d: Adjust expectations. + * testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.l, + testsuite/gas/i386/noreg64.l: New. + * testsuite/gas/i386/i386.exp: Run new tests. + +2020-01-21 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/avx512_bf16_vl.s, + testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Add broadcast forms + of VCVTNEPS2BF16{X,Y}. Add operand-size less Intel syntax + broadcast forms of VCVTNEPS2BF16. + * testsuite/gas/i386/avx512_bf16_vl.d, + testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Adjust expectations. + +2020-01-20 Nick Clifton <nickc@redhat.com> + + * po/uk.po: Updated Ukranian translation. + +2020-01-20 H.J. Lu <hongjiu.lu@intel.com> + + PR ld/25416 + * config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix + for lea with R_X86_64_GOTPC32_TLSDESC relocation when generating + x32 object. + * testsuite/gas/i386/ilp32/x32-tls.d: Updated. + * testsuite/gas/i386/ilp32/x32-tls.s: Add tests for lea with + R_X86_64_GOTPC32_TLSDESC relocation. + +2020-01-18 Nick Clifton <nickc@redhat.com> + + * configure: Regenerate. + * po/gas.pot: Regenerate. + +2020-01-18 Nick Clifton <nickc@redhat.com> + + Binutils 2.34 branch created. + +2020-01-17 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2 + with vex_encoding_vex. + (parse_insn): Likewise. + * doc/c-i386.texi: Replace {vex2} with {vex}. Update {vex} + and {vex3} documentation. + * testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with + {vex}. + * testsuite/gas/i386/x86-64-pseudos.s: Likewise. + +2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR 25376 + * config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH. + (armv8_1m_main_ext_table): Use CORE_HIGH for mve. + * testsuite/arm/armv8_1-m-fpu-mve-1.s: New. + * testsuite/arm/armv8_1-m-fpu-mve-1.d: New. + * testsuite/arm/armv8_1-m-fpu-mve-2.s: New. + * testsuite/arm/armv8_1-m-fpu-mve-2.d: New. + +2020-01-16 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (match_template): Drop found_cpu_match local + variable. + +2020-01-16 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/avx512dq-inval.l, + testsuite/gas/i386/avx512dq-inval.s: New. + * testsuite/gas/i386/i386.exp: Run new test. + +2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> + + * config/tc-msp430.c (CHECK_RELOC_MSP430): Always generate 430X + relocations when the target is 430X, except when extracting part of an + expression. + (msp430_srcoperand): Adjust comment. + Initialize the expp member of the msp430_operand_s struct as + appropriate. + (msp430_dstoperand): Likewise. + * testsuite/gas/msp430/msp430.exp: Run new test. + * testsuite/gas/msp430/reloc-lo-430x.d: New test. + * testsuite/gas/msp430/reloc-lo-430x.s: New test. + +2020-01-15 Alan Modra <amodra@gmail.com> + + * configure.tgt: Add sparc-*-freebsd case. + +2020-01-14 Lili Cui <lili.cui@intel.com> + + * testsuite/gas/i386/align-branch-1a.d: Updated for Darwin. + * testsuite/gas/i386/align-branch-1b.d: Likewise. + * testsuite/gas/i386/align-branch-1c.d: Likewise. + * testsuite/gas/i386/align-branch-1d.d: Likewise. + * testsuite/gas/i386/align-branch-1e.d: Likewise. + * testsuite/gas/i386/align-branch-1f.d: Likewise. + * testsuite/gas/i386/align-branch-1g.d: Likewise. + * testsuite/gas/i386/align-branch-1h.d: Likewise. + * testsuite/gas/i386/align-branch-1i.d: Likewise. + * testsuite/gas/i386/align-branch-5.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-1e.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-1f.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-1h.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-1i.d: Likewise. + * testsuite/gas/i386/x86-64-align-branch-5.d: Likewise. + * testsuite/gas/i386/i386.exp: Skip x86-64-align-branch-2a, + x86-64-align-branch-2b and x86-64-align-branch-2c on Darwin. + +2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com> + + PR 25377 + * config/tc-z80.c: Add support for half precision, single + precision and double precision floating point values. + * config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes. + * doc/as.texi: Add new z80 command line options. + * doc/c-z80.texi: Document new z80 command line options. + * testsuite/gas/z80/ez80_pref_dis.s: New test. + * testsuite/gas/z80/ez80_pref_dis.d: New test driver. + * testsuite/gas/z80/z80.exp: Run the new test. + * testsuite/gas/z80/fp_math48.d: Use correct command line option. + * testsuite/gas/z80/fp_zeda32.d: Likewise. + * testsuite/gas/z80/strings.d: Update expected output. + +2020-01-13 Matthew Malcomson <matthew.malcomson@arm.com> + + * config/tc-aarch64.c (f64mm, f32mm): Add sve as a feature + dependency. + +2020-01-13 Claudiu Zissulescu <claziss@gmail.com> + + * config/tc-arc.c (arc_select_cpu): Re-init the bfd if we change + the CPU. + * config/tc-arc.h: Add header if/defs. + * testsuite/gas/arc/pseudos.d: Improve matching pattern. + +2020-01-13 Alan Modra <amodra@gmail.com> + + * testsuite/gas/wasm32/allinsn.d: Update expected output. + +2020-01-13 Alan Modra <amodra@gmail.com> + + * config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap + insertion. + +2020-01-10 Alan Modra <amodra@gmail.com> + + * testsuite/gas/elf/pr14891.s: Don't start directives in first column. + * testsuite/gas/elf/pr21661.d: Don't run on hpux. + +2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com> + + PR 25224 + * config/tc-z80.c (emit_ld_m_rr): Use integer types when checking + opcode byte values. + (emit_ld_r_r): Likewise. + (emit_ld_rr_m): Likewise. + (emit_ld_rr_nn): Likewise. + +2020-01-09 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (optimize_encoding): Add + is_any_vex_encoding() invocations. Drop respective + i.tm.extension_opcode == None checks. + +2020-01-09 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (md_assemble): Check RegRex is clear during + REX transformations. Correct comment indentation. + +2020-01-09 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (optimize_encoding): Generalize register + transformation for TEST optimization. + +2020-01-09 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/x86-64-sysenter-amd.s, + testsuite/gas/i386/x86-64-sysenter-amd.d, + testsuite/gas/i386/x86-64-sysenter-amd.l, + testsuite/gas/i386/x86-64-sysenter-intel.d, + testsuite/gas/i386/x86-64-sysenter-mixed.d: New. + * testsuite/gas/i386/i386.exp: Run new tests. + +2020-01-08 Nick Clifton <nickc@redhat.com> + + PR 25284 + * doc/as.texi (Align): Document the fact that all arguments can be + omitted. + (Balign): Likewise. + (P2align): Likewise. + +2020-01-08 Nick Clifton <nickc@redhat.com> + + PR 14891 + * config/obj-elf.c (obj_elf_section): Fail if the section name is + already defined as a different symbol type. + * testsuite/gas/elf/pr14891.s: New test source file. + * testsuite/gas/elf/pr14891.d: New test driver. + * testsuite/gas/elf/pr14891.s: New test expected error output. + * testsuite/gas/elf/elf.exp: Run the new test. + +2020-01-08 Alan Modra <amodra@gmail.com> + + * config/tc-z8k.c (md_begin): Make idx unsigned. + (get_specific): Likewise for this_index. + +2020-01-07 Claudiu Zissulescu <claziss@synopsys.com> + + * onfig/tc-arc.c (parse_reloc_symbol): New function. + (tokenize_arguments): Clean up, use parse_reloc_symbol function. + (md_operand): Set X_md to absent. + (arc_parse_name): Check for X_md. + +2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com> + + PR 25311 + * as.h (TC_STRING_ESCAPES): Provide a default definition. + * app.c (do_scrub_chars): Use TC_STRING_ESCAPES instead of + NO_STRING_ESCAPES. + * read.c (next_char_of_string): Likewise. + * config/tc-ppc.h (TC_STRING_ESCAPES): Define. + * config/tc-z80.h (TC_STRING_ESCAPES): Define. + +2020-01-03 Nick Clifton <nickc@redhat.com> + + * po/sv.po: Updated Swedish translation. + +2020-01-03 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/aarch64/f64mm.s: Scale index of LD1RO{H,W,D}. + * testsuite/gas/aarch64/f64mm.d: Adjust expectations. + +2020-01-03 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/aarch64/i8mm.s: Add 128-bit form tests for + by-element usdot. Add 64-bit form tests for by-element sudot. + * testsuite/gas/aarch64/i8mm.d: Adjust expectations. + +2020-01-03 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/aarch64/f64mm.s: Drop 'i' from uzip<n>. + * testsuite/gas/aarch64/f64mm.d: Adjust expectations. + +2020-01-03 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/aarch64/f64mm.d, + testsuite/gas/aarch64/sve-movprfx-mm.d: Adjust expectations. + +2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com> + + * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add + support for assembler code generated by SDCC. Add new relocation + types. Add z80-elf target support. + * config/tc-z80.h: Add z80-elf target support. Enable dollar local + labels. Local labels starts from ".L". + * NEWS: Mention the new support. + * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. + * testsuite/gas/all/fwdexp.s: Likewise. + * testsuite/gas/all/cond.l: Likewise. + * testsuite/gas/all/cond.s: Likewise. + * testsuite/gas/all/fwdexp.d: Likewise. + * testsuite/gas/all/fwdexp.s: Likewise. + * testsuite/gas/elf/section2.e-mips: Likewise. + * testsuite/gas/elf/section2.l: Likewise. + * testsuite/gas/elf/section2.s: Likewise. + * testsuite/gas/macros/app1.d: Likewise. + * testsuite/gas/macros/app1.s: Likewise. + * testsuite/gas/macros/app2.d: Likewise. + * testsuite/gas/macros/app2.s: Likewise. + * testsuite/gas/macros/app3.d: Likewise. + * testsuite/gas/macros/app3.s: Likewise. + * testsuite/gas/macros/app4.d: Likewise. + * testsuite/gas/macros/app4.s: Likewise. + * testsuite/gas/macros/app4b.s: Likewise. + * testsuite/gas/z80/suffix.d: Fix failure on ELF target. + * testsuite/gas/z80/z80.exp: Add new tests + * testsuite/gas/z80/dollar.d: New file. + * testsuite/gas/z80/dollar.s: New file. + * testsuite/gas/z80/ez80_adl_all.d: New file. + * testsuite/gas/z80/ez80_adl_all.s: New file. + * testsuite/gas/z80/ez80_adl_suf.d: New file. + * testsuite/gas/z80/ez80_isuf.s: New file. + * testsuite/gas/z80/ez80_z80_all.d: New file. + * testsuite/gas/z80/ez80_z80_all.s: New file. + * testsuite/gas/z80/ez80_z80_suf.d: New file. + * testsuite/gas/z80/r800_extra.d: New file. + * testsuite/gas/z80/r800_extra.s: New file. + * testsuite/gas/z80/r800_ii8.d: New file. + * testsuite/gas/z80/r800_z80_doc.d: New file. + * testsuite/gas/z80/z180.d: New file. + * testsuite/gas/z80/z180.s: New file. + * testsuite/gas/z80/z180_z80_doc.d: New file. + * testsuite/gas/z80/z80_doc.d: New file. + * testsuite/gas/z80/z80_doc.s: New file. + * testsuite/gas/z80/z80_ii8.d: New file. + * testsuite/gas/z80/z80_ii8.s: New file. + * testsuite/gas/z80/z80_in_f_c.d: New file. + * testsuite/gas/z80/z80_in_f_c.s: New file. + * testsuite/gas/z80/z80_op_ii_ld.d: New file. + * testsuite/gas/z80/z80_op_ii_ld.s: New file. + * testsuite/gas/z80/z80_out_c_0.d: New file. + * testsuite/gas/z80/z80_out_c_0.s: New file. + * testsuite/gas/z80/z80_reloc.d: New file. + * testsuite/gas/z80/z80_reloc.s: New file. + * testsuite/gas/z80/z80_sli.d: New file. + * testsuite/gas/z80/z80_sli.s: New file. + +2020-01-02 Szabolcs Nagy <szabolcs.nagy@arm.com> + + * config/tc-arm.c (parse_reg_list): Use REG_TYPE_RN instead of + REGLIST_RN. + +2020-01-01 Alan Modra <amodra@gmail.com> + + Update year range in copyright notice of all files. + +For older changes see ChangeLog-2019 + +Copyright (C) 2020 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: |