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| author | Stafford Horne <shorne@gmail.com> | 2019-06-13 06:16:18 +0900 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2019-06-13 06:16:18 +0900 |
| commit | 6ce26ac7c381c78858b9a7bac344b5cd04bfb03e (patch) | |
| tree | 87569f01173efe774eb0ee4c470f78f4b0b08af7 /cpu/or1korbis.cpu | |
| parent | a0e44ef56c4d1a20785fe3bcb368638d1af148cf (diff) | |
| download | gdb-6ce26ac7c381c78858b9a7bac344b5cd04bfb03e.zip gdb-6ce26ac7c381c78858b9a7bac344b5cd04bfb03e.tar.gz gdb-6ce26ac7c381c78858b9a7bac344b5cd04bfb03e.tar.bz2 | |
cpu/or1k: Add support for orfp64a32 spec
This patch adds support for OpenRISC 64-bit FPU operations on 32-bit cores by
using register pairs. The functionality has been added to OpenRISC architecture
specification version 1.3 as per architecture proposal 14[0].
For supporting assembly of both 64-bit and 32-bit precision instructions we have
defined CGEN_VALIDATE_INSN_SUPPORTED. This allows cgen to use 64-bit bit
architecture assembly parsing on 64-bit toolchains and 32-bit architecture
assembly parsing on 32-bit toolchains. Without this the assembler has issues
parsing register pairs.
This patch also contains a few fixes to the symantics for existing OpenRISC
single and double precision FPU operations.
[0] https://openrisc.io/proposals/orfpx64a32
cpu/ChangeLog:
yyyy-mm-dd Andrey Bacherov <avbacherov@opencores.org>
Stafford Horne <shorne@gmail.com>
* or1k.cpu (ORFPX64A32-MACHS): New pmacro.
(ORFPX-MACHS): Removed pmacro.
* or1k.opc (or1k_cgen_insn_supported): New function.
(CGEN_VALIDATE_INSN_SUPPORTED): Define macro.
(parse_regpair, print_regpair): New functions.
* or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder
and add comments.
(h-fdr): Update comment to indicate or64.
(reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs.
(h-fd32r): New hardware for 64-bit fpu registers.
(h-i64r): New hardware for 64-bit int registers.
* or1korbis.cpu (f-resv-8-1): New field.
* or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS.
(rDDF, rADF, rBDF): Update operand comment to indicate or64.
(f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields.
(h-roff1): New hardware.
(double-field-and-ops mnemonic): New pmacro to generate operations
rDD32F, rAD32F, rBD32F, rDDI and rADI.
(float-regreg-insn): Update single precision generator to MACH
ORFPX32-MACHS. Add generator for or32 64-bit instructions.
(float-setflag-insn): Update single precision generator to MACH
ORFPX32-MACHS. Fix double instructions from single to double
precision. Add generator for or32 64-bit instructions.
(float-cust-insn cust-num): Update single precision generator to MACH
ORFPX32-MACHS. Add generator for or32 64-bit instructions.
(lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to
ORFPX32-MACHS.
(lf-rem-d): Fix operation from mod to rem.
(lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction.
(lf-itof-d): Fix operands from single to double.
(lf-ftoi-d): Update operand mode from DI to WI.
Diffstat (limited to 'cpu/or1korbis.cpu')
| -rw-r--r-- | cpu/or1korbis.cpu | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/cpu/or1korbis.cpu b/cpu/or1korbis.cpu index 094f018..308f378 100644 --- a/cpu/or1korbis.cpu +++ b/cpu/or1korbis.cpu @@ -61,6 +61,7 @@ (dnf f-resv-10-7 "resv-10-7" ((MACH ORBIS-MACHS) RESERVED) 10 7) (dnf f-resv-10-3 "resv-10-3" ((MACH ORBIS-MACHS) RESERVED) 10 3) (dnf f-resv-10-1 "resv-10-1" ((MACH ORBIS-MACHS) RESERVED) 10 1) +(dnf f-resv-8-1 "resv-8-1" ((MACH ORBIS-MACHS) RESERVED) 8 1) (dnf f-resv-7-4 "resv-7-4" ((MACH ORBIS-MACHS) RESERVED) 7 4) (dnf f-resv-5-2 "resv-5-2" ((MACH ORBIS-MACHS) RESERVED) 5 2) |