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authorMaciej W. Rozycki <macro@imgtec.com>2017-06-28 02:07:36 +0100
committerMaciej W. Rozycki <macro@imgtec.com>2017-06-28 02:07:36 +0100
commit38bf472a15210c222bb3885820e763c47760a704 (patch)
tree71d1b3d93f6a6f8d85fb4b1ff4a099fcf468b6a3 /binutils
parent9991e9d77fe04c4fde9b88964c6f25119a781e0d (diff)
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MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with the MIPS16e2 ASE as per documentation, including in particular: 1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW MIPS16e2 instructions[1], for assembly and disassembly, 2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE regular MIPS instructions[2], for assembly and disassembly, 3. ELF binary file annotation for the interAptiv MR2 MIPS architecture extension. 4. Support for interAptiv MR2 architecture selection for assembly, in the form of the `-march=interaptiv-mr2' command-line option and its corresponding `arch=interaptiv-mr2' setting for the `.set' and `.module' pseudo-ops. 5. Support for interAptiv MR2 architecture selection for disassembly, in the form of the `mips:interaptiv-mr2' target architecture, for use e.g. with the `-m' command-line option for `objdump'. Parts of this change by Matthew Fortune and Andrew Bennett. References: [1] "MIPS32 interAptiv Multiprocessing System Software User's Manual", Imagination Technologies Ltd., Document Number: MD00904, Revision 02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific Instructions", pp. 878-883 [2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917 include/ * elf/mips.h (E_MIPS_MACH_IAMR2): New macro. (AFL_EXT_INTERAPTIV_MR2): Likewise. * opcode/mips.h: Document new operand codes defined. (INSN_INTERAPTIV_MR2): New macro. (INSN_CHIP_MASK): Adjust accordingly. (CPU_INTERAPTIV_MR2): New macro. (cpu_is_member) <CPU_INTERAPTIV_MR2>: New case. (MIPS16_ALL_ARGS): Rename to... (MIPS_SVRS_ALL_ARGS): ... this. (MIPS16_ALL_STATICS): Rename to... (MIPS_SVRS_ALL_STATICS): ... this. bfd/ * archures.c (bfd_mach_mips_interaptiv_mr2): New macro. * cpu-mips.c (I_interaptiv_mr2): New enum value. (arch_info_struct): Add "mips:interaptiv-mr2" entry. * elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New case. (mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise. (bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise. (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise. (mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and `bfd_mach_mips_interaptiv_mr2' entries. * bfd-in2.h: Regenerate. opcodes/ * mips-formats.h (INT_BIAS): New macro. (INT_ADJ): Redefine in INT_BIAS terms. * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry. (mips_print_save_restore): New function. (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment. (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort' call. (print_insn_args): Handle OP_SAVE_RESTORE_LIST. (print_mips16_insn_arg): Call `mips_print_save_restore' for OP_SAVE_RESTORE_LIST handling, factored out from here. * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case. (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros. (mips_builtin_opcodes): Add "restore" and "save" entries. * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases. (IAMR2): New macro. (mips16_opcodes): Add "copyw" and "ucopyw" entries. binutils/ * readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case. (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise. * NEWS: Mention Imagination interAptiv MR2 processor support. gas/ * config/tc-mips.c (validate_mips_insn): Handle OP_SAVE_RESTORE_LIST specially. (mips_encode_save_restore, mips16_encode_save_restore): New functions. (match_save_restore_list_operand): Factor out SAVE/RESTORE operand insertion into the instruction word or halfword to these new functions. (mips_cpu_info_table): Add "interaptiv-mr2" entry. * doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the `-march=' argument list.
Diffstat (limited to 'binutils')
-rw-r--r--binutils/ChangeLog7
-rw-r--r--binutils/NEWS4
-rw-r--r--binutils/readelf.c4
3 files changed, 15 insertions, 0 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index af2a348..da3cf67 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,10 @@
+2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
+ Matthew Fortune <matthew.fortune@imgtec.com>
+
+ * readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case.
+ (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
+ * NEWS: Mention Imagination interAptiv MR2 processor support.
+
2017-06-26 Nick Clifton <nickc@redhat.com>
PR binutils/21665
diff --git a/binutils/NEWS b/binutils/NEWS
index 753d17f..b49e2d3 100644
--- a/binutils/NEWS
+++ b/binutils/NEWS
@@ -1,5 +1,9 @@
-*- text -*-
+* The MIPS port now supports the Imagination interAptiv MR2 processor,
+ which implements the MIPS32r3 ISA, the MIPS16e2 ASE as well as a couple
+ of implementation-specific regular MIPS and MIPS16e2 ASE instructions.
+
* The SPARC port now supports the SPARC M8 processor, which implements the
Oracle SPARC Architecture 2017.
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 916c6cb..edfe652 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -3334,6 +3334,7 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
+ case E_MIPS_MACH_IAMR2: strcat (buf, ", interaptiv-mr2"); break;
case 0:
/* We simply ignore the field in this case to avoid confusion:
MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
@@ -15131,6 +15132,9 @@ print_mips_isa_ext (unsigned int isa_ext)
case AFL_EXT_LOONGSON_2F:
fputs ("ST Microelectronics Loongson 2F", stdout);
break;
+ case AFL_EXT_INTERAPTIV_MR2:
+ fputs ("Imagination interAptiv MR2", stdout);
+ break;
default:
fprintf (stdout, "%s (%d)", _("Unknown"), isa_ext);
}