Fix verilog output when the width is > 1.

	PR 25202
bfd	* bfd.c (VerilogDataEndianness): New variable.
	(verilog_write_record): Use VerilogDataEndianness, if set, to
	choose the endianness of the output.
	(verilog_write_section): Adjust the address by the data width.

binutils* objcopy.c (copy_object): Set VerilogDataEndianness to the
	endianness of the input file.
	(copy_main): Verifiy the value set by the --verilog-data-width
	option.
	* testsuite/binutils-all/objcopy.exp: Add tests of the new behaviour.
	* testsuite/binutils-all/verilog-I4.hex: New file.

1 files changed, 19 insertions, 4 deletions

diff --git a/bfd/verilog.c b/bfd/verilog.c
index baf0e04..52c42c5 100644
--- a/bfd/verilog.c
+++ b/bfd/verilog.c
@@ -62,6 +62,10 @@
    Data width in bytes.  */
 unsigned int VerilogDataWidth = 1;
 
+/* Modified by obcopy.c
+   Data endianness.  */
+enum bfd_endian VerilogDataEndianness = BFD_ENDIAN_UNKNOWN;
+
 /* Macros for converting between hex and binary.  */
 
 static const char digs[] = "0123456789ABCDEF";
@@ -105,7 +109,7 @@ verilog_set_arch_mach (bfd *abfd, enum bfd_architecture arch, unsigned long mach
   return true;
 }
 
-/* We have to save up all the outpu for a splurge before output.  */
+/* We have to save up all the output for a splurge before output.  */
 
 static bool
 verilog_set_section_contents (bfd *abfd,
@@ -238,7 +242,8 @@ verilog_write_record (bfd *abfd,
 	    *dst++ = ' ';
 	}
     }
-  else if (bfd_little_endian (abfd))
+  else if ((VerilogDataEndianness == BFD_ENDIAN_UNKNOWN && bfd_little_endian (abfd)) /* FIXME: Can this happen ?  */
+	   || (VerilogDataEndianness == BFD_ENDIAN_LITTLE))
     {
       /* If the input byte stream contains:
 	   05 04 03 02 01 00
@@ -263,8 +268,10 @@ verilog_write_record (bfd *abfd,
 	  TOHEX (dst, *end);
 	  dst += 2;
 	}
+
+      /* FIXME: Should padding bytes be inserted here ?  */
     }
-  else
+  else /* Big endian output.  */
     {
       for (src = data; src < end;)
 	{
@@ -274,6 +281,7 @@ verilog_write_record (bfd *abfd,
 	  if ((src - data) % VerilogDataWidth == 0)
 	    *dst++ = ' ';
 	}
+      /* FIXME: Should padding bytes be inserted here ?  */
     }
 
   *dst++ = '\r';
@@ -291,7 +299,14 @@ verilog_write_section (bfd *abfd,
   unsigned int octets_written = 0;
   bfd_byte *location = list->data;
 
-  verilog_write_address (abfd, list->where);
+  /* Insist that the starting address is a multiple of the data width.  */
+  if (list->where % VerilogDataWidth)
+    {
+      bfd_set_error (bfd_error_invalid_operation);
+      return false;
+    }
+
+  verilog_write_address (abfd, list->where / VerilogDataWidth);
   while (octets_written < list->size)
     {
       unsigned int octets_this_chunk = list->size - octets_written;